Lines Matching +full:sdm845 +full:- +full:dispcc
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
13 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
14 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sm8150.h>
17 #include <dt-bindings/thermal/thermal.h>
20 interrupt-parent = <&intc>;
22 #address-cells = <2>;
23 #size-cells = <2>;
28 xo_board: xo-board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <38400000>;
32 clock-output-names = "xo_board";
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32764>;
39 clock-output-names = "sleep_clk";
44 #address-cells = <2>;
45 #size-cells = <0>;
52 enable-method = "psci";
53 capacity-dmips-mhz = <488>;
54 dynamic-power-coefficient = <232>;
55 next-level-cache = <&L2_0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
57 operating-points-v2 = <&cpu0_opp_table>;
60 power-domains = <&CPU_PD0>;
61 power-domain-names = "psci";
62 #cooling-cells = <2>;
63 L2_0: l2-cache {
65 cache-level = <2>;
66 cache-unified;
67 next-level-cache = <&L3_0>;
68 L3_0: l3-cache {
70 cache-level = <3>;
71 cache-unified;
81 enable-method = "psci";
82 capacity-dmips-mhz = <488>;
83 dynamic-power-coefficient = <232>;
84 next-level-cache = <&L2_100>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
86 operating-points-v2 = <&cpu0_opp_table>;
89 power-domains = <&CPU_PD1>;
90 power-domain-names = "psci";
91 #cooling-cells = <2>;
92 L2_100: l2-cache {
94 cache-level = <2>;
95 cache-unified;
96 next-level-cache = <&L3_0>;
105 enable-method = "psci";
106 capacity-dmips-mhz = <488>;
107 dynamic-power-coefficient = <232>;
108 next-level-cache = <&L2_200>;
109 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = <&cpu0_opp_table>;
113 power-domains = <&CPU_PD2>;
114 power-domain-names = "psci";
115 #cooling-cells = <2>;
116 L2_200: l2-cache {
118 cache-level = <2>;
119 cache-unified;
120 next-level-cache = <&L3_0>;
129 enable-method = "psci";
130 capacity-dmips-mhz = <488>;
131 dynamic-power-coefficient = <232>;
132 next-level-cache = <&L2_300>;
133 qcom,freq-domain = <&cpufreq_hw 0>;
134 operating-points-v2 = <&cpu0_opp_table>;
137 power-domains = <&CPU_PD3>;
138 power-domain-names = "psci";
139 #cooling-cells = <2>;
140 L2_300: l2-cache {
142 cache-level = <2>;
143 cache-unified;
144 next-level-cache = <&L3_0>;
153 enable-method = "psci";
154 capacity-dmips-mhz = <1024>;
155 dynamic-power-coefficient = <369>;
156 next-level-cache = <&L2_400>;
157 qcom,freq-domain = <&cpufreq_hw 1>;
158 operating-points-v2 = <&cpu4_opp_table>;
161 power-domains = <&CPU_PD4>;
162 power-domain-names = "psci";
163 #cooling-cells = <2>;
164 L2_400: l2-cache {
166 cache-level = <2>;
167 cache-unified;
168 next-level-cache = <&L3_0>;
177 enable-method = "psci";
178 capacity-dmips-mhz = <1024>;
179 dynamic-power-coefficient = <369>;
180 next-level-cache = <&L2_500>;
181 qcom,freq-domain = <&cpufreq_hw 1>;
182 operating-points-v2 = <&cpu4_opp_table>;
185 power-domains = <&CPU_PD5>;
186 power-domain-names = "psci";
187 #cooling-cells = <2>;
188 L2_500: l2-cache {
190 cache-level = <2>;
191 cache-unified;
192 next-level-cache = <&L3_0>;
201 enable-method = "psci";
202 capacity-dmips-mhz = <1024>;
203 dynamic-power-coefficient = <369>;
204 next-level-cache = <&L2_600>;
205 qcom,freq-domain = <&cpufreq_hw 1>;
206 operating-points-v2 = <&cpu4_opp_table>;
209 power-domains = <&CPU_PD6>;
210 power-domain-names = "psci";
211 #cooling-cells = <2>;
212 L2_600: l2-cache {
214 cache-level = <2>;
215 cache-unified;
216 next-level-cache = <&L3_0>;
225 enable-method = "psci";
226 capacity-dmips-mhz = <1024>;
227 dynamic-power-coefficient = <421>;
228 next-level-cache = <&L2_700>;
229 qcom,freq-domain = <&cpufreq_hw 2>;
230 operating-points-v2 = <&cpu7_opp_table>;
233 power-domains = <&CPU_PD7>;
234 power-domain-names = "psci";
235 #cooling-cells = <2>;
236 L2_700: l2-cache {
238 cache-level = <2>;
239 cache-unified;
240 next-level-cache = <&L3_0>;
244 cpu-map {
280 idle-states {
281 entry-method = "psci";
283 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
284 compatible = "arm,idle-state";
285 idle-state-name = "little-rail-power-collapse";
286 arm,psci-suspend-param = <0x40000004>;
287 entry-latency-us = <355>;
288 exit-latency-us = <909>;
289 min-residency-us = <3934>;
290 local-timer-stop;
293 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
294 compatible = "arm,idle-state";
295 idle-state-name = "big-rail-power-collapse";
296 arm,psci-suspend-param = <0x40000004>;
297 entry-latency-us = <241>;
298 exit-latency-us = <1461>;
299 min-residency-us = <4488>;
300 local-timer-stop;
304 domain-idle-states {
305 CLUSTER_SLEEP_0: cluster-sleep-0 {
306 compatible = "domain-idle-state";
307 arm,psci-suspend-param = <0x4100c244>;
308 entry-latency-us = <3263>;
309 exit-latency-us = <6562>;
310 min-residency-us = <9987>;
315 cpu0_opp_table: opp-table-cpu0 {
316 compatible = "operating-points-v2";
317 opp-shared;
319 cpu0_opp1: opp-300000000 {
320 opp-hz = /bits/ 64 <300000000>;
321 opp-peak-kBps = <800000 9600000>;
324 cpu0_opp2: opp-403200000 {
325 opp-hz = /bits/ 64 <403200000>;
326 opp-peak-kBps = <800000 9600000>;
329 cpu0_opp3: opp-499200000 {
330 opp-hz = /bits/ 64 <499200000>;
331 opp-peak-kBps = <800000 12902400>;
334 cpu0_opp4: opp-576000000 {
335 opp-hz = /bits/ 64 <576000000>;
336 opp-peak-kBps = <800000 12902400>;
339 cpu0_opp5: opp-672000000 {
340 opp-hz = /bits/ 64 <672000000>;
341 opp-peak-kBps = <800000 15974400>;
344 cpu0_opp6: opp-768000000 {
345 opp-hz = /bits/ 64 <768000000>;
346 opp-peak-kBps = <1804000 19660800>;
349 cpu0_opp7: opp-844800000 {
350 opp-hz = /bits/ 64 <844800000>;
351 opp-peak-kBps = <1804000 19660800>;
354 cpu0_opp8: opp-940800000 {
355 opp-hz = /bits/ 64 <940800000>;
356 opp-peak-kBps = <1804000 22732800>;
359 cpu0_opp9: opp-1036800000 {
360 opp-hz = /bits/ 64 <1036800000>;
361 opp-peak-kBps = <1804000 22732800>;
364 cpu0_opp10: opp-1113600000 {
365 opp-hz = /bits/ 64 <1113600000>;
366 opp-peak-kBps = <2188000 25804800>;
369 cpu0_opp11: opp-1209600000 {
370 opp-hz = /bits/ 64 <1209600000>;
371 opp-peak-kBps = <2188000 31948800>;
374 cpu0_opp12: opp-1305600000 {
375 opp-hz = /bits/ 64 <1305600000>;
376 opp-peak-kBps = <3072000 31948800>;
379 cpu0_opp13: opp-1382400000 {
380 opp-hz = /bits/ 64 <1382400000>;
381 opp-peak-kBps = <3072000 31948800>;
384 cpu0_opp14: opp-1478400000 {
385 opp-hz = /bits/ 64 <1478400000>;
386 opp-peak-kBps = <3072000 31948800>;
389 cpu0_opp15: opp-1555200000 {
390 opp-hz = /bits/ 64 <1555200000>;
391 opp-peak-kBps = <3072000 40550400>;
394 cpu0_opp16: opp-1632000000 {
395 opp-hz = /bits/ 64 <1632000000>;
396 opp-peak-kBps = <3072000 40550400>;
399 cpu0_opp17: opp-1708800000 {
400 opp-hz = /bits/ 64 <1708800000>;
401 opp-peak-kBps = <3072000 43008000>;
404 cpu0_opp18: opp-1785600000 {
405 opp-hz = /bits/ 64 <1785600000>;
406 opp-peak-kBps = <3072000 43008000>;
410 cpu4_opp_table: opp-table-cpu4 {
411 compatible = "operating-points-v2";
412 opp-shared;
414 cpu4_opp1: opp-710400000 {
415 opp-hz = /bits/ 64 <710400000>;
416 opp-peak-kBps = <1804000 15974400>;
419 cpu4_opp2: opp-825600000 {
420 opp-hz = /bits/ 64 <825600000>;
421 opp-peak-kBps = <2188000 19660800>;
424 cpu4_opp3: opp-940800000 {
425 opp-hz = /bits/ 64 <940800000>;
426 opp-peak-kBps = <2188000 22732800>;
429 cpu4_opp4: opp-1056000000 {
430 opp-hz = /bits/ 64 <1056000000>;
431 opp-peak-kBps = <3072000 25804800>;
434 cpu4_opp5: opp-1171200000 {
435 opp-hz = /bits/ 64 <1171200000>;
436 opp-peak-kBps = <3072000 31948800>;
439 cpu4_opp6: opp-1286400000 {
440 opp-hz = /bits/ 64 <1286400000>;
441 opp-peak-kBps = <4068000 31948800>;
444 cpu4_opp7: opp-1401600000 {
445 opp-hz = /bits/ 64 <1401600000>;
446 opp-peak-kBps = <4068000 31948800>;
449 cpu4_opp8: opp-1497600000 {
450 opp-hz = /bits/ 64 <1497600000>;
451 opp-peak-kBps = <4068000 40550400>;
454 cpu4_opp9: opp-1612800000 {
455 opp-hz = /bits/ 64 <1612800000>;
456 opp-peak-kBps = <4068000 40550400>;
459 cpu4_opp10: opp-1708800000 {
460 opp-hz = /bits/ 64 <1708800000>;
461 opp-peak-kBps = <4068000 43008000>;
464 cpu4_opp11: opp-1804800000 {
465 opp-hz = /bits/ 64 <1804800000>;
466 opp-peak-kBps = <6220000 43008000>;
469 cpu4_opp12: opp-1920000000 {
470 opp-hz = /bits/ 64 <1920000000>;
471 opp-peak-kBps = <6220000 49152000>;
474 cpu4_opp13: opp-2016000000 {
475 opp-hz = /bits/ 64 <2016000000>;
476 opp-peak-kBps = <7216000 49152000>;
479 cpu4_opp14: opp-2131200000 {
480 opp-hz = /bits/ 64 <2131200000>;
481 opp-peak-kBps = <8368000 49152000>;
484 cpu4_opp15: opp-2227200000 {
485 opp-hz = /bits/ 64 <2227200000>;
486 opp-peak-kBps = <8368000 51609600>;
489 cpu4_opp16: opp-2323200000 {
490 opp-hz = /bits/ 64 <2323200000>;
491 opp-peak-kBps = <8368000 51609600>;
494 cpu4_opp17: opp-2419200000 {
495 opp-hz = /bits/ 64 <2419200000>;
496 opp-peak-kBps = <8368000 51609600>;
500 cpu7_opp_table: opp-table-cpu7 {
501 compatible = "operating-points-v2";
502 opp-shared;
504 cpu7_opp1: opp-825600000 {
505 opp-hz = /bits/ 64 <825600000>;
506 opp-peak-kBps = <2188000 19660800>;
509 cpu7_opp2: opp-940800000 {
510 opp-hz = /bits/ 64 <940800000>;
511 opp-peak-kBps = <2188000 22732800>;
514 cpu7_opp3: opp-1056000000 {
515 opp-hz = /bits/ 64 <1056000000>;
516 opp-peak-kBps = <3072000 25804800>;
519 cpu7_opp4: opp-1171200000 {
520 opp-hz = /bits/ 64 <1171200000>;
521 opp-peak-kBps = <3072000 31948800>;
524 cpu7_opp5: opp-1286400000 {
525 opp-hz = /bits/ 64 <1286400000>;
526 opp-peak-kBps = <4068000 31948800>;
529 cpu7_opp6: opp-1401600000 {
530 opp-hz = /bits/ 64 <1401600000>;
531 opp-peak-kBps = <4068000 31948800>;
534 cpu7_opp7: opp-1497600000 {
535 opp-hz = /bits/ 64 <1497600000>;
536 opp-peak-kBps = <4068000 40550400>;
539 cpu7_opp8: opp-1612800000 {
540 opp-hz = /bits/ 64 <1612800000>;
541 opp-peak-kBps = <4068000 40550400>;
544 cpu7_opp9: opp-1708800000 {
545 opp-hz = /bits/ 64 <1708800000>;
546 opp-peak-kBps = <4068000 43008000>;
549 cpu7_opp10: opp-1804800000 {
550 opp-hz = /bits/ 64 <1804800000>;
551 opp-peak-kBps = <6220000 43008000>;
554 cpu7_opp11: opp-1920000000 {
555 opp-hz = /bits/ 64 <1920000000>;
556 opp-peak-kBps = <6220000 49152000>;
559 cpu7_opp12: opp-2016000000 {
560 opp-hz = /bits/ 64 <2016000000>;
561 opp-peak-kBps = <7216000 49152000>;
564 cpu7_opp13: opp-2131200000 {
565 opp-hz = /bits/ 64 <2131200000>;
566 opp-peak-kBps = <8368000 49152000>;
569 cpu7_opp14: opp-2227200000 {
570 opp-hz = /bits/ 64 <2227200000>;
571 opp-peak-kBps = <8368000 51609600>;
574 cpu7_opp15: opp-2323200000 {
575 opp-hz = /bits/ 64 <2323200000>;
576 opp-peak-kBps = <8368000 51609600>;
579 cpu7_opp16: opp-2419200000 {
580 opp-hz = /bits/ 64 <2419200000>;
581 opp-peak-kBps = <8368000 51609600>;
584 cpu7_opp17: opp-2534400000 {
585 opp-hz = /bits/ 64 <2534400000>;
586 opp-peak-kBps = <8368000 51609600>;
589 cpu7_opp18: opp-2649600000 {
590 opp-hz = /bits/ 64 <2649600000>;
591 opp-peak-kBps = <8368000 51609600>;
594 cpu7_opp19: opp-2745600000 {
595 opp-hz = /bits/ 64 <2745600000>;
596 opp-peak-kBps = <8368000 51609600>;
599 cpu7_opp20: opp-2841600000 {
600 opp-hz = /bits/ 64 <2841600000>;
601 opp-peak-kBps = <8368000 51609600>;
607 compatible = "qcom,scm-sm8150", "qcom,scm";
608 #reset-cells = <1>;
619 compatible = "arm,armv8-pmuv3";
624 compatible = "arm,psci-1.0";
627 CPU_PD0: power-domain-cpu0 {
628 #power-domain-cells = <0>;
629 power-domains = <&CLUSTER_PD>;
630 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
633 CPU_PD1: power-domain-cpu1 {
634 #power-domain-cells = <0>;
635 power-domains = <&CLUSTER_PD>;
636 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
639 CPU_PD2: power-domain-cpu2 {
640 #power-domain-cells = <0>;
641 power-domains = <&CLUSTER_PD>;
642 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
645 CPU_PD3: power-domain-cpu3 {
646 #power-domain-cells = <0>;
647 power-domains = <&CLUSTER_PD>;
648 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
651 CPU_PD4: power-domain-cpu4 {
652 #power-domain-cells = <0>;
653 power-domains = <&CLUSTER_PD>;
654 domain-idle-states = <&BIG_CPU_SLEEP_0>;
657 CPU_PD5: power-domain-cpu5 {
658 #power-domain-cells = <0>;
659 power-domains = <&CLUSTER_PD>;
660 domain-idle-states = <&BIG_CPU_SLEEP_0>;
663 CPU_PD6: power-domain-cpu6 {
664 #power-domain-cells = <0>;
665 power-domains = <&CLUSTER_PD>;
666 domain-idle-states = <&BIG_CPU_SLEEP_0>;
669 CPU_PD7: power-domain-cpu7 {
670 #power-domain-cells = <0>;
671 power-domains = <&CLUSTER_PD>;
672 domain-idle-states = <&BIG_CPU_SLEEP_0>;
675 CLUSTER_PD: power-domain-cpu-cluster0 {
676 #power-domain-cells = <0>;
677 domain-idle-states = <&CLUSTER_SLEEP_0>;
681 reserved-memory {
682 #address-cells = <2>;
683 #size-cells = <2>;
688 no-map;
693 no-map;
698 no-map;
702 compatible = "qcom,cmd-db";
704 no-map;
709 no-map;
714 no-map;
718 compatible = "qcom,rmtfs-mem";
720 no-map;
722 qcom,client-id = <1>;
728 no-map;
733 no-map;
738 no-map;
743 no-map;
748 no-map;
753 no-map;
758 no-map;
763 no-map;
768 no-map;
773 no-map;
778 no-map;
783 no-map;
788 no-map;
794 memory-region = <&smem_mem>;
798 smp2p-cdsp {
806 qcom,local-pid = <0>;
807 qcom,remote-pid = <5>;
809 cdsp_smp2p_out: master-kernel {
810 qcom,entry-name = "master-kernel";
811 #qcom,smem-state-cells = <1>;
814 cdsp_smp2p_in: slave-kernel {
815 qcom,entry-name = "slave-kernel";
817 interrupt-controller;
818 #interrupt-cells = <2>;
822 smp2p-lpass {
830 qcom,local-pid = <0>;
831 qcom,remote-pid = <2>;
833 adsp_smp2p_out: master-kernel {
834 qcom,entry-name = "master-kernel";
835 #qcom,smem-state-cells = <1>;
838 adsp_smp2p_in: slave-kernel {
839 qcom,entry-name = "slave-kernel";
841 interrupt-controller;
842 #interrupt-cells = <2>;
846 smp2p-mpss {
854 qcom,local-pid = <0>;
855 qcom,remote-pid = <1>;
857 modem_smp2p_out: master-kernel {
858 qcom,entry-name = "master-kernel";
859 #qcom,smem-state-cells = <1>;
862 modem_smp2p_in: slave-kernel {
863 qcom,entry-name = "slave-kernel";
865 interrupt-controller;
866 #interrupt-cells = <2>;
870 smp2p-slpi {
878 qcom,local-pid = <0>;
879 qcom,remote-pid = <3>;
881 slpi_smp2p_out: master-kernel {
882 qcom,entry-name = "master-kernel";
883 #qcom,smem-state-cells = <1>;
886 slpi_smp2p_in: slave-kernel {
887 qcom,entry-name = "slave-kernel";
889 interrupt-controller;
890 #interrupt-cells = <2>;
895 #address-cells = <2>;
896 #size-cells = <2>;
898 dma-ranges = <0 0 0 0 0x10 0>;
899 compatible = "simple-bus";
901 gcc: clock-controller@100000 {
902 compatible = "qcom,gcc-sm8150";
904 #clock-cells = <1>;
905 #reset-cells = <1>;
906 #power-domain-cells = <1>;
907 clock-names = "bi_tcxo",
913 gpi_dma0: dma-controller@800000 {
914 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
929 dma-channels = <13>;
930 dma-channel-mask = <0xfa>;
932 #dma-cells = <3>;
937 compatible = "qcom,sm8150-ethqos";
940 reg-names = "stmmaceth", "rgmii";
941 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
948 interrupt-names = "macirq", "eth_lpi";
950 power-domains = <&gcc EMAC_GDSC>;
956 rx-fifo-depth = <4096>;
957 tx-fifo-depth = <4096>;
963 compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
965 #address-cells = <1>;
966 #size-cells = <1>;
975 compatible = "qcom,geni-se-qup";
977 clock-names = "m-ahb", "s-ahb";
981 #address-cells = <2>;
982 #size-cells = <2>;
987 compatible = "qcom,geni-i2c";
989 clock-names = "se";
993 dma-names = "tx", "rx";
994 pinctrl-names = "default";
995 pinctrl-0 = <&qup_i2c0_default>;
997 #address-cells = <1>;
998 #size-cells = <0>;
1003 compatible = "qcom,geni-spi";
1005 reg-names = "se";
1006 clock-names = "se";
1010 dma-names = "tx", "rx";
1011 pinctrl-names = "default";
1012 pinctrl-0 = <&qup_spi0_default>;
1014 spi-max-frequency = <50000000>;
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1021 compatible = "qcom,geni-i2c";
1023 clock-names = "se";
1027 dma-names = "tx", "rx";
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&qup_i2c1_default>;
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1037 compatible = "qcom,geni-spi";
1039 reg-names = "se";
1040 clock-names = "se";
1044 dma-names = "tx", "rx";
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&qup_spi1_default>;
1048 spi-max-frequency = <50000000>;
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1055 compatible = "qcom,geni-i2c";
1057 clock-names = "se";
1061 dma-names = "tx", "rx";
1062 pinctrl-names = "default";
1063 pinctrl-0 = <&qup_i2c2_default>;
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1071 compatible = "qcom,geni-spi";
1073 reg-names = "se";
1074 clock-names = "se";
1078 dma-names = "tx", "rx";
1079 pinctrl-names = "default";
1080 pinctrl-0 = <&qup_spi2_default>;
1082 spi-max-frequency = <50000000>;
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1089 compatible = "qcom,geni-i2c";
1091 clock-names = "se";
1095 dma-names = "tx", "rx";
1096 pinctrl-names = "default";
1097 pinctrl-0 = <&qup_i2c3_default>;
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1105 compatible = "qcom,geni-spi";
1107 reg-names = "se";
1108 clock-names = "se";
1112 dma-names = "tx", "rx";
1113 pinctrl-names = "default";
1114 pinctrl-0 = <&qup_spi3_default>;
1116 spi-max-frequency = <50000000>;
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1123 compatible = "qcom,geni-i2c";
1125 clock-names = "se";
1129 dma-names = "tx", "rx";
1130 pinctrl-names = "default";
1131 pinctrl-0 = <&qup_i2c4_default>;
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1139 compatible = "qcom,geni-spi";
1141 reg-names = "se";
1142 clock-names = "se";
1146 dma-names = "tx", "rx";
1147 pinctrl-names = "default";
1148 pinctrl-0 = <&qup_spi4_default>;
1150 spi-max-frequency = <50000000>;
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1157 compatible = "qcom,geni-i2c";
1159 clock-names = "se";
1163 dma-names = "tx", "rx";
1164 pinctrl-names = "default";
1165 pinctrl-0 = <&qup_i2c5_default>;
1167 #address-cells = <1>;
1168 #size-cells = <0>;
1173 compatible = "qcom,geni-spi";
1175 reg-names = "se";
1176 clock-names = "se";
1180 dma-names = "tx", "rx";
1181 pinctrl-names = "default";
1182 pinctrl-0 = <&qup_spi5_default>;
1184 spi-max-frequency = <50000000>;
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1191 compatible = "qcom,geni-i2c";
1193 clock-names = "se";
1197 dma-names = "tx", "rx";
1198 pinctrl-names = "default";
1199 pinctrl-0 = <&qup_i2c6_default>;
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1207 compatible = "qcom,geni-spi";
1209 reg-names = "se";
1210 clock-names = "se";
1214 dma-names = "tx", "rx";
1215 pinctrl-names = "default";
1216 pinctrl-0 = <&qup_spi6_default>;
1218 spi-max-frequency = <50000000>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1225 compatible = "qcom,geni-i2c";
1227 clock-names = "se";
1231 dma-names = "tx", "rx";
1232 pinctrl-names = "default";
1233 pinctrl-0 = <&qup_i2c7_default>;
1235 #address-cells = <1>;
1236 #size-cells = <0>;
1241 compatible = "qcom,geni-spi";
1243 reg-names = "se";
1244 clock-names = "se";
1248 dma-names = "tx", "rx";
1249 pinctrl-names = "default";
1250 pinctrl-0 = <&qup_spi7_default>;
1252 spi-max-frequency = <50000000>;
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1259 gpi_dma1: dma-controller@a00000 {
1260 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1275 dma-channels = <13>;
1276 dma-channel-mask = <0xfa>;
1278 #dma-cells = <3>;
1283 compatible = "qcom,geni-se-qup";
1285 clock-names = "m-ahb", "s-ahb";
1289 #address-cells = <2>;
1290 #size-cells = <2>;
1295 compatible = "qcom,geni-i2c";
1297 clock-names = "se";
1301 dma-names = "tx", "rx";
1302 pinctrl-names = "default";
1303 pinctrl-0 = <&qup_i2c8_default>;
1305 #address-cells = <1>;
1306 #size-cells = <0>;
1311 compatible = "qcom,geni-spi";
1313 reg-names = "se";
1314 clock-names = "se";
1318 dma-names = "tx", "rx";
1319 pinctrl-names = "default";
1320 pinctrl-0 = <&qup_spi8_default>;
1322 spi-max-frequency = <50000000>;
1323 #address-cells = <1>;
1324 #size-cells = <0>;
1329 compatible = "qcom,geni-i2c";
1331 clock-names = "se";
1335 dma-names = "tx", "rx";
1336 pinctrl-names = "default";
1337 pinctrl-0 = <&qup_i2c9_default>;
1339 #address-cells = <1>;
1340 #size-cells = <0>;
1345 compatible = "qcom,geni-spi";
1347 reg-names = "se";
1348 clock-names = "se";
1352 dma-names = "tx", "rx";
1353 pinctrl-names = "default";
1354 pinctrl-0 = <&qup_spi9_default>;
1356 spi-max-frequency = <50000000>;
1357 #address-cells = <1>;
1358 #size-cells = <0>;
1363 compatible = "qcom,geni-uart";
1366 clock-names = "se";
1367 pinctrl-0 = <&qup_uart9_default>;
1368 pinctrl-names = "default";
1374 compatible = "qcom,geni-i2c";
1376 clock-names = "se";
1380 dma-names = "tx", "rx";
1381 pinctrl-names = "default";
1382 pinctrl-0 = <&qup_i2c10_default>;
1384 #address-cells = <1>;
1385 #size-cells = <0>;
1390 compatible = "qcom,geni-spi";
1392 reg-names = "se";
1393 clock-names = "se";
1397 dma-names = "tx", "rx";
1398 pinctrl-names = "default";
1399 pinctrl-0 = <&qup_spi10_default>;
1401 spi-max-frequency = <50000000>;
1402 #address-cells = <1>;
1403 #size-cells = <0>;
1408 compatible = "qcom,geni-i2c";
1410 clock-names = "se";
1414 dma-names = "tx", "rx";
1415 pinctrl-names = "default";
1416 pinctrl-0 = <&qup_i2c11_default>;
1418 #address-cells = <1>;
1419 #size-cells = <0>;
1424 compatible = "qcom,geni-spi";
1426 reg-names = "se";
1427 clock-names = "se";
1431 dma-names = "tx", "rx";
1432 pinctrl-names = "default";
1433 pinctrl-0 = <&qup_spi11_default>;
1435 spi-max-frequency = <50000000>;
1436 #address-cells = <1>;
1437 #size-cells = <0>;
1442 compatible = "qcom,geni-debug-uart";
1444 clock-names = "se";
1451 compatible = "qcom,geni-i2c";
1453 clock-names = "se";
1457 dma-names = "tx", "rx";
1458 pinctrl-names = "default";
1459 pinctrl-0 = <&qup_i2c12_default>;
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1467 compatible = "qcom,geni-spi";
1469 reg-names = "se";
1470 clock-names = "se";
1474 dma-names = "tx", "rx";
1475 pinctrl-names = "default";
1476 pinctrl-0 = <&qup_spi12_default>;
1478 spi-max-frequency = <50000000>;
1479 #address-cells = <1>;
1480 #size-cells = <0>;
1485 compatible = "qcom,geni-i2c";
1487 clock-names = "se";
1491 dma-names = "tx", "rx";
1492 pinctrl-names = "default";
1493 pinctrl-0 = <&qup_i2c16_default>;
1495 #address-cells = <1>;
1496 #size-cells = <0>;
1501 compatible = "qcom,geni-spi";
1503 reg-names = "se";
1504 clock-names = "se";
1508 dma-names = "tx", "rx";
1509 pinctrl-names = "default";
1510 pinctrl-0 = <&qup_spi16_default>;
1512 spi-max-frequency = <50000000>;
1513 #address-cells = <1>;
1514 #size-cells = <0>;
1519 gpi_dma2: dma-controller@c00000 {
1520 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1535 dma-channels = <13>;
1536 dma-channel-mask = <0xfa>;
1538 #dma-cells = <3>;
1543 compatible = "qcom,geni-se-qup";
1546 clock-names = "m-ahb", "s-ahb";
1550 #address-cells = <2>;
1551 #size-cells = <2>;
1556 compatible = "qcom,geni-i2c";
1558 clock-names = "se";
1562 dma-names = "tx", "rx";
1563 pinctrl-names = "default";
1564 pinctrl-0 = <&qup_i2c17_default>;
1566 #address-cells = <1>;
1567 #size-cells = <0>;
1572 compatible = "qcom,geni-spi";
1574 reg-names = "se";
1575 clock-names = "se";
1579 dma-names = "tx", "rx";
1580 pinctrl-names = "default";
1581 pinctrl-0 = <&qup_spi17_default>;
1583 spi-max-frequency = <50000000>;
1584 #address-cells = <1>;
1585 #size-cells = <0>;
1590 compatible = "qcom,geni-i2c";
1592 clock-names = "se";
1596 dma-names = "tx", "rx";
1597 pinctrl-names = "default";
1598 pinctrl-0 = <&qup_i2c18_default>;
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1606 compatible = "qcom,geni-spi";
1608 reg-names = "se";
1609 clock-names = "se";
1613 dma-names = "tx", "rx";
1614 pinctrl-names = "default";
1615 pinctrl-0 = <&qup_spi18_default>;
1617 spi-max-frequency = <50000000>;
1618 #address-cells = <1>;
1619 #size-cells = <0>;
1624 compatible = "qcom,geni-i2c";
1626 clock-names = "se";
1630 dma-names = "tx", "rx";
1631 pinctrl-names = "default";
1632 pinctrl-0 = <&qup_i2c19_default>;
1634 #address-cells = <1>;
1635 #size-cells = <0>;
1640 compatible = "qcom,geni-spi";
1642 reg-names = "se";
1643 clock-names = "se";
1647 dma-names = "tx", "rx";
1648 pinctrl-names = "default";
1649 pinctrl-0 = <&qup_spi19_default>;
1651 spi-max-frequency = <50000000>;
1652 #address-cells = <1>;
1653 #size-cells = <0>;
1658 compatible = "qcom,geni-i2c";
1660 clock-names = "se";
1664 dma-names = "tx", "rx";
1665 pinctrl-names = "default";
1666 pinctrl-0 = <&qup_i2c13_default>;
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1674 compatible = "qcom,geni-spi";
1676 reg-names = "se";
1677 clock-names = "se";
1681 dma-names = "tx", "rx";
1682 pinctrl-names = "default";
1683 pinctrl-0 = <&qup_spi13_default>;
1685 spi-max-frequency = <50000000>;
1686 #address-cells = <1>;
1687 #size-cells = <0>;
1692 compatible = "qcom,geni-i2c";
1694 clock-names = "se";
1698 dma-names = "tx", "rx";
1699 pinctrl-names = "default";
1700 pinctrl-0 = <&qup_i2c14_default>;
1702 #address-cells = <1>;
1703 #size-cells = <0>;
1708 compatible = "qcom,geni-spi";
1710 reg-names = "se";
1711 clock-names = "se";
1715 dma-names = "tx", "rx";
1716 pinctrl-names = "default";
1717 pinctrl-0 = <&qup_spi14_default>;
1719 spi-max-frequency = <50000000>;
1720 #address-cells = <1>;
1721 #size-cells = <0>;
1726 compatible = "qcom,geni-i2c";
1728 clock-names = "se";
1732 dma-names = "tx", "rx";
1733 pinctrl-names = "default";
1734 pinctrl-0 = <&qup_i2c15_default>;
1736 #address-cells = <1>;
1737 #size-cells = <0>;
1742 compatible = "qcom,geni-spi";
1744 reg-names = "se";
1745 clock-names = "se";
1749 dma-names = "tx", "rx";
1750 pinctrl-names = "default";
1751 pinctrl-0 = <&qup_spi15_default>;
1753 spi-max-frequency = <50000000>;
1754 #address-cells = <1>;
1755 #size-cells = <0>;
1761 compatible = "qcom,sm8150-config-noc";
1763 #interconnect-cells = <2>;
1764 qcom,bcm-voters = <&apps_bcm_voter>;
1768 compatible = "qcom,sm8150-system-noc";
1770 #interconnect-cells = <2>;
1771 qcom,bcm-voters = <&apps_bcm_voter>;
1775 compatible = "qcom,sm8150-mc-virt";
1777 #interconnect-cells = <2>;
1778 qcom,bcm-voters = <&apps_bcm_voter>;
1782 compatible = "qcom,sm8150-aggre1-noc";
1784 #interconnect-cells = <2>;
1785 qcom,bcm-voters = <&apps_bcm_voter>;
1789 compatible = "qcom,sm8150-aggre2-noc";
1791 #interconnect-cells = <2>;
1792 qcom,bcm-voters = <&apps_bcm_voter>;
1796 compatible = "qcom,sm8150-compute-noc";
1798 #interconnect-cells = <2>;
1799 qcom,bcm-voters = <&apps_bcm_voter>;
1803 compatible = "qcom,sm8150-mmss-noc";
1805 #interconnect-cells = <2>;
1806 qcom,bcm-voters = <&apps_bcm_voter>;
1809 system-cache-controller@9200000 {
1810 compatible = "qcom,sm8150-llcc";
1814 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1820 compatible = "qcom,sm8150-dcc", "qcom,dcc";
1826 compatible = "qcom,pcie-sm8150";
1832 reg-names = "parf", "dbi", "elbi", "atu", "config";
1834 linux,pci-domain = <0>;
1835 bus-range = <0x00 0xff>;
1836 num-lanes = <1>;
1838 #address-cells = <3>;
1839 #size-cells = <2>;
1845 interrupt-names = "msi";
1846 #interrupt-cells = <1>;
1847 interrupt-map-mask = <0 0 0 0x7>;
1848 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1860 clock-names = "pipe",
1868 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1872 reset-names = "pci";
1874 power-domains = <&gcc PCIE_0_GDSC>;
1877 phy-names = "pciephy";
1879 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1880 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1882 pinctrl-names = "default";
1883 pinctrl-0 = <&pcie0_default_state>;
1889 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1891 #address-cells = <2>;
1892 #size-cells = <2>;
1898 clock-names = "aux",
1904 reset-names = "phy";
1906 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1907 assigned-clock-rates = <100000000>;
1917 clock-names = "pipe0";
1919 #phy-cells = <0>;
1920 clock-output-names = "pcie_0_pipe_clk";
1925 compatible = "qcom,pcie-sm8150";
1931 reg-names = "parf", "dbi", "elbi", "atu", "config";
1933 linux,pci-domain = <1>;
1934 bus-range = <0x00 0xff>;
1935 num-lanes = <2>;
1937 #address-cells = <3>;
1938 #size-cells = <2>;
1944 interrupt-names = "msi";
1945 #interrupt-cells = <1>;
1946 interrupt-map-mask = <0 0 0 0x7>;
1947 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1959 clock-names = "pipe",
1967 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1968 assigned-clock-rates = <19200000>;
1970 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1974 reset-names = "pci";
1976 power-domains = <&gcc PCIE_1_GDSC>;
1979 phy-names = "pciephy";
1981 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
1982 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
1984 pinctrl-names = "default";
1985 pinctrl-0 = <&pcie1_default_state>;
1991 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
1993 #address-cells = <2>;
1994 #size-cells = <2>;
2000 clock-names = "aux",
2006 reset-names = "phy";
2008 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2009 assigned-clock-rates = <100000000>;
2021 clock-names = "pipe0";
2023 #phy-cells = <0>;
2024 clock-output-names = "pcie_1_pipe_clk";
2029 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2030 "jedec,ufs-2.0";
2033 reg-names = "std", "ice";
2036 phy-names = "ufsphy";
2037 lanes-per-direction = <2>;
2038 #reset-cells = <1>;
2040 reset-names = "rst";
2044 clock-names =
2064 freq-table-hz =
2079 compatible = "qcom,sm8150-qmp-ufs-phy";
2081 #address-cells = <2>;
2082 #size-cells = <2>;
2084 clock-names = "ref",
2089 power-domains = <&gcc UFS_PHY_GDSC>;
2092 reset-names = "ufsphy";
2101 #phy-cells = <0>;
2105 cryptobam: dma-controller@1dc4000 {
2106 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2109 #dma-cells = <1>;
2111 qcom,controlled-remotely;
2112 num-channels = <8>;
2113 qcom,num-ees = <2>;
2122 compatible = "qcom,sm8150-qce", "qcom,qce";
2125 dma-names = "rx", "tx";
2132 interconnect-names = "memory";
2136 compatible = "qcom,tcsr-mutex";
2138 #hwlock-cells = <1>;
2142 compatible = "qcom,sm8150-tcsr", "syscon";
2147 compatible = "qcom,sm8150-slpi-pas";
2150 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2155 interrupt-names = "wdog", "fatal", "ready",
2156 "handover", "stop-ack";
2159 clock-names = "xo";
2161 power-domains = <&rpmhpd SM8150_LCX>,
2163 power-domain-names = "lcx", "lmx";
2165 memory-region = <&slpi_mem>;
2169 qcom,smem-states = <&slpi_smp2p_out 0>;
2170 qcom,smem-state-names = "stop";
2174 glink-edge {
2177 qcom,remote-pid = <3>;
2182 qcom,glink-channels = "fastrpcglink-apps-dsp";
2184 qcom,non-secure-domain;
2185 #address-cells = <1>;
2186 #size-cells = <0>;
2188 compute-cb@1 {
2189 compatible = "qcom,fastrpc-compute-cb";
2194 compute-cb@2 {
2195 compatible = "qcom,fastrpc-compute-cb";
2200 compute-cb@3 {
2201 compatible = "qcom,fastrpc-compute-cb";
2204 /* note: shared-cb = <4> in downstream */
2211 compatible = "qcom,adreno-640.1", "qcom,adreno";
2213 reg-names = "kgsl_3d0_reg_memory";
2219 operating-points-v2 = <&gpu_opp_table>;
2223 nvmem-cells = <&gpu_speed_bin>;
2224 nvmem-cell-names = "speed_bin";
2228 zap-shader {
2229 memory-region = <&gpu_mem>;
2232 gpu_opp_table: opp-table {
2233 compatible = "operating-points-v2";
2235 opp-675000000 {
2236 opp-hz = /bits/ 64 <675000000>;
2237 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2238 opp-supported-hw = <0x2>;
2241 opp-585000000 {
2242 opp-hz = /bits/ 64 <585000000>;
2243 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2244 opp-supported-hw = <0x3>;
2247 opp-499200000 {
2248 opp-hz = /bits/ 64 <499200000>;
2249 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2250 opp-supported-hw = <0x3>;
2253 opp-427000000 {
2254 opp-hz = /bits/ 64 <427000000>;
2255 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2256 opp-supported-hw = <0x3>;
2259 opp-345000000 {
2260 opp-hz = /bits/ 64 <345000000>;
2261 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2262 opp-supported-hw = <0x3>;
2265 opp-257000000 {
2266 opp-hz = /bits/ 64 <257000000>;
2267 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2268 opp-supported-hw = <0x3>;
2274 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2279 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2283 interrupt-names = "hfi", "gmu";
2290 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2292 power-domains = <&gpucc GPU_CX_GDSC>,
2294 power-domain-names = "cx", "gx";
2298 operating-points-v2 = <&gmu_opp_table>;
2302 gmu_opp_table: opp-table {
2303 compatible = "operating-points-v2";
2305 opp-200000000 {
2306 opp-hz = /bits/ 64 <200000000>;
2307 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2312 gpucc: clock-controller@2c90000 {
2313 compatible = "qcom,sm8150-gpucc";
2318 clock-names = "bi_tcxo",
2321 #clock-cells = <1>;
2322 #reset-cells = <1>;
2323 #power-domain-cells = <1>;
2327 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2328 "qcom,smmu-500", "arm,mmu-500";
2330 #iommu-cells = <2>;
2331 #global-interrupts = <1>;
2344 clock-names = "ahb", "bus", "iface";
2346 power-domains = <&gpucc GPU_CX_GDSC>;
2350 compatible = "qcom,sm8150-pinctrl";
2355 reg-names = "west", "east", "north", "south";
2357 gpio-ranges = <&tlmm 0 0 176>;
2358 gpio-controller;
2359 #gpio-cells = <2>;
2360 interrupt-controller;
2361 #interrupt-cells = <2>;
2362 wakeup-parent = <&pdc>;
2364 qup_i2c0_default: qup-i2c0-default-state {
2367 drive-strength = <0x02>;
2368 bias-disable;
2371 qup_spi0_default: qup-spi0-default-state {
2374 drive-strength = <6>;
2375 bias-disable;
2378 qup_i2c1_default: qup-i2c1-default-state {
2381 drive-strength = <2>;
2382 bias-disable;
2385 qup_spi1_default: qup-spi1-default-state {
2388 drive-strength = <6>;
2389 bias-disable;
2392 qup_i2c2_default: qup-i2c2-default-state {
2395 drive-strength = <2>;
2396 bias-disable;
2399 qup_spi2_default: qup-spi2-default-state {
2402 drive-strength = <6>;
2403 bias-disable;
2406 qup_i2c3_default: qup-i2c3-default-state {
2409 drive-strength = <2>;
2410 bias-disable;
2413 qup_spi3_default: qup-spi3-default-state {
2416 drive-strength = <6>;
2417 bias-disable;
2420 qup_i2c4_default: qup-i2c4-default-state {
2423 drive-strength = <2>;
2424 bias-disable;
2427 qup_spi4_default: qup-spi4-default-state {
2430 drive-strength = <6>;
2431 bias-disable;
2434 qup_i2c5_default: qup-i2c5-default-state {
2437 drive-strength = <2>;
2438 bias-disable;
2441 qup_spi5_default: qup-spi5-default-state {
2444 drive-strength = <6>;
2445 bias-disable;
2448 qup_i2c6_default: qup-i2c6-default-state {
2451 drive-strength = <2>;
2452 bias-disable;
2455 qup_spi6_default: qup-spi6_default-state {
2458 drive-strength = <6>;
2459 bias-disable;
2462 qup_i2c7_default: qup-i2c7-default-state {
2465 drive-strength = <2>;
2466 bias-disable;
2469 qup_spi7_default: qup-spi7_default-state {
2472 drive-strength = <6>;
2473 bias-disable;
2476 qup_i2c8_default: qup-i2c8-default-state {
2479 drive-strength = <2>;
2480 bias-disable;
2483 qup_spi8_default: qup-spi8-default-state {
2486 drive-strength = <6>;
2487 bias-disable;
2490 qup_i2c9_default: qup-i2c9-default-state {
2493 drive-strength = <2>;
2494 bias-disable;
2497 qup_spi9_default: qup-spi9-default-state {
2500 drive-strength = <6>;
2501 bias-disable;
2504 qup_uart9_default: qup-uart9-default-state {
2507 drive-strength = <2>;
2508 bias-disable;
2511 qup_i2c10_default: qup-i2c10-default-state {
2514 drive-strength = <2>;
2515 bias-disable;
2518 qup_spi10_default: qup-spi10-default-state {
2521 drive-strength = <6>;
2522 bias-disable;
2525 qup_i2c11_default: qup-i2c11-default-state {
2528 drive-strength = <2>;
2529 bias-disable;
2532 qup_spi11_default: qup-spi11-default-state {
2535 drive-strength = <6>;
2536 bias-disable;
2539 qup_i2c12_default: qup-i2c12-default-state {
2542 drive-strength = <2>;
2543 bias-disable;
2546 qup_spi12_default: qup-spi12-default-state {
2549 drive-strength = <6>;
2550 bias-disable;
2553 qup_i2c13_default: qup-i2c13-default-state {
2556 drive-strength = <2>;
2557 bias-disable;
2560 qup_spi13_default: qup-spi13-default-state {
2563 drive-strength = <6>;
2564 bias-disable;
2567 qup_i2c14_default: qup-i2c14-default-state {
2570 drive-strength = <2>;
2571 bias-disable;
2574 qup_spi14_default: qup-spi14-default-state {
2577 drive-strength = <6>;
2578 bias-disable;
2581 qup_i2c15_default: qup-i2c15-default-state {
2584 drive-strength = <2>;
2585 bias-disable;
2588 qup_spi15_default: qup-spi15-default-state {
2591 drive-strength = <6>;
2592 bias-disable;
2595 qup_i2c16_default: qup-i2c16-default-state {
2598 drive-strength = <2>;
2599 bias-disable;
2602 qup_spi16_default: qup-spi16-default-state {
2605 drive-strength = <6>;
2606 bias-disable;
2609 qup_i2c17_default: qup-i2c17-default-state {
2612 drive-strength = <2>;
2613 bias-disable;
2616 qup_spi17_default: qup-spi17-default-state {
2619 drive-strength = <6>;
2620 bias-disable;
2623 qup_i2c18_default: qup-i2c18-default-state {
2626 drive-strength = <2>;
2627 bias-disable;
2630 qup_spi18_default: qup-spi18-default-state {
2633 drive-strength = <6>;
2634 bias-disable;
2637 qup_i2c19_default: qup-i2c19-default-state {
2640 drive-strength = <2>;
2641 bias-disable;
2644 qup_spi19_default: qup-spi19-default-state {
2647 drive-strength = <6>;
2648 bias-disable;
2651 pcie0_default_state: pcie0-default-state {
2652 perst-pins {
2655 drive-strength = <2>;
2656 bias-pull-down;
2659 clkreq-pins {
2662 drive-strength = <2>;
2663 bias-pull-up;
2666 wake-pins {
2669 drive-strength = <2>;
2670 bias-pull-up;
2674 pcie1_default_state: pcie1-default-state {
2675 perst-pins {
2678 drive-strength = <2>;
2679 bias-pull-down;
2682 clkreq-pins {
2685 drive-strength = <2>;
2686 bias-pull-up;
2689 wake-pins {
2692 drive-strength = <2>;
2693 bias-pull-up;
2699 compatible = "qcom,sm8150-mpss-pas";
2702 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2708 interrupt-names = "wdog", "fatal", "ready", "handover",
2709 "stop-ack", "shutdown-ack";
2712 clock-names = "xo";
2714 power-domains = <&rpmhpd SM8150_CX>,
2716 power-domain-names = "cx", "mss";
2718 memory-region = <&mpss_mem>;
2722 qcom,smem-states = <&modem_smp2p_out 0>;
2723 qcom,smem-state-names = "stop";
2727 glink-edge {
2730 qcom,remote-pid = <1>;
2736 compatible = "arm,coresight-stm", "arm,primecell";
2739 reg-names = "stm-base", "stm-stimulus-base";
2742 clock-names = "apb_pclk";
2744 out-ports {
2747 remote-endpoint = <&funnel0_in7>;
2754 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2758 clock-names = "apb_pclk";
2760 out-ports {
2763 remote-endpoint = <&merge_funnel_in0>;
2768 in-ports {
2769 #address-cells = <1>;
2770 #size-cells = <0>;
2775 remote-endpoint = <&stm_out>;
2782 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2786 clock-names = "apb_pclk";
2788 out-ports {
2791 remote-endpoint = <&merge_funnel_in1>;
2796 in-ports {
2797 #address-cells = <1>;
2798 #size-cells = <0>;
2803 remote-endpoint = <&swao_replicator_out>;
2810 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2814 clock-names = "apb_pclk";
2816 out-ports {
2819 remote-endpoint = <&merge_funnel_in2>;
2824 in-ports {
2825 #address-cells = <1>;
2826 #size-cells = <0>;
2831 remote-endpoint = <&apss_merge_funnel_out>;
2838 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2842 clock-names = "apb_pclk";
2844 out-ports {
2847 remote-endpoint = <&etf_in>;
2852 in-ports {
2853 #address-cells = <1>;
2854 #size-cells = <0>;
2859 remote-endpoint = <&funnel0_out>;
2866 remote-endpoint = <&funnel1_out>;
2873 remote-endpoint = <&funnel2_out>;
2880 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2884 clock-names = "apb_pclk";
2886 out-ports {
2887 #address-cells = <1>;
2888 #size-cells = <0>;
2893 remote-endpoint = <&etr_in>;
2900 remote-endpoint = <&replicator1_in>;
2905 in-ports {
2908 remote-endpoint = <&etf_out>;
2915 compatible = "arm,coresight-tmc", "arm,primecell";
2919 clock-names = "apb_pclk";
2921 out-ports {
2924 remote-endpoint = <&replicator_in0>;
2929 in-ports {
2932 remote-endpoint = <&merge_funnel_out>;
2939 compatible = "arm,coresight-tmc", "arm,primecell";
2944 clock-names = "apb_pclk";
2945 arm,scatter-gather;
2947 in-ports {
2950 remote-endpoint = <&replicator_out0>;
2957 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2961 clock-names = "apb_pclk";
2963 out-ports {
2964 #address-cells = <1>;
2965 #size-cells = <0>;
2970 remote-endpoint = <&swao_funnel_in>;
2975 in-ports {
2979 remote-endpoint = <&replicator_out1>;
2986 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2990 clock-names = "apb_pclk";
2992 out-ports {
2995 remote-endpoint = <&swao_etf_in>;
3000 in-ports {
3001 #address-cells = <1>;
3002 #size-cells = <0>;
3007 remote-endpoint = <&replicator1_out>;
3014 compatible = "arm,coresight-tmc", "arm,primecell";
3018 clock-names = "apb_pclk";
3020 out-ports {
3023 remote-endpoint = <&swao_replicator_in>;
3028 in-ports {
3031 remote-endpoint = <&swao_funnel_out>;
3038 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3042 clock-names = "apb_pclk";
3043 qcom,replicator-loses-context;
3045 out-ports {
3048 remote-endpoint = <&funnel1_in4>;
3053 in-ports {
3056 remote-endpoint = <&swao_etf_out>;
3063 compatible = "arm,coresight-etm4x", "arm,primecell";
3069 clock-names = "apb_pclk";
3070 arm,coresight-loses-context-with-cpu;
3071 qcom,skip-power-up;
3073 out-ports {
3076 remote-endpoint = <&apss_funnel_in0>;
3083 compatible = "arm,coresight-etm4x", "arm,primecell";
3089 clock-names = "apb_pclk";
3090 arm,coresight-loses-context-with-cpu;
3091 qcom,skip-power-up;
3093 out-ports {
3096 remote-endpoint = <&apss_funnel_in1>;
3103 compatible = "arm,coresight-etm4x", "arm,primecell";
3109 clock-names = "apb_pclk";
3110 arm,coresight-loses-context-with-cpu;
3111 qcom,skip-power-up;
3113 out-ports {
3116 remote-endpoint = <&apss_funnel_in2>;
3123 compatible = "arm,coresight-etm4x", "arm,primecell";
3129 clock-names = "apb_pclk";
3130 arm,coresight-loses-context-with-cpu;
3131 qcom,skip-power-up;
3133 out-ports {
3136 remote-endpoint = <&apss_funnel_in3>;
3143 compatible = "arm,coresight-etm4x", "arm,primecell";
3149 clock-names = "apb_pclk";
3150 arm,coresight-loses-context-with-cpu;
3151 qcom,skip-power-up;
3153 out-ports {
3156 remote-endpoint = <&apss_funnel_in4>;
3163 compatible = "arm,coresight-etm4x", "arm,primecell";
3169 clock-names = "apb_pclk";
3170 arm,coresight-loses-context-with-cpu;
3171 qcom,skip-power-up;
3173 out-ports {
3176 remote-endpoint = <&apss_funnel_in5>;
3183 compatible = "arm,coresight-etm4x", "arm,primecell";
3189 clock-names = "apb_pclk";
3190 arm,coresight-loses-context-with-cpu;
3191 qcom,skip-power-up;
3193 out-ports {
3196 remote-endpoint = <&apss_funnel_in6>;
3203 compatible = "arm,coresight-etm4x", "arm,primecell";
3209 clock-names = "apb_pclk";
3210 arm,coresight-loses-context-with-cpu;
3211 qcom,skip-power-up;
3213 out-ports {
3216 remote-endpoint = <&apss_funnel_in7>;
3223 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3227 clock-names = "apb_pclk";
3229 out-ports {
3232 remote-endpoint = <&apss_merge_funnel_in>;
3237 in-ports {
3238 #address-cells = <1>;
3239 #size-cells = <0>;
3244 remote-endpoint = <&etm0_out>;
3251 remote-endpoint = <&etm1_out>;
3258 remote-endpoint = <&etm2_out>;
3265 remote-endpoint = <&etm3_out>;
3272 remote-endpoint = <&etm4_out>;
3279 remote-endpoint = <&etm5_out>;
3286 remote-endpoint = <&etm6_out>;
3293 remote-endpoint = <&etm7_out>;
3300 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3304 clock-names = "apb_pclk";
3306 out-ports {
3309 remote-endpoint = <&funnel2_in2>;
3314 in-ports {
3317 remote-endpoint = <&apss_funnel_out>;
3324 compatible = "qcom,sm8150-cdsp-pas";
3327 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3332 interrupt-names = "wdog", "fatal", "ready",
3333 "handover", "stop-ack";
3336 clock-names = "xo";
3338 power-domains = <&rpmhpd SM8150_CX>;
3340 memory-region = <&cdsp_mem>;
3344 qcom,smem-states = <&cdsp_smp2p_out 0>;
3345 qcom,smem-state-names = "stop";
3349 glink-edge {
3352 qcom,remote-pid = <5>;
3357 qcom,glink-channels = "fastrpcglink-apps-dsp";
3359 qcom,non-secure-domain;
3360 #address-cells = <1>;
3361 #size-cells = <0>;
3363 compute-cb@1 {
3364 compatible = "qcom,fastrpc-compute-cb";
3369 compute-cb@2 {
3370 compatible = "qcom,fastrpc-compute-cb";
3375 compute-cb@3 {
3376 compatible = "qcom,fastrpc-compute-cb";
3381 compute-cb@4 {
3382 compatible = "qcom,fastrpc-compute-cb";
3387 compute-cb@5 {
3388 compatible = "qcom,fastrpc-compute-cb";
3393 compute-cb@6 {
3394 compatible = "qcom,fastrpc-compute-cb";
3399 compute-cb@7 {
3400 compatible = "qcom,fastrpc-compute-cb";
3405 compute-cb@8 {
3406 compatible = "qcom,fastrpc-compute-cb";
3417 compatible = "qcom,sm8150-usb-hs-phy",
3418 "qcom,usb-snps-hs-7nm-phy";
3421 #phy-cells = <0>;
3424 clock-names = "ref";
3430 compatible = "qcom,sm8150-usb-hs-phy",
3431 "qcom,usb-snps-hs-7nm-phy";
3434 #phy-cells = <0>;
3437 clock-names = "ref";
3443 compatible = "qcom,sm8150-qmp-usb3-phy";
3447 #address-cells = <2>;
3448 #size-cells = <2>;
3455 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3459 reset-names = "phy", "common";
3468 #clock-cells = <0>;
3469 #phy-cells = <0>;
3471 clock-names = "pipe0";
3472 clock-output-names = "usb3_phy_pipe_clk_src";
3477 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3480 #address-cells = <2>;
3481 #size-cells = <2>;
3488 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3492 reset-names = "phy", "common";
3499 #clock-cells = <0>;
3500 #phy-cells = <0>;
3502 clock-names = "pipe0";
3503 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3508 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3513 interrupt-names = "hc_irq", "pwr_irq";
3518 clock-names = "iface", "core", "xo";
3520 qcom,dll-config = <0x0007642c>;
3521 qcom,ddr-config = <0x80040868>;
3522 power-domains = <&rpmhpd 0>;
3523 operating-points-v2 = <&sdhc2_opp_table>;
3527 sdhc2_opp_table: opp-table {
3528 compatible = "operating-points-v2";
3530 opp-19200000 {
3531 opp-hz = /bits/ 64 <19200000>;
3532 required-opps = <&rpmhpd_opp_min_svs>;
3535 opp-50000000 {
3536 opp-hz = /bits/ 64 <50000000>;
3537 required-opps = <&rpmhpd_opp_low_svs>;
3540 opp-100000000 {
3541 opp-hz = /bits/ 64 <100000000>;
3542 required-opps = <&rpmhpd_opp_svs>;
3545 opp-202000000 {
3546 opp-hz = /bits/ 64 <202000000>;
3547 required-opps = <&rpmhpd_opp_svs_l1>;
3553 compatible = "qcom,sm8150-dc-noc";
3555 #interconnect-cells = <2>;
3556 qcom,bcm-voters = <&apps_bcm_voter>;
3560 compatible = "qcom,sm8150-gem-noc";
3562 #interconnect-cells = <2>;
3563 qcom,bcm-voters = <&apps_bcm_voter>;
3567 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3570 #address-cells = <2>;
3571 #size-cells = <2>;
3573 dma-ranges;
3581 clock-names = "cfg_noc",
3588 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3590 assigned-clock-rates = <19200000>, <200000000>;
3592 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3596 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3599 power-domains = <&gcc USB30_PRIM_GDSC>;
3605 interconnect-names = "usb-ddr", "apps-usb";
3615 phy-names = "usb2-phy", "usb3-phy";
3620 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3623 #address-cells = <2>;
3624 #size-cells = <2>;
3626 dma-ranges;
3634 clock-names = "cfg_noc",
3641 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3643 assigned-clock-rates = <19200000>, <200000000>;
3645 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3649 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3652 power-domains = <&gcc USB30_SEC_GDSC>;
3658 interconnect-names = "usb-ddr", "apps-usb";
3668 phy-names = "usb2-phy", "usb3-phy";
3673 compatible = "qcom,sm8150-camnoc-virt";
3675 #interconnect-cells = <2>;
3676 qcom,bcm-voters = <&apps_bcm_voter>;
3679 mdss: display-subsystem@ae00000 {
3680 compatible = "qcom,sm8150-mdss";
3682 reg-names = "mdss";
3686 interconnect-names = "mdp0-mem", "mdp1-mem";
3688 power-domains = <&dispcc MDSS_GDSC>;
3690 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3693 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3694 clock-names = "iface", "bus", "nrt_bus", "core";
3697 interrupt-controller;
3698 #interrupt-cells = <1>;
3704 #address-cells = <2>;
3705 #size-cells = <2>;
3708 mdss_mdp: display-controller@ae01000 {
3709 compatible = "qcom,sm8150-dpu";
3712 reg-names = "mdp", "vbif";
3714 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3716 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3717 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3718 clock-names = "iface", "bus", "core", "vsync";
3720 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3721 assigned-clock-rates = <19200000>;
3723 operating-points-v2 = <&mdp_opp_table>;
3724 power-domains = <&rpmhpd SM8150_MMCX>;
3726 interrupt-parent = <&mdss>;
3730 #address-cells = <1>;
3731 #size-cells = <0>;
3736 remote-endpoint = <&mdss_dsi0_in>;
3743 remote-endpoint = <&mdss_dsi1_in>;
3748 mdp_opp_table: opp-table {
3749 compatible = "operating-points-v2";
3751 opp-171428571 {
3752 opp-hz = /bits/ 64 <171428571>;
3753 required-opps = <&rpmhpd_opp_low_svs>;
3756 opp-300000000 {
3757 opp-hz = /bits/ 64 <300000000>;
3758 required-opps = <&rpmhpd_opp_svs>;
3761 opp-345000000 {
3762 opp-hz = /bits/ 64 <345000000>;
3763 required-opps = <&rpmhpd_opp_svs_l1>;
3766 opp-460000000 {
3767 opp-hz = /bits/ 64 <460000000>;
3768 required-opps = <&rpmhpd_opp_nom>;
3774 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3776 reg-names = "dsi_ctrl";
3778 interrupt-parent = <&mdss>;
3781 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3782 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3783 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3784 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3785 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3787 clock-names = "byte",
3794 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3795 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3796 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3799 operating-points-v2 = <&dsi_opp_table>;
3800 power-domains = <&rpmhpd SM8150_MMCX>;
3806 #address-cells = <1>;
3807 #size-cells = <0>;
3810 #address-cells = <1>;
3811 #size-cells = <0>;
3816 remote-endpoint = <&dpu_intf1_out>;
3827 dsi_opp_table: opp-table {
3828 compatible = "operating-points-v2";
3830 opp-187500000 {
3831 opp-hz = /bits/ 64 <187500000>;
3832 required-opps = <&rpmhpd_opp_low_svs>;
3835 opp-300000000 {
3836 opp-hz = /bits/ 64 <300000000>;
3837 required-opps = <&rpmhpd_opp_svs>;
3840 opp-358000000 {
3841 opp-hz = /bits/ 64 <358000000>;
3842 required-opps = <&rpmhpd_opp_svs_l1>;
3848 compatible = "qcom,dsi-phy-7nm-8150";
3852 reg-names = "dsi_phy",
3856 #clock-cells = <1>;
3857 #phy-cells = <0>;
3859 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3861 clock-names = "iface", "ref";
3867 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3869 reg-names = "dsi_ctrl";
3871 interrupt-parent = <&mdss>;
3874 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3875 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3876 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3877 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3878 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3880 clock-names = "byte",
3887 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3888 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3889 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3892 operating-points-v2 = <&dsi_opp_table>;
3893 power-domains = <&rpmhpd SM8150_MMCX>;
3899 #address-cells = <1>;
3900 #size-cells = <0>;
3903 #address-cells = <1>;
3904 #size-cells = <0>;
3909 remote-endpoint = <&dpu_intf2_out>;
3922 compatible = "qcom,dsi-phy-7nm-8150";
3926 reg-names = "dsi_phy",
3930 #clock-cells = <1>;
3931 #phy-cells = <0>;
3933 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3935 clock-names = "iface", "ref";
3941 dispcc: clock-controller@af00000 { label
3942 compatible = "qcom,sm8150-dispcc";
3951 clock-names = "bi_tcxo",
3958 power-domains = <&rpmhpd SM8150_MMCX>;
3959 required-opps = <&rpmhpd_opp_low_svs>;
3960 #clock-cells = <1>;
3961 #reset-cells = <1>;
3962 #power-domain-cells = <1>;
3965 pdc: interrupt-controller@b220000 {
3966 compatible = "qcom,sm8150-pdc", "qcom,pdc";
3968 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3970 #interrupt-cells = <2>;
3971 interrupt-parent = <&intc>;
3972 interrupt-controller;
3975 aoss_qmp: power-management@c300000 {
3976 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
3981 #clock-cells = <0>;
3985 compatible = "qcom,rpmh-stats";
3989 tsens0: thermal-sensor@c263000 {
3990 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3996 interrupt-names = "uplow", "critical";
3997 #thermal-sensor-cells = <1>;
4000 tsens1: thermal-sensor@c265000 {
4001 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4007 interrupt-names = "uplow", "critical";
4008 #thermal-sensor-cells = <1>;
4012 compatible = "qcom,spmi-pmic-arb";
4018 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4019 interrupt-names = "periph_irq";
4023 #address-cells = <2>;
4024 #size-cells = <0>;
4025 interrupt-controller;
4026 #interrupt-cells = <4>;
4030 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4032 #iommu-cells = <2>;
4033 #global-interrupts = <1>;
4118 compatible = "qcom,sm8150-adsp-pas";
4121 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4126 interrupt-names = "wdog", "fatal", "ready",
4127 "handover", "stop-ack";
4130 clock-names = "xo";
4132 power-domains = <&rpmhpd SM8150_CX>;
4134 memory-region = <&adsp_mem>;
4138 qcom,smem-states = <&adsp_smp2p_out 0>;
4139 qcom,smem-state-names = "stop";
4143 glink-edge {
4146 qcom,remote-pid = <2>;
4151 qcom,glink-channels = "fastrpcglink-apps-dsp";
4153 qcom,non-secure-domain;
4154 #address-cells = <1>;
4155 #size-cells = <0>;
4157 compute-cb@3 {
4158 compatible = "qcom,fastrpc-compute-cb";
4163 compute-cb@4 {
4164 compatible = "qcom,fastrpc-compute-cb";
4169 compute-cb@5 {
4170 compatible = "qcom,fastrpc-compute-cb";
4178 intc: interrupt-controller@17a00000 {
4179 compatible = "arm,gic-v3";
4180 interrupt-controller;
4181 #interrupt-cells = <3>;
4188 compatible = "qcom,sm8150-apss-shared",
4189 "qcom,sdm845-apss-shared";
4191 #mbox-cells = <1>;
4195 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4202 #address-cells = <1>;
4203 #size-cells = <1>;
4205 compatible = "arm,armv7-timer-mem";
4207 clock-frequency = <19200000>;
4210 frame-number = <0>;
4218 frame-number = <1>;
4225 frame-number = <2>;
4232 frame-number = <3>;
4239 frame-number = <4>;
4246 frame-number = <5>;
4253 frame-number = <6>;
4262 compatible = "qcom,rpmh-rsc";
4266 reg-names = "drv-0", "drv-1", "drv-2";
4270 qcom,tcs-offset = <0xd00>;
4271 qcom,drv-id = <2>;
4272 qcom,tcs-config = <ACTIVE_TCS 2>,
4276 power-domains = <&CLUSTER_PD>;
4278 rpmhcc: clock-controller {
4279 compatible = "qcom,sm8150-rpmh-clk";
4280 #clock-cells = <1>;
4281 clock-names = "xo";
4285 rpmhpd: power-controller {
4286 compatible = "qcom,sm8150-rpmhpd";
4287 #power-domain-cells = <1>;
4288 operating-points-v2 = <&rpmhpd_opp_table>;
4290 rpmhpd_opp_table: opp-table {
4291 compatible = "operating-points-v2";
4294 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4298 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4302 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4306 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4310 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4314 opp-level = <224>;
4318 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4322 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4326 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4330 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4334 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4339 apps_bcm_voter: bcm-voter {
4340 compatible = "qcom,bcm-voter";
4345 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4349 clock-names = "xo", "alternate";
4351 #interconnect-cells = <1>;
4355 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4358 reg-names = "freq-domain0", "freq-domain1",
4359 "freq-domain2";
4362 clock-names = "xo", "alternate";
4364 #freq-domain-cells = <1>;
4365 #clock-cells = <1>;
4369 compatible = "qcom,sm8150-lmh";
4373 qcom,lmh-temp-arm-millicelsius = <60000>;
4374 qcom,lmh-temp-low-millicelsius = <84500>;
4375 qcom,lmh-temp-high-millicelsius = <85000>;
4376 interrupt-controller;
4377 #interrupt-cells = <1>;
4381 compatible = "qcom,sm8150-lmh";
4385 qcom,lmh-temp-arm-millicelsius = <60000>;
4386 qcom,lmh-temp-low-millicelsius = <84500>;
4387 qcom,lmh-temp-high-millicelsius = <85000>;
4388 interrupt-controller;
4389 #interrupt-cells = <1>;
4393 compatible = "qcom,wcn3990-wifi";
4395 reg-names = "membase";
4396 memory-region = <&wlan_mem>;
4397 clock-names = "cxo_ref_clk_pin", "qdss";
4417 compatible = "arm,armv8-timer";
4424 thermal-zones {
4425 cpu0-thermal {
4426 polling-delay-passive = <250>;
4427 polling-delay = <1000>;
4429 thermal-sensors = <&tsens0 1>;
4432 cpu0_alert0: trip-point0 {
4438 cpu0_alert1: trip-point1 {
4444 cpu0_crit: cpu-crit {
4451 cooling-maps {
4454 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4461 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4469 cpu1-thermal {
4470 polling-delay-passive = <250>;
4471 polling-delay = <1000>;
4473 thermal-sensors = <&tsens0 2>;
4476 cpu1_alert0: trip-point0 {
4482 cpu1_alert1: trip-point1 {
4488 cpu1_crit: cpu-crit {
4495 cooling-maps {
4498 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4505 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4513 cpu2-thermal {
4514 polling-delay-passive = <250>;
4515 polling-delay = <1000>;
4517 thermal-sensors = <&tsens0 3>;
4520 cpu2_alert0: trip-point0 {
4526 cpu2_alert1: trip-point1 {
4532 cpu2_crit: cpu-crit {
4539 cooling-maps {
4542 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4549 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4557 cpu3-thermal {
4558 polling-delay-passive = <250>;
4559 polling-delay = <1000>;
4561 thermal-sensors = <&tsens0 4>;
4564 cpu3_alert0: trip-point0 {
4570 cpu3_alert1: trip-point1 {
4576 cpu3_crit: cpu-crit {
4583 cooling-maps {
4586 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4593 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4601 cpu4-top-thermal {
4602 polling-delay-passive = <250>;
4603 polling-delay = <1000>;
4605 thermal-sensors = <&tsens0 7>;
4608 cpu4_top_alert0: trip-point0 {
4614 cpu4_top_alert1: trip-point1 {
4620 cpu4_top_crit: cpu-crit {
4627 cooling-maps {
4630 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4637 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 cpu5-top-thermal {
4646 polling-delay-passive = <250>;
4647 polling-delay = <1000>;
4649 thermal-sensors = <&tsens0 8>;
4652 cpu5_top_alert0: trip-point0 {
4658 cpu5_top_alert1: trip-point1 {
4664 cpu5_top_crit: cpu-crit {
4671 cooling-maps {
4674 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 cpu6-top-thermal {
4690 polling-delay-passive = <250>;
4691 polling-delay = <1000>;
4693 thermal-sensors = <&tsens0 9>;
4696 cpu6_top_alert0: trip-point0 {
4702 cpu6_top_alert1: trip-point1 {
4708 cpu6_top_crit: cpu-crit {
4715 cooling-maps {
4718 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 cpu7-top-thermal {
4734 polling-delay-passive = <250>;
4735 polling-delay = <1000>;
4737 thermal-sensors = <&tsens0 10>;
4740 cpu7_top_alert0: trip-point0 {
4746 cpu7_top_alert1: trip-point1 {
4752 cpu7_top_crit: cpu-crit {
4759 cooling-maps {
4762 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4777 cpu4-bottom-thermal {
4778 polling-delay-passive = <250>;
4779 polling-delay = <1000>;
4781 thermal-sensors = <&tsens0 11>;
4784 cpu4_bottom_alert0: trip-point0 {
4790 cpu4_bottom_alert1: trip-point1 {
4796 cpu4_bottom_crit: cpu-crit {
4803 cooling-maps {
4806 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4813 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4821 cpu5-bottom-thermal {
4822 polling-delay-passive = <250>;
4823 polling-delay = <1000>;
4825 thermal-sensors = <&tsens0 12>;
4828 cpu5_bottom_alert0: trip-point0 {
4834 cpu5_bottom_alert1: trip-point1 {
4840 cpu5_bottom_crit: cpu-crit {
4847 cooling-maps {
4850 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4857 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4865 cpu6-bottom-thermal {
4866 polling-delay-passive = <250>;
4867 polling-delay = <1000>;
4869 thermal-sensors = <&tsens0 13>;
4872 cpu6_bottom_alert0: trip-point0 {
4878 cpu6_bottom_alert1: trip-point1 {
4884 cpu6_bottom_crit: cpu-crit {
4891 cooling-maps {
4894 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4901 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4909 cpu7-bottom-thermal {
4910 polling-delay-passive = <250>;
4911 polling-delay = <1000>;
4913 thermal-sensors = <&tsens0 14>;
4916 cpu7_bottom_alert0: trip-point0 {
4922 cpu7_bottom_alert1: trip-point1 {
4928 cpu7_bottom_crit: cpu-crit {
4935 cooling-maps {
4938 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4945 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4953 aoss0-thermal {
4954 polling-delay-passive = <250>;
4955 polling-delay = <1000>;
4957 thermal-sensors = <&tsens0 0>;
4960 aoss0_alert0: trip-point0 {
4968 cluster0-thermal {
4969 polling-delay-passive = <250>;
4970 polling-delay = <1000>;
4972 thermal-sensors = <&tsens0 5>;
4975 cluster0_alert0: trip-point0 {
4988 cluster1-thermal {
4989 polling-delay-passive = <250>;
4990 polling-delay = <1000>;
4992 thermal-sensors = <&tsens0 6>;
4995 cluster1_alert0: trip-point0 {
5008 gpu-top-thermal {
5009 polling-delay-passive = <250>;
5010 polling-delay = <1000>;
5012 thermal-sensors = <&tsens0 15>;
5015 gpu1_alert0: trip-point0 {
5023 aoss1-thermal {
5024 polling-delay-passive = <250>;
5025 polling-delay = <1000>;
5027 thermal-sensors = <&tsens1 0>;
5030 aoss1_alert0: trip-point0 {
5038 wlan-thermal {
5039 polling-delay-passive = <250>;
5040 polling-delay = <1000>;
5042 thermal-sensors = <&tsens1 1>;
5045 wlan_alert0: trip-point0 {
5053 video-thermal {
5054 polling-delay-passive = <250>;
5055 polling-delay = <1000>;
5057 thermal-sensors = <&tsens1 2>;
5060 video_alert0: trip-point0 {
5068 mem-thermal {
5069 polling-delay-passive = <250>;
5070 polling-delay = <1000>;
5072 thermal-sensors = <&tsens1 3>;
5075 mem_alert0: trip-point0 {
5083 q6-hvx-thermal {
5084 polling-delay-passive = <250>;
5085 polling-delay = <1000>;
5087 thermal-sensors = <&tsens1 4>;
5090 q6_hvx_alert0: trip-point0 {
5098 camera-thermal {
5099 polling-delay-passive = <250>;
5100 polling-delay = <1000>;
5102 thermal-sensors = <&tsens1 5>;
5105 camera_alert0: trip-point0 {
5113 compute-thermal {
5114 polling-delay-passive = <250>;
5115 polling-delay = <1000>;
5117 thermal-sensors = <&tsens1 6>;
5120 compute_alert0: trip-point0 {
5128 modem-thermal {
5129 polling-delay-passive = <250>;
5130 polling-delay = <1000>;
5132 thermal-sensors = <&tsens1 7>;
5135 modem_alert0: trip-point0 {
5143 npu-thermal {
5144 polling-delay-passive = <250>;
5145 polling-delay = <1000>;
5147 thermal-sensors = <&tsens1 8>;
5150 npu_alert0: trip-point0 {
5158 modem-vec-thermal {
5159 polling-delay-passive = <250>;
5160 polling-delay = <1000>;
5162 thermal-sensors = <&tsens1 9>;
5165 modem_vec_alert0: trip-point0 {
5173 modem-scl-thermal {
5174 polling-delay-passive = <250>;
5175 polling-delay = <1000>;
5177 thermal-sensors = <&tsens1 10>;
5180 modem_scl_alert0: trip-point0 {
5188 gpu-bottom-thermal {
5189 polling-delay-passive = <250>;
5190 polling-delay = <1000>;
5192 thermal-sensors = <&tsens1 11>;
5195 gpu2_alert0: trip-point0 {