Lines Matching +full:1 +full:c25000
152 clocks = <&cpufreq_hw 1>;
157 qcom,freq-domain = <&cpufreq_hw 1>;
176 clocks = <&cpufreq_hw 1>;
181 qcom,freq-domain = <&cpufreq_hw 1>;
200 clocks = <&cpufreq_hw 1>;
205 qcom,freq-domain = <&cpufreq_hw 1>;
293 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
608 #reset-cells = <1>;
722 qcom,client-id = <1>;
811 #qcom,smem-state-cells = <1>;
835 #qcom,smem-state-cells = <1>;
855 qcom,remote-pid = <1>;
859 #qcom,smem-state-cells = <1>;
883 #qcom,smem-state-cells = <1>;
904 #clock-cells = <1>;
905 #reset-cells = <1>;
906 #power-domain-cells = <1>;
965 #address-cells = <1>;
966 #size-cells = <1>;
992 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
997 #address-cells = <1>;
1009 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1015 #address-cells = <1>;
1025 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1026 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1031 #address-cells = <1>;
1042 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1043 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1049 #address-cells = <1>;
1060 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1065 #address-cells = <1>;
1077 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1083 #address-cells = <1>;
1094 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1099 #address-cells = <1>;
1111 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1117 #address-cells = <1>;
1128 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1133 #address-cells = <1>;
1145 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1151 #address-cells = <1>;
1162 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1167 #address-cells = <1>;
1179 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1185 #address-cells = <1>;
1196 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1201 #address-cells = <1>;
1213 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1219 #address-cells = <1>;
1230 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1235 #address-cells = <1>;
1247 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1253 #address-cells = <1>;
1300 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1305 #address-cells = <1>;
1317 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1323 #address-cells = <1>;
1333 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1334 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1339 #address-cells = <1>;
1350 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1351 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1357 #address-cells = <1>;
1379 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1384 #address-cells = <1>;
1396 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1402 #address-cells = <1>;
1413 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1418 #address-cells = <1>;
1430 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1436 #address-cells = <1>;
1456 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1461 #address-cells = <1>;
1473 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1479 #address-cells = <1>;
1490 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1495 #address-cells = <1>;
1507 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1513 #address-cells = <1>;
1561 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1566 #address-cells = <1>;
1578 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1584 #address-cells = <1>;
1594 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1595 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1600 #address-cells = <1>;
1611 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1612 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1618 #address-cells = <1>;
1629 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1634 #address-cells = <1>;
1646 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1652 #address-cells = <1>;
1663 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1668 #address-cells = <1>;
1680 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1686 #address-cells = <1>;
1697 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1702 #address-cells = <1>;
1714 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1720 #address-cells = <1>;
1731 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1736 #address-cells = <1>;
1748 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1754 #address-cells = <1>;
1825 pcie0: pci@1c00000 {
1836 num-lanes = <1>;
1846 #interrupt-cells = <1>;
1848 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1888 pcie0_phy: phy@1c06000 {
1911 pcie0_lane: phy@1c06200 {
1924 pcie1: pci@1c08000 {
1933 linux,pci-domain = <1>;
1945 #interrupt-cells = <1>;
1947 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1990 pcie1_phy: phy@1c0e000 {
2013 pcie1_lane: phy@1c0e200 {
2028 ufs_mem_hc: ufshc@1d84000 {
2038 #reset-cells = <1>;
2078 ufs_mem_phy: phy@1d87000 {
2095 ufs_mem_phy_lanes: phy@1d87400 {
2105 cryptobam: dma-controller@1dc4000 {
2109 #dma-cells = <1>;
2121 crypto: crypto@1dfa000 {
2135 tcsr_mutex: hwlock@1f40000 {
2138 #hwlock-cells = <1>;
2141 tcsr_regs_1: syscon@1f60000 {
2152 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 #address-cells = <1>;
2188 compute-cb@1 {
2190 reg = <1>;
2321 #clock-cells = <1>;
2322 #reset-cells = <1>;
2323 #power-domain-cells = <1>;
2331 #global-interrupts = <1>;
2704 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2730 qcom,remote-pid = <1>;
2769 #address-cells = <1>;
2797 #address-cells = <1>;
2825 #address-cells = <1>;
2853 #address-cells = <1>;
2863 port@1 {
2864 reg = <1>;
2887 #address-cells = <1>;
2897 port@1 {
2898 reg = <1>;
2964 #address-cells = <1>;
2967 port@1 {
2968 reg = <1>;
3001 #address-cells = <1>;
3238 #address-cells = <1>;
3248 port@1 {
3249 reg = <1>;
3329 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3360 #address-cells = <1>;
3363 compute-cb@1 {
3365 reg = <1>;
3698 #interrupt-cells = <1>;
3730 #address-cells = <1>;
3740 port@1 {
3741 reg = <1>;
3797 <&mdss_dsi0_phy 1>;
3806 #address-cells = <1>;
3810 #address-cells = <1>;
3820 port@1 {
3821 reg = <1>;
3856 #clock-cells = <1>;
3890 <&mdss_dsi1_phy 1>;
3899 #address-cells = <1>;
3903 #address-cells = <1>;
3913 port@1 {
3914 reg = <1>;
3930 #clock-cells = <1>;
3946 <&mdss_dsi0_phy 1>,
3948 <&mdss_dsi1_phy 1>,
3960 #clock-cells = <1>;
3961 #reset-cells = <1>;
3962 #power-domain-cells = <1>;
3969 <125 63 1>;
3997 #thermal-sensor-cells = <1>;
4008 #thermal-sensor-cells = <1>;
4033 #global-interrupts = <1>;
4123 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4154 #address-cells = <1>;
4191 #mbox-cells = <1>;
4202 #address-cells = <1>;
4203 #size-cells = <1>;
4218 frame-number = <1>;
4224 frame@17c25000 {
4266 reg-names = "drv-0", "drv-1", "drv-2";
4275 <CONTROL_TCS 1>;
4280 #clock-cells = <1>;
4287 #power-domain-cells = <1>;
4351 #interconnect-cells = <1>;
4364 #freq-domain-cells = <1>;
4365 #clock-cells = <1>;
4377 #interrupt-cells = <1>;
4389 #interrupt-cells = <1>;
4418 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4429 thermal-sensors = <&tsens0 1>;
5042 thermal-sensors = <&tsens1 1>;