Lines Matching +full:0 +full:x0c222000
30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
58 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
87 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
103 reg = <0x0 0x200>;
104 clocks = <&cpufreq_hw 0>;
109 qcom,freq-domain = <&cpufreq_hw 0>;
111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
127 reg = <0x0 0x300>;
128 clocks = <&cpufreq_hw 0>;
133 qcom,freq-domain = <&cpufreq_hw 0>;
135 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
151 reg = <0x0 0x400>;
159 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
175 reg = <0x0 0x500>;
183 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
199 reg = <0x0 0x600>;
207 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
223 reg = <0x0 0x700>;
231 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
283 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
286 arm,psci-suspend-param = <0x40000004>;
293 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
296 arm,psci-suspend-param = <0x40000004>;
305 CLUSTER_SLEEP_0: cluster-sleep-0 {
307 arm,psci-suspend-param = <0x4100c244>;
615 reg = <0x0 0x80000000 0x0 0x0>;
628 #power-domain-cells = <0>;
634 #power-domain-cells = <0>;
640 #power-domain-cells = <0>;
646 #power-domain-cells = <0>;
652 #power-domain-cells = <0>;
658 #power-domain-cells = <0>;
664 #power-domain-cells = <0>;
670 #power-domain-cells = <0>;
676 #power-domain-cells = <0>;
687 reg = <0x0 0x85700000 0x0 0x600000>;
692 reg = <0x0 0x85d00000 0x0 0x140000>;
697 reg = <0x0 0x85f00000 0x0 0x20000>;
703 reg = <0x0 0x85f20000 0x0 0x20000>;
708 reg = <0x0 0x86000000 0x0 0x200000>;
713 reg = <0x0 0x86200000 0x0 0x3900000>;
719 reg = <0x0 0x89b00000 0x0 0x200000>;
727 reg = <0x0 0x8b700000 0x0 0x500000>;
732 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 reg = <0x0 0x96e00000 0x0 0x500000>;
757 reg = <0x0 0x97300000 0x0 0x1400000>;
762 reg = <0x0 0x98700000 0x0 0x10000>;
767 reg = <0x0 0x98710000 0x0 0x5000>;
772 reg = <0x0 0x98715000 0x0 0x2000>;
777 reg = <0x0 0x98800000 0x0 0x100000>;
782 reg = <0x0 0x98900000 0x0 0x1400000>;
787 reg = <0x0 0x9e400000 0x0 0x1400000>;
806 qcom,local-pid = <0>;
830 qcom,local-pid = <0>;
854 qcom,local-pid = <0>;
878 qcom,local-pid = <0>;
894 soc: soc@0 {
897 ranges = <0 0 0 0 0x10 0>;
898 dma-ranges = <0 0 0 0 0x10 0>;
903 reg = <0x0 0x00100000 0x0 0x1f0000>;
915 reg = <0 0x00800000 0 0x60000>;
930 dma-channel-mask = <0xfa>;
931 iommus = <&apps_smmu 0x00d6 0x0>;
938 reg = <0x0 0x00020000 0x0 0x10000>,
939 <0x0 0x00036000 0x0 0x100>;
953 iommus = <&apps_smmu 0x3c0 0x0>;
964 reg = <0 0x00784000 0 0x8ff>;
969 reg = <0x133 0x1>;
976 reg = <0x0 0x008c0000 0x0 0x6000>;
980 iommus = <&apps_smmu 0xc3 0x0>;
988 reg = <0 0x00880000 0 0x4000>;
991 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
992 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
995 pinctrl-0 = <&qup_i2c0_default>;
998 #size-cells = <0>;
1004 reg = <0 0x00880000 0 0x4000>;
1008 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1009 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1012 pinctrl-0 = <&qup_spi0_default>;
1016 #size-cells = <0>;
1022 reg = <0 0x00884000 0 0x4000>;
1025 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1029 pinctrl-0 = <&qup_i2c1_default>;
1032 #size-cells = <0>;
1038 reg = <0 0x00884000 0 0x4000>;
1042 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1046 pinctrl-0 = <&qup_spi1_default>;
1050 #size-cells = <0>;
1056 reg = <0 0x00888000 0 0x4000>;
1059 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1063 pinctrl-0 = <&qup_i2c2_default>;
1066 #size-cells = <0>;
1072 reg = <0 0x00888000 0 0x4000>;
1076 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1080 pinctrl-0 = <&qup_spi2_default>;
1084 #size-cells = <0>;
1090 reg = <0 0x0088c000 0 0x4000>;
1093 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1097 pinctrl-0 = <&qup_i2c3_default>;
1100 #size-cells = <0>;
1106 reg = <0 0x0088c000 0 0x4000>;
1110 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1114 pinctrl-0 = <&qup_spi3_default>;
1118 #size-cells = <0>;
1124 reg = <0 0x00890000 0 0x4000>;
1127 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1131 pinctrl-0 = <&qup_i2c4_default>;
1134 #size-cells = <0>;
1140 reg = <0 0x00890000 0 0x4000>;
1144 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1148 pinctrl-0 = <&qup_spi4_default>;
1152 #size-cells = <0>;
1158 reg = <0 0x00894000 0 0x4000>;
1161 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1165 pinctrl-0 = <&qup_i2c5_default>;
1168 #size-cells = <0>;
1174 reg = <0 0x00894000 0 0x4000>;
1178 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1182 pinctrl-0 = <&qup_spi5_default>;
1186 #size-cells = <0>;
1192 reg = <0 0x00898000 0 0x4000>;
1195 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1199 pinctrl-0 = <&qup_i2c6_default>;
1202 #size-cells = <0>;
1208 reg = <0 0x00898000 0 0x4000>;
1212 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1216 pinctrl-0 = <&qup_spi6_default>;
1220 #size-cells = <0>;
1226 reg = <0 0x0089c000 0 0x4000>;
1229 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1233 pinctrl-0 = <&qup_i2c7_default>;
1236 #size-cells = <0>;
1242 reg = <0 0x0089c000 0 0x4000>;
1246 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1250 pinctrl-0 = <&qup_spi7_default>;
1254 #size-cells = <0>;
1261 reg = <0 0x00a00000 0 0x60000>;
1276 dma-channel-mask = <0xfa>;
1277 iommus = <&apps_smmu 0x0616 0x0>;
1284 reg = <0x0 0x00ac0000 0x0 0x6000>;
1288 iommus = <&apps_smmu 0x603 0x0>;
1296 reg = <0 0x00a80000 0 0x4000>;
1299 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1300 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1303 pinctrl-0 = <&qup_i2c8_default>;
1306 #size-cells = <0>;
1312 reg = <0 0x00a80000 0 0x4000>;
1316 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1317 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1320 pinctrl-0 = <&qup_spi8_default>;
1324 #size-cells = <0>;
1330 reg = <0 0x00a84000 0 0x4000>;
1333 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1337 pinctrl-0 = <&qup_i2c9_default>;
1340 #size-cells = <0>;
1346 reg = <0 0x00a84000 0 0x4000>;
1350 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1354 pinctrl-0 = <&qup_spi9_default>;
1358 #size-cells = <0>;
1364 reg = <0x0 0x00a84000 0x0 0x4000>;
1367 pinctrl-0 = <&qup_uart9_default>;
1375 reg = <0 0x00a88000 0 0x4000>;
1378 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1382 pinctrl-0 = <&qup_i2c10_default>;
1385 #size-cells = <0>;
1391 reg = <0 0x00a88000 0 0x4000>;
1395 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1399 pinctrl-0 = <&qup_spi10_default>;
1403 #size-cells = <0>;
1409 reg = <0 0x00a8c000 0 0x4000>;
1412 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1416 pinctrl-0 = <&qup_i2c11_default>;
1419 #size-cells = <0>;
1425 reg = <0 0x00a8c000 0 0x4000>;
1429 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1433 pinctrl-0 = <&qup_spi11_default>;
1437 #size-cells = <0>;
1443 reg = <0x0 0x00a90000 0x0 0x4000>;
1452 reg = <0 0x00a90000 0 0x4000>;
1455 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1459 pinctrl-0 = <&qup_i2c12_default>;
1462 #size-cells = <0>;
1468 reg = <0 0x00a90000 0 0x4000>;
1472 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1476 pinctrl-0 = <&qup_spi12_default>;
1480 #size-cells = <0>;
1486 reg = <0 0x00094000 0 0x4000>;
1489 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1493 pinctrl-0 = <&qup_i2c16_default>;
1496 #size-cells = <0>;
1502 reg = <0 0x00a94000 0 0x4000>;
1506 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1510 pinctrl-0 = <&qup_spi16_default>;
1514 #size-cells = <0>;
1521 reg = <0 0x00c00000 0 0x60000>;
1536 dma-channel-mask = <0xfa>;
1537 iommus = <&apps_smmu 0x07b6 0x0>;
1544 reg = <0x0 0x00cc0000 0x0 0x6000>;
1549 iommus = <&apps_smmu 0x7a3 0x0>;
1557 reg = <0 0x00c80000 0 0x4000>;
1560 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1561 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1564 pinctrl-0 = <&qup_i2c17_default>;
1567 #size-cells = <0>;
1573 reg = <0 0x00c80000 0 0x4000>;
1577 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1578 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1581 pinctrl-0 = <&qup_spi17_default>;
1585 #size-cells = <0>;
1591 reg = <0 0x00c84000 0 0x4000>;
1594 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1598 pinctrl-0 = <&qup_i2c18_default>;
1601 #size-cells = <0>;
1607 reg = <0 0x00c84000 0 0x4000>;
1611 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1615 pinctrl-0 = <&qup_spi18_default>;
1619 #size-cells = <0>;
1625 reg = <0 0x00c88000 0 0x4000>;
1628 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1632 pinctrl-0 = <&qup_i2c19_default>;
1635 #size-cells = <0>;
1641 reg = <0 0x00c88000 0 0x4000>;
1645 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1649 pinctrl-0 = <&qup_spi19_default>;
1653 #size-cells = <0>;
1659 reg = <0 0x00c8c000 0 0x4000>;
1662 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1666 pinctrl-0 = <&qup_i2c13_default>;
1669 #size-cells = <0>;
1675 reg = <0 0x00c8c000 0 0x4000>;
1679 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1683 pinctrl-0 = <&qup_spi13_default>;
1687 #size-cells = <0>;
1693 reg = <0 0x00c90000 0 0x4000>;
1696 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1700 pinctrl-0 = <&qup_i2c14_default>;
1703 #size-cells = <0>;
1709 reg = <0 0x00c90000 0 0x4000>;
1713 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1717 pinctrl-0 = <&qup_spi14_default>;
1721 #size-cells = <0>;
1727 reg = <0 0x00c94000 0 0x4000>;
1730 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1734 pinctrl-0 = <&qup_i2c15_default>;
1737 #size-cells = <0>;
1743 reg = <0 0x00c94000 0 0x4000>;
1747 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1751 pinctrl-0 = <&qup_spi15_default>;
1755 #size-cells = <0>;
1762 reg = <0 0x01500000 0 0x7400>;
1769 reg = <0 0x01620000 0 0x19400>;
1776 reg = <0 0x0163a000 0 0x1000>;
1783 reg = <0 0x016e0000 0 0xd080>;
1790 reg = <0 0x01700000 0 0x20000>;
1797 reg = <0 0x01720000 0 0x7000>;
1804 reg = <0 0x01740000 0 0x1c100>;
1811 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
1812 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
1813 <0 0x09600000 0 0x50000>;
1821 reg = <0x0 0x010a2000 0x0 0x1000>,
1822 <0x0 0x010ad000 0x0 0x3000>;
1827 reg = <0 0x01c00000 0 0x3000>,
1828 <0 0x60000000 0 0xf1d>,
1829 <0 0x60000f20 0 0xa8>,
1830 <0 0x60001000 0 0x1000>,
1831 <0 0x60100000 0 0x100000>;
1834 linux,pci-domain = <0>;
1835 bus-range = <0x00 0xff>;
1841 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1842 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1847 interrupt-map-mask = <0 0 0 0x7>;
1848 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1849 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1850 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1851 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1868 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1869 <0x100 &apps_smmu 0x1d81 0x1>;
1883 pinctrl-0 = <&pcie0_default_state>;
1890 reg = <0 0x01c06000 0 0x1c0>;
1912 reg = <0 0x01c06200 0 0x170>, /* tx */
1913 <0 0x01c06400 0 0x200>, /* rx */
1914 <0 0x01c06800 0 0x1f0>, /* pcs */
1915 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1919 #phy-cells = <0>;
1926 reg = <0 0x01c08000 0 0x3000>,
1927 <0 0x40000000 0 0xf1d>,
1928 <0 0x40000f20 0 0xa8>,
1929 <0 0x40001000 0 0x1000>,
1930 <0 0x40100000 0 0x100000>;
1934 bus-range = <0x00 0xff>;
1940 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1941 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1946 interrupt-map-mask = <0 0 0 0x7>;
1947 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1948 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1949 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1950 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1970 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1971 <0x100 &apps_smmu 0x1e01 0x1>;
1985 pinctrl-0 = <&pcie1_default_state>;
1992 reg = <0 0x01c0e000 0 0x1c0>;
2014 reg = <0 0x01c0e200 0 0x170>, /* tx0 */
2015 <0 0x01c0e400 0 0x200>, /* rx0 */
2016 <0 0x01c0ea00 0 0x1f0>, /* pcs */
2017 <0 0x01c0e600 0 0x170>, /* tx1 */
2018 <0 0x01c0e800 0 0x200>, /* rx1 */
2019 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2023 #phy-cells = <0>;
2031 reg = <0 0x01d84000 0 0x2500>,
2032 <0 0x01d90000 0 0x8000>;
2042 iommus = <&apps_smmu 0x300 0>;
2066 <0 0>,
2067 <0 0>,
2069 <0 0>,
2070 <0 0>,
2071 <0 0>,
2072 <0 0>,
2073 <0 300000000>;
2080 reg = <0 0x01d87000 0 0x1c0>;
2091 resets = <&ufs_mem_hc 0>;
2096 reg = <0 0x01d87400 0 0x16c>,
2097 <0 0x01d87600 0 0x200>,
2098 <0 0x01d87c00 0 0x200>,
2099 <0 0x01d87800 0 0x16c>,
2100 <0 0x01d87a00 0 0x200>;
2101 #phy-cells = <0>;
2107 reg = <0 0x01dc4000 0 0x24000>;
2110 qcom,ee = <0>;
2114 iommus = <&apps_smmu 0x502 0x0641>,
2115 <&apps_smmu 0x504 0x0011>,
2116 <&apps_smmu 0x506 0x0011>,
2117 <&apps_smmu 0x508 0x0011>,
2118 <&apps_smmu 0x512 0x0000>;
2123 reg = <0 0x01dfa000 0 0x6000>;
2126 iommus = <&apps_smmu 0x502 0x0641>,
2127 <&apps_smmu 0x504 0x0011>,
2128 <&apps_smmu 0x506 0x0011>,
2129 <&apps_smmu 0x508 0x0011>,
2130 <&apps_smmu 0x512 0x0000>;
2131 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2137 reg = <0x0 0x01f40000 0x0 0x20000>;
2143 reg = <0x0 0x01f60000 0x0 0x20000>;
2148 reg = <0x0 0x02400000 0x0 0x4040>;
2151 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2169 qcom,smem-states = <&slpi_smp2p_out 0>;
2186 #size-cells = <0>;
2191 iommus = <&apps_smmu 0x05a1 0x0>;
2197 iommus = <&apps_smmu 0x05a2 0x0>;
2203 iommus = <&apps_smmu 0x05a3 0x0>;
2212 reg = <0 0x02c00000 0 0x40000>;
2217 iommus = <&adreno_smmu 0 0x401>;
2238 opp-supported-hw = <0x2>;
2244 opp-supported-hw = <0x3>;
2250 opp-supported-hw = <0x3>;
2256 opp-supported-hw = <0x3>;
2262 opp-supported-hw = <0x3>;
2268 opp-supported-hw = <0x3>;
2276 reg = <0 0x02c6a000 0 0x30000>,
2277 <0 0x0b290000 0 0x10000>,
2278 <0 0x0b490000 0 0x10000>;
2296 iommus = <&adreno_smmu 5 0x400>;
2314 reg = <0 0x02c90000 0 0x9000>;
2329 reg = <0 0x02ca0000 0 0x10000>;
2351 reg = <0x0 0x03100000 0x0 0x300000>,
2352 <0x0 0x03500000 0x0 0x300000>,
2353 <0x0 0x03900000 0x0 0x300000>,
2354 <0x0 0x03D00000 0x0 0x300000>;
2357 gpio-ranges = <&tlmm 0 0 176>;
2367 drive-strength = <0x02>;
2700 reg = <0x0 0x04080000 0x0 0x4040>;
2703 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2722 qcom,smem-states = <&modem_smp2p_out 0>;
2737 reg = <0 0x06002000 0 0x1000>,
2738 <0 0x16280000 0 0x180000>;
2755 reg = <0 0x06041000 0 0x1000>;
2770 #size-cells = <0>;
2783 reg = <0 0x06042000 0 0x1000>;
2798 #size-cells = <0>;
2811 reg = <0 0x06043000 0 0x1000>;
2826 #size-cells = <0>;
2839 reg = <0 0x06045000 0 0x1000>;
2854 #size-cells = <0>;
2856 port@0 {
2857 reg = <0>;
2881 reg = <0 0x06046000 0 0x1000>;
2888 #size-cells = <0>;
2890 port@0 {
2891 reg = <0>;
2916 reg = <0 0x06047000 0 0x1000>;
2940 reg = <0 0x06048000 0 0x1000>;
2941 iommus = <&apps_smmu 0x05e0 0x0>;
2958 reg = <0 0x0604a000 0 0x1000>;
2965 #size-cells = <0>;
2987 reg = <0 0x06b08000 0 0x1000>;
3002 #size-cells = <0>;
3015 reg = <0 0x06b09000 0 0x1000>;
3039 reg = <0 0x06b0a000 0 0x1000>;
3064 reg = <0 0x07040000 0 0x1000>;
3084 reg = <0 0x07140000 0 0x1000>;
3104 reg = <0 0x07240000 0 0x1000>;
3124 reg = <0 0x07340000 0 0x1000>;
3144 reg = <0 0x07440000 0 0x1000>;
3164 reg = <0 0x07540000 0 0x1000>;
3184 reg = <0 0x07640000 0 0x1000>;
3204 reg = <0 0x07740000 0 0x1000>;
3224 reg = <0 0x07800000 0 0x1000>;
3239 #size-cells = <0>;
3241 port@0 {
3242 reg = <0>;
3301 reg = <0 0x07810000 0 0x1000>;
3325 reg = <0x0 0x08300000 0x0 0x4040>;
3328 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3344 qcom,smem-states = <&cdsp_smp2p_out 0>;
3361 #size-cells = <0>;
3366 iommus = <&apps_smmu 0x1001 0x0460>;
3372 iommus = <&apps_smmu 0x1002 0x0460>;
3378 iommus = <&apps_smmu 0x1003 0x0460>;
3384 iommus = <&apps_smmu 0x1004 0x0460>;
3390 iommus = <&apps_smmu 0x1005 0x0460>;
3396 iommus = <&apps_smmu 0x1006 0x0460>;
3402 iommus = <&apps_smmu 0x1007 0x0460>;
3408 iommus = <&apps_smmu 0x1008 0x0460>;
3419 reg = <0 0x088e2000 0 0x400>;
3421 #phy-cells = <0>;
3432 reg = <0 0x088e3000 0 0x400>;
3434 #phy-cells = <0>;
3444 reg = <0 0x088e9000 0 0x18c>,
3445 <0 0x088e8000 0 0x10>;
3462 reg = <0 0x088e9200 0 0x200>,
3463 <0 0x088e9400 0 0x200>,
3464 <0 0x088e9c00 0 0x218>,
3465 <0 0x088e9600 0 0x200>,
3466 <0 0x088e9800 0 0x200>,
3467 <0 0x088e9a00 0 0x100>;
3468 #clock-cells = <0>;
3469 #phy-cells = <0>;
3478 reg = <0 0x088eb000 0 0x200>;
3495 reg = <0 0x088eb200 0 0x200>,
3496 <0 0x088eb400 0 0x200>,
3497 <0 0x088eb800 0 0x800>,
3498 <0 0x088eb600 0 0x200>;
3499 #clock-cells = <0>;
3500 #phy-cells = <0>;
3509 reg = <0 0x08804000 0 0x1000>;
3519 iommus = <&apps_smmu 0x6a0 0x0>;
3520 qcom,dll-config = <0x0007642c>;
3521 qcom,ddr-config = <0x80040868>;
3522 power-domains = <&rpmhpd 0>;
3554 reg = <0 0x09160000 0 0x3200>;
3561 reg = <0 0x09680000 0 0x3e200>;
3568 reg = <0 0x0a6f8800 0 0x400>;
3603 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
3604 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
3609 reg = <0 0x0a600000 0 0xcd00>;
3611 iommus = <&apps_smmu 0x140 0>;
3621 reg = <0 0x0a8f8800 0 0x400>;
3656 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
3657 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
3662 reg = <0 0x0a800000 0 0xcd00>;
3664 iommus = <&apps_smmu 0x160 0>;
3674 reg = <0 0x0ac00000 0 0x1000>;
3681 reg = <0 0x0ae00000 0 0x1000>;
3684 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
3685 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
3700 iommus = <&apps_smmu 0x800 0x420>;
3710 reg = <0 0x0ae01000 0 0x8f000>,
3711 <0 0x0aeb0000 0 0x2008>;
3727 interrupts = <0>;
3731 #size-cells = <0>;
3733 port@0 {
3734 reg = <0>;
3775 reg = <0 0x0ae94000 0 0x400>;
3796 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3807 #size-cells = <0>;
3811 #size-cells = <0>;
3813 port@0 {
3814 reg = <0>;
3849 reg = <0 0x0ae94400 0 0x200>,
3850 <0 0x0ae94600 0 0x280>,
3851 <0 0x0ae94900 0 0x260>;
3857 #phy-cells = <0>;
3868 reg = <0 0x0ae96000 0 0x400>;
3889 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3900 #size-cells = <0>;
3904 #size-cells = <0>;
3906 port@0 {
3907 reg = <0>;
3923 reg = <0 0x0ae96400 0 0x200>,
3924 <0 0x0ae96600 0 0x280>,
3925 <0 0x0ae96900 0 0x260>;
3931 #phy-cells = <0>;
3943 reg = <0 0x0af00000 0 0x10000>;
3945 <&mdss_dsi0_phy 0>,
3947 <&mdss_dsi1_phy 0>,
3949 <0>,
3950 <0>;
3967 reg = <0 0x0b220000 0 0x30000>;
3968 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3977 reg = <0x0 0x0c300000 0x0 0x400>;
3979 mboxes = <&apss_shared 0>;
3981 #clock-cells = <0>;
3986 reg = <0 0x0c3f0000 0 0x400>;
3991 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3992 <0 0x0c222000 0 0x1ff>; /* SROT */
4002 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4003 <0 0x0c223000 0 0x1ff>; /* SROT */
4013 reg = <0x0 0x0c440000 0x0 0x0001100>,
4014 <0x0 0x0c600000 0x0 0x2000000>,
4015 <0x0 0x0e600000 0x0 0x0100000>,
4016 <0x0 0x0e700000 0x0 0x00a0000>,
4017 <0x0 0x0c40a000 0x0 0x0026000>;
4021 qcom,ee = <0>;
4022 qcom,channel = <0>;
4024 #size-cells = <0>;
4031 reg = <0 0x15000000 0 0x100000>;
4119 reg = <0x0 0x17300000 0x0 0x4040>;
4122 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4138 qcom,smem-states = <&adsp_smp2p_out 0>;
4155 #size-cells = <0>;
4160 iommus = <&apps_smmu 0x1b23 0x0>;
4166 iommus = <&apps_smmu 0x1b24 0x0>;
4172 iommus = <&apps_smmu 0x1b25 0x0>;
4182 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4183 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4190 reg = <0x0 0x17c00000 0x0 0x1000>;
4196 reg = <0 0x17c10000 0 0x1000>;
4198 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4204 ranges = <0 0 0 0x20000000>;
4206 reg = <0x0 0x17c20000 0x0 0x1000>;
4210 frame-number = <0>;
4213 reg = <0x17c21000 0x1000>,
4214 <0x17c22000 0x1000>;
4220 reg = <0x17c23000 0x1000>;
4227 reg = <0x17c25000 0x1000>;
4234 reg = <0x17c26000 0x1000>;
4241 reg = <0x17c29000 0x1000>;
4248 reg = <0x17c2b000 0x1000>;
4255 reg = <0x17c2d000 0x1000>;
4263 reg = <0x0 0x18200000 0x0 0x10000>,
4264 <0x0 0x18210000 0x0 0x10000>,
4265 <0x0 0x18220000 0x0 0x10000>;
4266 reg-names = "drv-0", "drv-1", "drv-2";
4270 qcom,tcs-offset = <0xd00>;
4346 reg = <0 0x18321000 0 0x1400>;
4356 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4357 <0 0x18327800 0 0x1400>;
4370 reg = <0 0x18350800 0 0x400>;
4382 reg = <0 0x18358800 0 0x400>;
4394 reg = <0 0x18800000 0 0x800000>;
4411 iommus = <&apps_smmu 0x0640 0x1>;
4421 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4957 thermal-sensors = <&tsens0 0>;
5027 thermal-sensors = <&tsens1 0>;