Lines Matching +full:0 +full:x04a80000
27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
45 clocks = <&cpufreq_hw 0>;
48 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x100>;
71 clocks = <&cpufreq_hw 0>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
91 reg = <0x0 0x200>;
92 clocks = <&cpufreq_hw 0>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
112 reg = <0x0 0x300>;
113 clocks = <&cpufreq_hw 0>;
116 qcom,freq-domain = <&cpufreq_hw 0>;
133 reg = <0x0 0x400>;
134 clocks = <&cpufreq_hw 0>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
154 reg = <0x0 0x500>;
155 clocks = <&cpufreq_hw 0>;
158 qcom,freq-domain = <&cpufreq_hw 0>;
175 reg = <0x0 0x600>;
196 reg = <0x0 0x700>;
253 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
256 arm,psci-suspend-param = <0x40000003>;
263 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
266 arm,psci-suspend-param = <0x40000004>;
273 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
276 arm,psci-suspend-param = <0x40000003>;
286 arm,psci-suspend-param = <0x40000004>;
295 CLUSTER_SLEEP_0: cluster-sleep-0 {
297 arm,psci-suspend-param = <0x41000044>;
321 #power-domain-cells = <0>;
327 <89 314>, /* TSENS0 0C */
328 <90 315>, /* TSENS1 0C */
336 reg = <0x0 0x80000000 0x0 0x0>;
459 #power-domain-cells = <0>;
465 #power-domain-cells = <0>;
471 #power-domain-cells = <0>;
477 #power-domain-cells = <0>;
483 #power-domain-cells = <0>;
489 #power-domain-cells = <0>;
495 #power-domain-cells = <0>;
501 #power-domain-cells = <0>;
507 #power-domain-cells = <0>;
538 reg = <0 0x80000000 0 0x600000>;
543 reg = <0 0x80700000 0 0x100000>;
548 reg = <0 0x80880000 0 0x14000>;
554 reg = <0 0x80900000 0 0x200000>;
560 reg = <0 0x80b00000 0 0x100000>;
565 reg = <0 0x80c00000 0 0x1e00000>;
570 reg = <0 0x85e00000 0 0x100000>;
575 reg = <0 0x86500000 0 0x200000>;
580 reg = <0 0x86700000 0 0x2000000>;
585 reg = <0 0x88700000 0 0x1e00000>;
590 reg = <0 0x8a500000 0 0x500000>;
595 reg = <0 0x8aa00000 0 0x10000>;
600 reg = <0 0x8aa10000 0 0xa000>;
605 reg = <0 0x8aa1a000 0 0x2000>;
610 reg = <0 0x8b800000 0 0x10000000>;
615 reg = <0 0xc0000000 0 0x5100000>;
621 reg = <0 0xf3900000 0 0x280000>;
629 reg = <0 0xffb00000 0 0xc0000>;
634 reg = <0 0xffbc0000 0 0x80000>;
639 reg = <0 0xffd00000 0 0x1000>;
724 qcom,local-pid = <0>;
748 qcom,local-pid = <0>;
772 qcom,local-pid = <0>;
804 soc: soc@0 {
807 ranges = <0 0 0 0 0x10 0>;
808 dma-ranges = <0 0 0 0 0x10 0>;
813 reg = <0 0x00208000 0 0x1000>;
822 reg = <0x0 0x00340000 0x0 0x40000>;
828 reg = <0 0x00500000 0 0x800000>;
830 gpio-ranges = <&tlmm 0 0 157>;
923 reg = <0 0x01400000 0 0x1f0000>;
934 reg = <0 0x0162b000 0 0x400>;
939 #phy-cells = <0>;
946 reg = <0 0x01c40000 0 0x1100>,
947 <0 0x01e00000 0 0x2000000>,
948 <0 0x03e00000 0 0x100000>,
949 <0 0x03f00000 0 0xa0000>,
950 <0 0x01c0a000 0 0x26000>;
954 qcom,ee = <0>;
955 qcom,channel = <0>;
957 #size-cells = <0>;
964 reg = <0 0x04411000 0 0x140>, /* TM */
965 <0 0x04410000 0 0x20>; /* SROT */
975 reg = <0 0x04413000 0 0x140>, /* TM */
976 <0 0x04412000 0 0x20>; /* SROT */
986 reg = <0 0x045f0000 0 0x7000>;
989 ranges = <0 0x0 0x045f0000 0x7000>;
992 reg = <0x1b8 0x48>;
998 reg = <0 0x04690000 0 0x400>;
1003 reg = <0 0x04784000 0 0x1000>;
1014 iommus = <&apps_smmu 0x40 0x0>;
1016 pinctrl-0 = <&sdc2_on_state>;
1020 qcom,dll-config = <0x0007642c>;
1021 qcom,ddr-config = <0x80040868>;
1045 reg = <0 0x04a00000 0 0x60000>;
1057 dma-channel-mask = <0x1f>;
1058 iommus = <&apps_smmu 0x16 0x0>;
1065 reg = <0x0 0x04ac0000 0x0 0x2000>;
1069 iommus = <&apps_smmu 0x3 0x0>;
1077 reg = <0x0 0x04a80000 0x0 0x4000>;
1082 pinctrl-0 = <&qup_i2c0_default>;
1083 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1084 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1087 #size-cells = <0>;
1093 reg = <0x0 0x04a80000 0x0 0x4000>;
1098 pinctrl-0 = <&qup_spi0_default>;
1101 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1102 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1105 #size-cells = <0>;
1111 reg = <0x0 0x04a84000 0x0 0x4000>;
1116 pinctrl-0 = <&qup_i2c1_default>;
1117 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1121 #size-cells = <0>;
1127 reg = <0x0 0x04a84000 0x0 0x4000>;
1133 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1137 #size-cells = <0>;
1143 reg = <0x0 0x04a88000 0x0 0x4000>;
1148 pinctrl-0 = <&qup_i2c2_default>;
1149 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1153 #size-cells = <0>;
1159 reg = <0x0 0x04a88000 0x0 0x4000>;
1165 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1169 #size-cells = <0>;
1184 reg = <0 0x04c00000 0 0x60000>;
1196 dma-channel-mask = <0x1f>;
1197 iommus = <&apps_smmu 0xd6 0x0>;
1204 reg = <0x0 0x04cc0000 0x0 0x2000>;
1208 iommus = <&apps_smmu 0xc3 0x0>;
1216 reg = <0x0 0x04c80000 0x0 0x4000>;
1220 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1221 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1224 #size-cells = <0>;
1230 reg = <0x0 0x04c80000 0x0 0x4000>;
1236 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1237 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1240 #size-cells = <0>;
1246 reg = <0x0 0x04c84000 0x0 0x4000>;
1250 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1254 #size-cells = <0>;
1260 reg = <0x0 0x04c84000 0x0 0x4000>;
1266 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1270 #size-cells = <0>;
1276 reg = <0x0 0x04c88000 0x0 0x4000>;
1281 pinctrl-0 = <&qup_i2c8_default>;
1282 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1286 #size-cells = <0>;
1292 reg = <0x0 0x04c88000 0x0 0x4000>;
1298 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1302 #size-cells = <0>;
1308 reg = <0x0 0x04c8c000 0x0 0x4000>;
1312 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1316 #size-cells = <0>;
1322 reg = <0x0 0x04c8c000 0x0 0x4000>;
1328 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1332 #size-cells = <0>;
1338 reg = <0x0 0x04c90000 0x0 0x4000>;
1343 pinctrl-0 = <&qup_i2c10_default>;
1344 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1348 #size-cells = <0>;
1354 reg = <0x0 0x04c90000 0x0 0x4000>;
1360 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1364 #size-cells = <0>;
1371 reg = <0 0x04ef8800 0 0x400>;
1418 reg = <0 0x04e00000 0 0xcd00>;
1423 iommus = <&apps_smmu 0xe0 0x0>;
1426 snps,hird-threshold = /bits/ 8 <0x10>;
1440 reg = <0 0x05940000 0 0x10000>;
1462 reg = <0 0x05990000 0 0x9000>;
1476 reg = <0 0x06000000 0 0x4040>;
1479 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1499 qcom,smem-states = <&smp2p_modem_out 0>;
1517 reg = <0 0x0a400000 0 0x100>;
1520 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1536 qcom,smem-states = <&smp2p_adsp_out 0>;
1555 reg = <0x0 0x0b000000 0x0 0x100000>;
1558 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1573 qcom,smem-states = <&smp2p_cdsp_out 0>;
1591 reg = <0 0x0c125000 0 0x1000>;
1592 ranges = <0 0 0x0c125000 0x1000>;
1599 reg = <0x94c 0xc8>;
1605 reg = <0 0x0c600000 0 0x100000>;
1681 reg = <0 0x0c800000 0 0x800000>;
1696 iommus = <&apps_smmu 0x80 0x1>;
1703 reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */
1704 <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */
1708 redistributor-stride = <0 0x20000>;
1714 reg = <0 0x0f420000 0 0x1000>;
1715 ranges = <0 0 0 0x20000000>;
1720 reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>;
1723 frame-number = <0>;
1727 reg = <0x0f243000 0x1000>;
1734 reg = <0x0f425000 0x1000>;
1741 reg = <0x0f427000 0x1000>;
1748 reg = <0x0f429000 0x1000>;
1755 reg = <0x0f42b000 0x1000>;
1762 reg = <0x0f42d000 0x1000>;
1771 reg = <0 0x0fd90000 0 0x1000>;
1780 reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>;
1787 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
1795 polling-delay-passive = <0>;
1796 polling-delay = <0>;
1798 thermal-sensors = <&tsens0 0>;
1822 polling-delay-passive = <0>;
1823 polling-delay = <0>;
1849 polling-delay-passive = <0>;
1850 polling-delay = <0>;
1876 polling-delay-passive = <0>;
1877 polling-delay = <0>;
1903 polling-delay-passive = <0>;
1904 polling-delay = <0>;
1930 polling-delay-passive = <0>;
1931 polling-delay = <0>;
1957 polling-delay-passive = <0>;
1958 polling-delay = <0>;
1984 polling-delay-passive = <0>;
1985 polling-delay = <0>;
2011 polling-delay-passive = <0>;
2012 polling-delay = <0>;
2038 polling-delay-passive = <0>;
2039 polling-delay = <0>;
2065 polling-delay-passive = <0>;
2066 polling-delay = <0>;
2092 polling-delay-passive = <0>;
2093 polling-delay = <0>;
2119 polling-delay-passive = <0>;
2120 polling-delay = <0>;
2146 polling-delay-passive = <0>;
2147 polling-delay = <0>;
2173 polling-delay-passive = <0>;
2174 polling-delay = <0>;
2200 polling-delay-passive = <0>;
2201 polling-delay = <0>;
2203 thermal-sensors = <&tsens1 0>;
2227 polling-delay-passive = <0>;
2228 polling-delay = <0>;
2254 polling-delay-passive = <0>;
2255 polling-delay = <0>;
2281 polling-delay-passive = <0>;
2282 polling-delay = <0>;
2308 polling-delay-passive = <0>;
2309 polling-delay = <0>;
2335 polling-delay-passive = <0>;
2336 polling-delay = <0>;
2362 polling-delay-passive = <0>;
2363 polling-delay = <0>;
2389 polling-delay-passive = <0>;
2390 polling-delay = <0>;
2416 polling-delay-passive = <0>;
2417 polling-delay = <0>;
2443 polling-delay-passive = <0>;
2444 polling-delay = <0>;
2470 polling-delay-passive = <0>;
2471 polling-delay = <0>;
2502 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;