Lines Matching +full:0 +full:x0ae01000
31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
105 reg = <0x0 0x200>;
106 clocks = <&cpufreq_hw 0>;
111 qcom,freq-domain = <&cpufreq_hw 0>;
130 reg = <0x0 0x300>;
131 clocks = <&cpufreq_hw 0>;
136 qcom,freq-domain = <&cpufreq_hw 0>;
155 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw 0>;
161 qcom,freq-domain = <&cpufreq_hw 0>;
180 reg = <0x0 0x500>;
181 clocks = <&cpufreq_hw 0>;
186 qcom,freq-domain = <&cpufreq_hw 0>;
205 reg = <0x0 0x600>;
230 reg = <0x0 0x700>;
289 CLUSTER_SLEEP_PC: cluster-sleep-0 {
291 arm,psci-suspend-param = <0x41000044>;
299 arm,psci-suspend-param = <0x41001244>;
307 arm,psci-suspend-param = <0x4100b244>;
317 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
320 arm,psci-suspend-param = <0x40000003>;
327 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
330 arm,psci-suspend-param = <0x40000004>;
337 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
340 arm,psci-suspend-param = <0x40000003>;
350 arm,psci-suspend-param = <0x40000004>;
369 reg = <0x0 0x80000000 0x0 0x0>;
507 #power-domain-cells = <0>;
513 #power-domain-cells = <0>;
519 #power-domain-cells = <0>;
525 #power-domain-cells = <0>;
531 #power-domain-cells = <0>;
537 #power-domain-cells = <0>;
543 #power-domain-cells = <0>;
549 #power-domain-cells = <0>;
555 #power-domain-cells = <0>;
568 reg = <0 0x80000000 0 0x600000>;
573 reg = <0 0x80700000 0 0x160000>;
579 reg = <0 0x80860000 0 0x20000>;
584 reg = <0 0x808ff000 0 0x1000>;
589 reg = <0 0x80900000 0 0x200000>;
594 reg = <0 0x80b00000 0 0x1e00000>;
599 reg = <0 0x86000000 0 0x500000>;
604 reg = <0 0x86500000 0 0x500000>;
609 reg = <0 0x86a00000 0 0x500000>;
614 reg = <0 0x86f00000 0 0x1e00000>;
619 reg = <0 0x88d00000 0 0x2800000>;
624 reg = <0 0x8b500000 0 0x200000>;
629 reg = <0 0x8b700000 0 0x10000>;
634 reg = <0 0x8b710000 0 0x5400>;
639 reg = <0 0x8b800000 0 0xf800000>;
644 reg = <0 0xa0000000 0 0x2300000>;
649 reg = <0 0xa2300000 0 0x100000>;
654 reg = <0 0xc0000000 0 0x3900000>;
659 reg = <0 0xf0d00000 0 0x1000>;
664 reg = <0 0xffb00000 0 0xc0000>;
669 reg = <0 0xffbc0000 0 0x40000>;
675 reg = <0 0xffc00000 0 0x100000>;
676 record-size = <0x1000>;
677 console-size = <0x40000>;
678 pmsg-size = <0x20000>;
684 reg = <0 0xffd00000 0 0x1000>;
704 qcom,local-pid = <0>;
728 qcom,local-pid = <0>;
753 qcom,local-pid = <0>;
779 soc: soc@0 {
782 ranges = <0 0 0 0 0x10 0>;
783 dma-ranges = <0 0 0 0 0x10 0>;
788 reg = <0 0x00100000 0 0x1f0000>;
802 reg = <0 0x00408000 0 0x1000>;
811 reg = <0 0x00784000 0 0x3000>;
816 reg = <0x2015 0x1>;
817 bits = <0 8>;
823 reg = <0 0x00793000 0 0x1000>;
830 reg = <0 0x007c4000 0 0x1000>,
831 <0 0x007c5000 0 0x1000>,
832 <0 0x007c8000 0 0x8000>;
838 iommus = <&apps_smmu 0x60 0x0>;
845 qcom,dll-config = <0x000f642c>;
846 qcom,ddr-config = <0x80040868>;
877 reg = <0 0x00800000 0 0x60000>;
889 dma-channel-mask = <0x1f>;
890 iommus = <&apps_smmu 0x56 0x0>;
897 reg = <0x0 0x008c0000 0x0 0x2000>;
903 iommus = <&apps_smmu 0x43 0x0>;
909 reg = <0 0x00880000 0 0x4000>;
913 pinctrl-0 = <&qup_i2c0_default>;
915 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
916 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
919 #size-cells = <0>;
920 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
921 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
922 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
929 reg = <0 0x00884000 0 0x4000>;
933 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
937 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
938 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
945 reg = <0 0x00888000 0 0x4000>;
949 pinctrl-0 = <&qup_i2c2_default>;
951 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
955 #size-cells = <0>;
956 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
957 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
958 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
966 reg = <0 0x00900000 0 0x60000>;
978 dma-channel-mask = <0x3f>;
979 iommus = <&apps_smmu 0x4d6 0x0>;
986 reg = <0x0 0x009c0000 0x0 0x2000>;
992 iommus = <&apps_smmu 0x4c3 0x0>;
998 reg = <0 0x00980000 0 0x4000>;
1002 pinctrl-0 = <&qup_i2c6_default>;
1004 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1005 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1008 #size-cells = <0>;
1009 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1010 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1011 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1018 reg = <0 0x00984000 0 0x4000>;
1022 pinctrl-0 = <&qup_i2c7_default>;
1024 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1028 #size-cells = <0>;
1029 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1030 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1031 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1038 reg = <0 0x00988000 0 0x4000>;
1042 pinctrl-0 = <&qup_i2c8_default>;
1044 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1048 #size-cells = <0>;
1049 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1050 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1051 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1058 reg = <0 0x0098c000 0 0x4000>;
1062 pinctrl-0 = <&qup_uart9_default>;
1064 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1065 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1072 reg = <0 0x00990000 0 0x4000>;
1076 pinctrl-0 = <&qup_i2c10_default>;
1078 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1082 #size-cells = <0>;
1083 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1084 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1085 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1093 reg = <0 0x01500000 0 0x28000>;
1100 reg = <0 0x01620000 0 0x17080>;
1113 reg = <0 0x016e0000 0 0x15080>;
1120 reg = <0 0x01700000 0 0x1f880>;
1133 reg = <0 0x01740000 0 0x1c100>;
1141 reg = <0 0x01d84000 0 0x3000>,
1142 <0 0x01d90000 0 0x8000>;
1154 iommus = <&apps_smmu 0x80 0x0>;
1176 <0 0>,
1177 <0 0>,
1180 <0 0>,
1181 <0 0>,
1182 <0 0>,
1183 <0 0>;
1190 reg = <0 0x01d87000 0 0x18c>;
1202 resets = <&ufs_mem_hc 0>;
1208 reg = <0 0x01d87400 0 0x128>,
1209 <0 0x01d87600 0 0x1fc>,
1210 <0 0x01d87c00 0 0x1dc>,
1211 <0 0x01d87800 0 0x128>,
1212 <0 0x01d87a00 0 0x1fc>;
1213 #phy-cells = <0>;
1220 iommus = <&apps_smmu 0x440 0x0>,
1221 <&apps_smmu 0x442 0x0>;
1222 reg = <0 0x01e40000 0 0x8000>,
1223 <0 0x01e50000 0 0x3000>,
1224 <0 0x01e04000 0 0x23000>;
1231 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1241 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>,
1242 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>,
1243 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>;
1246 qcom,smem-states = <&ipa_smp2p_out 0>,
1256 reg = <0x0 0x01f40000 0x0 0x40000>;
1262 reg = <0 0x03000000 0 0x100>;
1265 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1283 qcom,smem-states = <&smp2p_adsp_out 0>;
1304 #size-cells = <0>;
1309 iommus = <&apps_smmu 0x1003 0x0>;
1315 iommus = <&apps_smmu 0x1004 0x0>;
1321 iommus = <&apps_smmu 0x1005 0x0>;
1330 reg = <0 0x03d00000 0 0x40000>,
1331 <0 0x03d9e000 0 0x1000>;
1336 iommus = <&adreno_smmu 0>;
1354 opp-supported-hw = <0x03>;
1360 opp-supported-hw = <0x07>;
1366 opp-supported-hw = <0x0f>;
1372 opp-supported-hw = <0x1f>;
1378 opp-supported-hw = <0x1f>;
1384 opp-supported-hw = <0x1f>;
1390 opp-supported-hw = <0x1f>;
1397 reg = <0 0x03d40000 0 0x10000>;
1423 reg = <0 0x03d6a000 0 0x31000>,
1424 <0 0x0b290000 0 0x10000>,
1425 <0 0x0b490000 0 0x10000>;
1469 reg = <0 0x03d90000 0 0x9000>;
1483 reg = <0x0 0x04080000 0x0 0x4040>;
1486 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1505 qcom,smem-states = <&modem_smp2p_out 0>;
1523 reg = <0 0x08300000 0 0x10000>;
1526 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1544 qcom,smem-states = <&smp2p_cdsp_out 0>;
1565 #size-cells = <0>;
1570 iommus = <&apps_smmu 0x1401 0x20>;
1576 iommus = <&apps_smmu 0x1402 0x20>;
1582 iommus = <&apps_smmu 0x1403 0x20>;
1588 iommus = <&apps_smmu 0x1404 0x20>;
1594 iommus = <&apps_smmu 0x1405 0x20>;
1600 iommus = <&apps_smmu 0x1406 0x20>;
1606 iommus = <&apps_smmu 0x1407 0x20>;
1612 iommus = <&apps_smmu 0x1408 0x20>;
1622 reg = <0 0x08804000 0 0x1000>;
1627 iommus = <&apps_smmu 0x560 0x0>;
1634 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
1635 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
1638 pinctrl-0 = <&sdc2_on_state>;
1642 qcom,dll-config = <0x0007642c>;
1643 qcom,ddr-config = <0x80040868>;
1671 reg = <0 0x088e3000 0 0x400>;
1673 #phy-cells = <0>;
1683 reg = <0 0x088e8000 0 0x3000>;
1705 reg = <0 0x09160000 0 0x3200>;
1712 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
1718 reg = <0 0x09680000 0 0x3e200>;
1725 reg = <0 0x09990000 0 0x1600>;
1732 reg = <0x0 0x090b6300 0x0 0x600>;
1742 opp-0 {
1771 reg = <0x0 0x090cd000 0x0 0x1000>;
1781 opp-0 {
1829 reg = <0 0x0a6f8800 0 0x400>;
1858 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>,
1859 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1864 reg = <0 0x0a600000 0 0xcd00>;
1866 iommus = <&apps_smmu 0x540 0x0>;
1870 snps,hird-threshold = /bits/ 8 <0x10>;
1879 reg = <0 0x0ac4a000 0 0x1000>;
1900 pinctrl-0 = <&cci0_default &cci1_default>;
1905 #size-cells = <0>;
1909 cci0_i2c0: i2c-bus@0 {
1910 reg = <0>;
1913 #size-cells = <0>;
1920 #size-cells = <0>;
1926 reg = <0 0x0ac4b000 0 0x1000>;
1947 pinctrl-0 = <&cci2_default>;
1952 #size-cells = <0>;
1956 cci1_i2c0: i2c-bus@0 {
1957 reg = <0>;
1960 #size-cells = <0>;
1968 reg = <0 0x0ad00000 0 0x16000>;
1977 reg = <0 0x0ae00000 0 0x1000>;
1992 iommus = <&apps_smmu 0x800 0x2>;
2002 reg = <0 0x0ae01000 0 0x8f000>,
2003 <0 0x0aeb0000 0 0x2008>;
2007 interrupts = <0>;
2030 #size-cells = <0>;
2032 port@0 {
2033 reg = <0>;
2078 reg = <0 0x0ae94000 0 0x400>;
2099 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2108 #size-cells = <0>;
2114 #size-cells = <0>;
2116 port@0 {
2117 reg = <0>;
2154 reg = <0 0x0ae94400 0 0x200>,
2155 <0 0x0ae94600 0 0x280>,
2156 <0 0x0ae94a00 0 0x1e0>;
2162 #phy-cells = <0>;
2174 reg = <0 0x0af00000 0 0x20000>;
2177 <&mdss_dsi0_phy 0>,
2194 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
2195 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2204 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2205 <0 0x0c222000 0 0x8>; /* SROT */
2215 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2216 <0 0x0c223000 0 0x8>; /* SROT */
2226 reg = <0 0x0c300000 0 0x1000>;
2231 #clock-cells = <0>;
2236 reg = <0 0x0c440000 0 0x1100>,
2237 <0 0x0c600000 0 0x2000000>,
2238 <0 0x0e600000 0 0x100000>,
2239 <0 0x0e700000 0 0xa0000>,
2240 <0 0x0c40a000 0 0x26000>;
2244 qcom,ee = <0>;
2245 qcom,channel = <0>;
2247 #size-cells = <0>;
2254 reg = <0 0x0f100000 0 0x300000>;
2268 gpio-ranges = <&tlmm 0 0 157>;
2433 reg = <0 0x15000000 0 0x100000>;
2523 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
2524 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
2530 reg = <0 0x17c10000 0 0x1000>;
2532 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
2537 reg = <0x0 0x17c20000 0x0 0x1000>;
2541 ranges = <0 0 0 0x20000000>;
2544 frame-number = <0>;
2547 reg = <0x17c21000 0x1000>,
2548 <0x17c22000 0x1000>;
2554 reg = <0x17c23000 0x1000>;
2561 reg = <0x17c25000 0x1000>;
2568 reg = <0x17c27000 0x1000>;
2575 reg = <0x17c29000 0x1000>;
2582 reg = <0x17c2b000 0x1000>;
2589 reg = <0x17c2d000 0x1000>;
2597 reg = <0x0 0x18200000 0x0 0x10000>,
2598 <0x0 0x18210000 0x0 0x10000>,
2599 <0x0 0x18220000 0x0 0x10000>;
2600 reg-names = "drv-0", "drv-1", "drv-2";
2604 qcom,tcs-offset = <0xd00>;
2674 reg = <0x0 0x18321000 0x0 0x1000>;
2684 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
2695 reg = <0 0x18800000 0 0x800000>;
2710 iommus = <&apps_smmu 0x20 0x1>;
2722 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;