Lines Matching +full:0 +full:x04ac0000
23 #clock-cells = <0>;
30 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
66 reg = <0x0 0x2>;
75 reg = <0x0 0x3>;
84 reg = <0x0 0x100>;
98 reg = <0x0 0x101>;
107 reg = <0x0 0x102>;
116 reg = <0x0 0x103>;
170 reg = <0x0 0x40000000 0x0 0x0>;
192 mboxes = <&apcs_glb 0>;
262 reg = <0x0 0x45700000 0x0 0x600000>;
267 reg = <0x0 0x45e00000 0x0 0x140000>;
272 reg = <0x0 0x45fff000 0x0 0x1000>;
277 reg = <0x0 0x46000000 0x0 0x200000>;
282 reg = <0x0 0x46200000 0x0 0x2d00000>;
287 reg = <0x0 0x4ab00000 0x0 0x500000>;
292 reg = <0x0 0x4b000000 0x0 0x7e00000>;
297 reg = <0x0 0x52e00000 0x0 0x500000>;
302 reg = <0x0 0x53300000 0x0 0x200000>;
307 reg = <0x0 0x53500000 0x0 0x1e00000>;
312 reg = <0x0 0x55300000 0x0 0x1e00000>;
317 reg = <0x0 0x57100000 0x0 0x10000>;
322 reg = <0x0 0x57110000 0x0 0x5000>;
327 reg = <0x0 0x57115000 0x0 0x2000>;
332 reg = <0x0 0x5c000000 0x0 0x00f00000>;
337 reg = <0x0 0x5cf00000 0x0 0x0100000>;
342 reg = <0x0 0x5f800000 0x0 0x1e00000>;
347 reg = <0x0 0x5e400000 0x0 0x1400000>;
352 reg = <0x0 0xf3000000 0x0 0x400000>;
357 reg = <0x0 0xf3400000 0x0 0x800000>;
362 reg = <0x1 0x3fc00000 0x0 0x400000>;
373 soc@0 {
376 ranges = <0x00 0x00 0x00 0xffffffff>;
381 reg = <0x00340000 0x20000>;
387 reg = <0x00500000 0x400000>,
388 <0x00900000 0x400000>,
389 <0x00d00000 0x400000>;
393 gpio-ranges = <&tlmm 0 0 134>;
665 reg = <0x01400000 0x1f0000>;
675 reg = <0x01613000 0x180>;
676 #phy-cells = <0>;
688 reg = <0x045f0000 0x7000>;
693 reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
704 iommus = <&apps_smmu 0x160 0x0>;
708 qcom,dll-config = <0x000f642c>;
709 qcom,ddr-config = <0x80040873>;
720 reg = <0x04784000 0x1000>;
731 iommus = <&apps_smmu 0x180 0x0>;
733 pinctrl-0 = <&sdc2_on_state>;
739 qcom,dll-config = <0x0007642c>;
740 qcom,ddr-config = <0x80040873>;
748 reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
769 <0 0>,
770 <0 0>,
772 <0 0>,
773 <0 0>,
774 <0 0>,
786 iommus = <&apps_smmu 0x200 0x0>;
793 reg = <0x04807000 0xdb8>;
800 resets = <&ufs_mem_hc 0>;
805 #phy-cells = <0>;
812 reg = <0x04a00000 0x60000>;
822 dma-channel-mask = <0x1f>;
823 iommus = <&apps_smmu 0x136 0x0>;
830 reg = <0x04ac0000 0x2000>;
834 iommus = <&apps_smmu 0x123 0x0>;
842 reg = <0x04a80000 0x4000>;
846 pinctrl-0 = <&qup_i2c0_default>;
849 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
850 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
853 #size-cells = <0>;
859 reg = <0x04a80000 0x4000>;
863 pinctrl-0 = <&qup_spi0_default>;
866 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
867 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
870 #size-cells = <0>;
876 reg = <0x04a84000 0x4000>;
880 pinctrl-0 = <&qup_i2c1_default>;
883 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
887 #size-cells = <0>;
893 reg = <0x04a88000 0x4000>;
897 pinctrl-0 = <&qup_i2c2_default>;
900 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
904 #size-cells = <0>;
910 reg = <0x04a88000 0x4000>;
914 pinctrl-0 = <&qup_spi2_default>;
917 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
921 #size-cells = <0>;
927 reg = <0x04a8c000 0x4000>;
931 pinctrl-0 = <&qup_i2c3_default>;
934 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
938 #size-cells = <0>;
944 reg = <0x04a90000 0x4000>;
948 pinctrl-0 = <&qup_i2c4_default>;
951 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
955 #size-cells = <0>;
962 reg = <0x04c00000 0x60000>;
972 dma-channel-mask = <0x0f>;
973 iommus = <&apps_smmu 0x156 0x0>;
980 reg = <0x04cc0000 0x2000>;
984 iommus = <&apps_smmu 0x143 0x0>;
992 reg = <0x04c80000 0x4000>;
996 pinctrl-0 = <&qup_i2c5_default>;
999 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1000 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1003 #size-cells = <0>;
1009 reg = <0x04c80000 0x4000>;
1013 pinctrl-0 = <&qup_spi5_default>;
1016 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1017 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1020 #size-cells = <0>;
1026 reg = <0x04c84000 0x4000>;
1030 pinctrl-0 = <&qup_i2c6_default>;
1033 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1037 #size-cells = <0>;
1043 reg = <0x04c84000 0x4000>;
1047 pinctrl-0 = <&qup_spi6_default>;
1050 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1054 #size-cells = <0>;
1060 reg = <0x04c88000 0x4000>;
1064 pinctrl-0 = <&qup_i2c7_default>;
1067 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1071 #size-cells = <0>;
1077 reg = <0x04c8c000 0x4000>;
1081 pinctrl-0 = <&qup_i2c8_default>;
1084 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1088 #size-cells = <0>;
1094 reg = <0x04c8c000 0x4000>;
1098 pinctrl-0 = <&qup_spi8_default>;
1101 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1105 #size-cells = <0>;
1111 reg = <0x04c90000 0x4000>;
1115 pinctrl-0 = <&qup_i2c9_default>;
1118 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1122 #size-cells = <0>;
1128 reg = <0x04c90000 0x4000>;
1132 pinctrl-0 = <&qup_spi9_default>;
1135 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1139 #size-cells = <0>;
1146 reg = <0x04ef8800 0x400>;
1178 reg = <0x04e00000 0xcd00>;
1180 iommus = <&apps_smmu 0x100 0x0>;
1192 reg = <0x04690000 0x10000>;
1197 reg = <0x01c40000 0x1100>,
1198 <0x01e00000 0x2000000>,
1199 <0x03e00000 0x100000>,
1200 <0x03f00000 0xa0000>,
1201 <0x01c0a000 0x26000>;
1205 qcom,ee = <0>;
1206 qcom,channel = <0>;
1208 #size-cells = <0>;
1215 reg = <0x0c600000 0x80000>;
1289 reg = <0x0f111000 0x1000>;
1299 reg = <0x0f120000 0x1000>;
1303 frame-number = <0>;
1306 reg = <0x0f121000 0x1000>,
1307 <0x0f122000 0x1000>;
1313 reg = <0x0f123000 0x1000>;
1320 reg = <0x0f124000 0x1000>;
1327 reg = <0x0f125000 0x1000>;
1334 reg = <0x0f126000 0x1000>;
1341 reg = <0x0f127000 0x1000>;
1348 reg = <0x0f128000 0x1000>;
1355 reg = <0x0f200000 0x20000>,
1356 <0x0f300000 0x100000>;
1365 interrupts = <GIC_PPI 1 0xf08
1366 GIC_PPI 2 0xf08
1367 GIC_PPI 3 0xf08
1368 GIC_PPI 0 0xf08>;