Lines Matching +full:has +full:- +full:lpm +full:- +full:erratum
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
25 xo_board: xo-board {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
37 #address-cells = <2>;
38 #size-cells = <0>;
45 capacity-dmips-mhz = <1024>;
46 dynamic-power-coefficient = <100>;
47 enable-method = "psci";
48 next-level-cache = <&L2_0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
50 power-domains = <&CPU_PD0>;
51 power-domain-names = "psci";
52 L2_0: l2-cache {
54 cache-level = <2>;
55 cache-unified;
64 capacity-dmips-mhz = <1024>;
65 dynamic-power-coefficient = <100>;
66 enable-method = "psci";
67 next-level-cache = <&L2_0>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
69 power-domains = <&CPU_PD1>;
70 power-domain-names = "psci";
78 capacity-dmips-mhz = <1024>;
79 dynamic-power-coefficient = <100>;
80 enable-method = "psci";
81 next-level-cache = <&L2_0>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
83 power-domains = <&CPU_PD2>;
84 power-domain-names = "psci";
92 capacity-dmips-mhz = <1024>;
93 dynamic-power-coefficient = <100>;
94 enable-method = "psci";
95 next-level-cache = <&L2_0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
97 power-domains = <&CPU_PD3>;
98 power-domain-names = "psci";
106 enable-method = "psci";
107 capacity-dmips-mhz = <1638>;
108 dynamic-power-coefficient = <282>;
109 next-level-cache = <&L2_1>;
110 qcom,freq-domain = <&cpufreq_hw 1>;
111 power-domains = <&CPU_PD4>;
112 power-domain-names = "psci";
113 L2_1: l2-cache {
115 cache-level = <2>;
116 cache-unified;
125 capacity-dmips-mhz = <1638>;
126 dynamic-power-coefficient = <282>;
127 enable-method = "psci";
128 next-level-cache = <&L2_1>;
129 qcom,freq-domain = <&cpufreq_hw 1>;
130 power-domains = <&CPU_PD5>;
131 power-domain-names = "psci";
139 capacity-dmips-mhz = <1638>;
140 dynamic-power-coefficient = <282>;
141 enable-method = "psci";
142 next-level-cache = <&L2_1>;
143 qcom,freq-domain = <&cpufreq_hw 1>;
144 power-domains = <&CPU_PD6>;
145 power-domain-names = "psci";
153 capacity-dmips-mhz = <1638>;
154 dynamic-power-coefficient = <282>;
155 enable-method = "psci";
156 next-level-cache = <&L2_1>;
157 qcom,freq-domain = <&cpufreq_hw 1>;
158 power-domains = <&CPU_PD7>;
159 power-domain-names = "psci";
162 cpu-map {
200 idle-states {
201 entry-method = "psci";
203 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
204 compatible = "arm,idle-state";
205 idle-state-name = "silver-rail-power-collapse";
206 arm,psci-suspend-param = <0x40000003>;
207 entry-latency-us = <290>;
208 exit-latency-us = <376>;
209 min-residency-us = <1182>;
210 local-timer-stop;
213 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
214 compatible = "arm,idle-state";
215 idle-state-name = "gold-rail-power-collapse";
216 arm,psci-suspend-param = <0x40000003>;
217 entry-latency-us = <297>;
218 exit-latency-us = <324>;
219 min-residency-us = <1110>;
220 local-timer-stop;
224 domain-idle-states {
225 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 {
227 compatible = "domain-idle-state";
228 arm,psci-suspend-param = <0x40000022>;
229 entry-latency-us = <360>;
230 exit-latency-us = <421>;
231 min-residency-us = <782>;
234 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 {
236 compatible = "domain-idle-state";
237 arm,psci-suspend-param = <0x41000044>;
238 entry-latency-us = <800>;
239 exit-latency-us = <2118>;
240 min-residency-us = <7376>;
243 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 {
245 compatible = "domain-idle-state";
246 arm,psci-suspend-param = <0x40000042>;
247 entry-latency-us = <314>;
248 exit-latency-us = <345>;
249 min-residency-us = <660>;
252 CLUSTER_1_SLEEP_1: cluster-sleep-1-1 {
254 compatible = "domain-idle-state";
255 arm,psci-suspend-param = <0x41000044>;
256 entry-latency-us = <640>;
257 exit-latency-us = <1654>;
258 min-residency-us = <8094>;
265 compatible = "qcom,scm-sm6115", "qcom,scm";
266 #reset-cells = <1>;
277 compatible = "arm,armv8-pmuv3";
282 compatible = "arm,psci-1.0";
285 CPU_PD0: power-domain-cpu0 {
286 #power-domain-cells = <0>;
287 power-domains = <&CLUSTER_0_PD>;
288 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
291 CPU_PD1: power-domain-cpu1 {
292 #power-domain-cells = <0>;
293 power-domains = <&CLUSTER_0_PD>;
294 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
297 CPU_PD2: power-domain-cpu2 {
298 #power-domain-cells = <0>;
299 power-domains = <&CLUSTER_0_PD>;
300 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
303 CPU_PD3: power-domain-cpu3 {
304 #power-domain-cells = <0>;
305 power-domains = <&CLUSTER_0_PD>;
306 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
309 CPU_PD4: power-domain-cpu4 {
310 #power-domain-cells = <0>;
311 power-domains = <&CLUSTER_1_PD>;
312 domain-idle-states = <&BIG_CPU_SLEEP_0>;
315 CPU_PD5: power-domain-cpu5 {
316 #power-domain-cells = <0>;
317 power-domains = <&CLUSTER_1_PD>;
318 domain-idle-states = <&BIG_CPU_SLEEP_0>;
321 CPU_PD6: power-domain-cpu6 {
322 #power-domain-cells = <0>;
323 power-domains = <&CLUSTER_1_PD>;
324 domain-idle-states = <&BIG_CPU_SLEEP_0>;
327 CPU_PD7: power-domain-cpu7 {
328 #power-domain-cells = <0>;
329 power-domains = <&CLUSTER_1_PD>;
330 domain-idle-states = <&BIG_CPU_SLEEP_0>;
333 CLUSTER_0_PD: power-domain-cpu-cluster0 {
334 #power-domain-cells = <0>;
335 domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>;
338 CLUSTER_1_PD: power-domain-cpu-cluster1 {
339 #power-domain-cells = <0>;
340 domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>;
345 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc";
347 glink-edge {
348 compatible = "qcom,glink-rpm";
351 qcom,rpm-msg-ram = <&rpm_msg_ram>;
354 rpm_requests: rpm-requests {
355 compatible = "qcom,rpm-sm6115";
356 qcom,glink-channels = "rpm_requests";
358 rpmcc: clock-controller {
359 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
361 clock-names = "xo";
362 #clock-cells = <1>;
365 rpmpd: power-controller {
366 compatible = "qcom,sm6115-rpmpd";
367 #power-domain-cells = <1>;
368 operating-points-v2 = <&rpmpd_opp_table>;
370 rpmpd_opp_table: opp-table {
371 compatible = "operating-points-v2";
374 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
378 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
382 opp-level = <RPM_SMD_LEVEL_SVS>;
386 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
390 opp-level = <RPM_SMD_LEVEL_NOM>;
394 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
398 opp-level = <RPM_SMD_LEVEL_TURBO>;
402 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
410 reserved_memory: reserved-memory {
411 #address-cells = <2>;
412 #size-cells = <2>;
417 no-map;
422 no-map;
427 no-map;
433 no-map;
436 qcom,rpm-msg-ram = <&rpm_msg_ram>;
441 no-map;
446 no-map;
451 no-map;
456 no-map;
461 no-map;
466 no-map;
471 no-map;
476 no-map;
481 no-map;
486 no-map;
491 no-map;
496 no-map;
500 compatible = "qcom,rmtfs-mem";
502 no-map;
504 qcom,client-id = <1>;
509 smp2p-adsp {
517 qcom,local-pid = <0>;
518 qcom,remote-pid = <2>;
520 adsp_smp2p_out: master-kernel {
521 qcom,entry-name = "master-kernel";
522 #qcom,smem-state-cells = <1>;
525 adsp_smp2p_in: slave-kernel {
526 qcom,entry-name = "slave-kernel";
528 interrupt-controller;
529 #interrupt-cells = <2>;
533 smp2p-cdsp {
541 qcom,local-pid = <0>;
542 qcom,remote-pid = <5>;
544 cdsp_smp2p_out: master-kernel {
545 qcom,entry-name = "master-kernel";
546 #qcom,smem-state-cells = <1>;
549 cdsp_smp2p_in: slave-kernel {
550 qcom,entry-name = "slave-kernel";
552 interrupt-controller;
553 #interrupt-cells = <2>;
557 smp2p-mpss {
565 qcom,local-pid = <0>;
566 qcom,remote-pid = <1>;
568 modem_smp2p_out: master-kernel {
569 qcom,entry-name = "master-kernel";
570 #qcom,smem-state-cells = <1>;
573 modem_smp2p_in: slave-kernel {
574 qcom,entry-name = "slave-kernel";
576 interrupt-controller;
577 #interrupt-cells = <2>;
582 compatible = "simple-bus";
583 #address-cells = <2>;
584 #size-cells = <2>;
586 dma-ranges = <0 0 0 0 0x10 0>;
589 compatible = "qcom,tcsr-mutex";
591 #hwlock-cells = <1>;
595 compatible = "qcom,sm6115-tcsr", "syscon";
600 compatible = "qcom,sm6115-tlmm";
604 reg-names = "west", "south", "east";
606 gpio-controller;
607 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
608 #gpio-cells = <2>;
609 interrupt-controller;
610 #interrupt-cells = <2>;
612 qup_i2c0_default: qup-i2c0-default-state {
615 drive-strength = <2>;
616 bias-pull-up;
619 qup_i2c1_default: qup-i2c1-default-state {
622 drive-strength = <2>;
623 bias-pull-up;
626 qup_i2c2_default: qup-i2c2-default-state {
629 drive-strength = <2>;
630 bias-pull-up;
633 qup_i2c3_default: qup-i2c3-default-state {
636 drive-strength = <2>;
637 bias-pull-up;
640 qup_i2c4_default: qup-i2c4-default-state {
643 drive-strength = <2>;
644 bias-pull-up;
647 qup_i2c5_default: qup-i2c5-default-state {
650 drive-strength = <2>;
651 bias-pull-up;
654 qup_spi0_default: qup-spi0-default-state {
657 drive-strength = <2>;
658 bias-pull-up;
661 qup_spi1_default: qup-spi1-default-state {
664 drive-strength = <2>;
665 bias-pull-up;
668 qup_spi2_default: qup-spi2-default-state {
671 drive-strength = <2>;
672 bias-pull-up;
675 qup_spi3_default: qup-spi3-default-state {
678 drive-strength = <2>;
679 bias-pull-up;
682 qup_spi4_default: qup-spi4-default-state {
685 drive-strength = <2>;
686 bias-pull-up;
689 qup_spi5_default: qup-spi5-default-state {
692 drive-strength = <2>;
693 bias-pull-up;
696 sdc1_state_on: sdc1-on-state {
697 clk-pins {
699 bias-disable;
700 drive-strength = <16>;
703 cmd-pins {
705 bias-pull-up;
706 drive-strength = <10>;
709 data-pins {
711 bias-pull-up;
712 drive-strength = <10>;
715 rclk-pins {
717 bias-pull-down;
721 sdc1_state_off: sdc1-off-state {
722 clk-pins {
724 bias-disable;
725 drive-strength = <2>;
728 cmd-pins {
730 bias-pull-up;
731 drive-strength = <2>;
734 data-pins {
736 bias-pull-up;
737 drive-strength = <2>;
740 rclk-pins {
742 bias-pull-down;
746 sdc2_state_on: sdc2-on-state {
747 clk-pins {
749 bias-disable;
750 drive-strength = <16>;
753 cmd-pins {
755 bias-pull-up;
756 drive-strength = <10>;
759 data-pins {
761 bias-pull-up;
762 drive-strength = <10>;
766 sdc2_state_off: sdc2-off-state {
767 clk-pins {
769 bias-disable;
770 drive-strength = <2>;
773 cmd-pins {
775 bias-pull-up;
776 drive-strength = <2>;
779 data-pins {
781 bias-pull-up;
782 drive-strength = <2>;
787 gcc: clock-controller@1400000 {
788 compatible = "qcom,gcc-sm6115";
791 clock-names = "bi_tcxo", "sleep_clk";
792 #clock-cells = <1>;
793 #reset-cells = <1>;
794 #power-domain-cells = <1>;
798 compatible = "qcom,sm6115-qusb2-phy";
800 #phy-cells = <0>;
803 clock-names = "cfg_ahb", "ref";
806 nvmem-cells = <&qusb2_hstx_trim>;
811 cryptobam: dma-controller@1b04000 {
812 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
816 clock-names = "bam_clk";
817 #dma-cells = <1>;
819 qcom,controlled-remotely;
828 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce";
831 clock-names = "core";
834 dma-names = "rx", "tx";
843 compatible = "qcom,sm6115-qmp-usb3-phy";
850 clock-names = "cfg_ahb",
857 reset-names = "phy", "phy_phy";
859 #clock-cells = <0>;
860 clock-output-names = "usb3_phy_pipe_clk_src";
862 #phy-cells = <0>;
864 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
870 compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
872 #address-cells = <1>;
873 #size-cells = <1>;
875 qusb2_hstx_trim: hstx-trim@25b {
880 gpu_speed_bin: gpu-speed-bin@6006 {
887 compatible = "qcom,prng-ee";
890 clock-names = "core";
894 compatible = "qcom,spmi-pmic-arb";
900 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
901 interrupt-names = "periph_irq";
905 #address-cells = <2>;
906 #size-cells = <0>;
907 interrupt-controller;
908 #interrupt-cells = <4>;
911 tsens0: thermal-sensor@4411000 {
912 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
918 interrupt-names = "uplow", "critical";
919 #thermal-sensor-cells = <1>;
923 compatible = "qcom,rpm-msg-ram";
928 compatible = "qcom,rpm-stats";
933 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
937 reg-names = "hc", "cqhci", "ice";
941 interrupt-names = "hc_irq", "pwr_irq";
947 clock-names = "iface", "core", "xo", "ice";
949 bus-width = <8>;
954 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
956 reg-names = "hc";
960 interrupt-names = "hc_irq", "pwr_irq";
965 clock-names = "iface", "core", "xo";
967 power-domains = <&rpmpd SM6115_VDDCX>;
968 operating-points-v2 = <&sdhc2_opp_table>;
972 bus-width = <4>;
973 qcom,dll-config = <0x0007642c>;
974 qcom,ddr-config = <0x80040868>;
977 sdhc2_opp_table: opp-table {
978 compatible = "operating-points-v2";
980 opp-100000000 {
981 opp-hz = /bits/ 64 <100000000>;
982 required-opps = <&rpmpd_opp_low_svs>;
985 opp-202000000 {
986 opp-hz = /bits/ 64 <202000000>;
987 required-opps = <&rpmpd_opp_nom>;
993 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
995 reg-names = "std", "ice";
998 phy-names = "ufsphy";
999 lanes-per-direction = <1>;
1000 #reset-cells = <1>;
1002 reset-names = "rst";
1004 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1015 clock-names = "core_clk",
1024 freq-table-hz = <50000000 200000000>,
1037 compatible = "qcom,sm6115-qmp-ufs-phy";
1039 #address-cells = <2>;
1040 #size-cells = <2>;
1044 clock-names = "ref", "ref_aux";
1046 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1049 reset-names = "ufsphy";
1056 #phy-cells = <0>;
1060 gpi_dma0: dma-controller@4a00000 {
1061 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
1073 dma-channels = <10>;
1074 dma-channel-mask = <0xf>;
1076 #dma-cells = <3>;
1081 compatible = "qcom,geni-se-qup";
1083 clock-names = "m-ahb", "s-ahb";
1086 #address-cells = <2>;
1087 #size-cells = <2>;
1093 compatible = "qcom,geni-i2c";
1095 clock-names = "se";
1097 pinctrl-names = "default";
1098 pinctrl-0 = <&qup_i2c0_default>;
1102 dma-names = "tx", "rx";
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1109 compatible = "qcom,geni-spi";
1111 clock-names = "se";
1113 pinctrl-names = "default";
1114 pinctrl-0 = <&qup_spi0_default>;
1118 dma-names = "tx", "rx";
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1125 compatible = "qcom,geni-i2c";
1127 clock-names = "se";
1129 pinctrl-names = "default";
1130 pinctrl-0 = <&qup_i2c1_default>;
1134 dma-names = "tx", "rx";
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1141 compatible = "qcom,geni-spi";
1143 clock-names = "se";
1145 pinctrl-names = "default";
1146 pinctrl-0 = <&qup_spi1_default>;
1150 dma-names = "tx", "rx";
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1157 compatible = "qcom,geni-i2c";
1159 clock-names = "se";
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&qup_i2c2_default>;
1166 dma-names = "tx", "rx";
1167 #address-cells = <1>;
1168 #size-cells = <0>;
1173 compatible = "qcom,geni-spi";
1175 clock-names = "se";
1177 pinctrl-names = "default";
1178 pinctrl-0 = <&qup_spi2_default>;
1182 dma-names = "tx", "rx";
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1189 compatible = "qcom,geni-i2c";
1191 clock-names = "se";
1193 pinctrl-names = "default";
1194 pinctrl-0 = <&qup_i2c3_default>;
1198 dma-names = "tx", "rx";
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1205 compatible = "qcom,geni-spi";
1207 clock-names = "se";
1209 pinctrl-names = "default";
1210 pinctrl-0 = <&qup_spi3_default>;
1214 dma-names = "tx", "rx";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1221 compatible = "qcom,geni-i2c";
1223 clock-names = "se";
1225 pinctrl-names = "default";
1226 pinctrl-0 = <&qup_i2c4_default>;
1230 dma-names = "tx", "rx";
1231 #address-cells = <1>;
1232 #size-cells = <0>;
1237 compatible = "qcom,geni-spi";
1239 clock-names = "se";
1241 pinctrl-names = "default";
1242 pinctrl-0 = <&qup_spi4_default>;
1246 dma-names = "tx", "rx";
1247 #address-cells = <1>;
1248 #size-cells = <0>;
1253 compatible = "qcom,geni-debug-uart";
1255 clock-names = "se";
1262 compatible = "qcom,geni-i2c";
1264 clock-names = "se";
1266 pinctrl-names = "default";
1267 pinctrl-0 = <&qup_i2c5_default>;
1271 dma-names = "tx", "rx";
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1278 compatible = "qcom,geni-spi";
1280 clock-names = "se";
1282 pinctrl-names = "default";
1283 pinctrl-0 = <&qup_spi5_default>;
1287 dma-names = "tx", "rx";
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1295 compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
1297 #address-cells = <2>;
1298 #size-cells = <2>;
1307 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
1309 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1311 assigned-clock-rates = <19200000>, <66666667>;
1315 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1318 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1319 qcom,select-utmi-as-pipe-clk;
1327 phy-names = "usb2-phy", "usb3-phy";
1331 snps,has-lpm-erratum;
1332 snps,hird-threshold = /bits/ 8 <0x10>;
1338 compatible = "qcom,adreno-610.0", "qcom,adreno";
1340 reg-names = "kgsl_3d0_reg_memory";
1349 clock-names = "core",
1359 operating-points-v2 = <&gpu_opp_table>;
1360 power-domains = <&rpmpd SM6115_VDDCX>;
1363 nvmem-cells = <&gpu_speed_bin>;
1364 nvmem-cell-names = "speed_bin";
1368 zap-shader {
1369 memory-region = <&pil_gpu_mem>;
1372 gpu_opp_table: opp-table {
1373 compatible = "operating-points-v2";
1375 opp-320000000 {
1376 opp-hz = /bits/ 64 <320000000>;
1377 required-opps = <&rpmpd_opp_low_svs>;
1378 opp-supported-hw = <0x1f>;
1381 opp-465000000 {
1382 opp-hz = /bits/ 64 <465000000>;
1383 required-opps = <&rpmpd_opp_svs>;
1384 opp-supported-hw = <0x1f>;
1387 opp-600000000 {
1388 opp-hz = /bits/ 64 <600000000>;
1389 required-opps = <&rpmpd_opp_svs_plus>;
1390 opp-supported-hw = <0x1f>;
1393 opp-745000000 {
1394 opp-hz = /bits/ 64 <745000000>;
1395 required-opps = <&rpmpd_opp_nom>;
1396 opp-supported-hw = <0xf>;
1399 opp-820000000 {
1400 opp-hz = /bits/ 64 <820000000>;
1401 required-opps = <&rpmpd_opp_nom_plus>;
1402 opp-supported-hw = <0x7>;
1405 opp-900000000 {
1406 opp-hz = /bits/ 64 <900000000>;
1407 required-opps = <&rpmpd_opp_turbo>;
1408 opp-supported-hw = <0x7>;
1412 opp-950000000 {
1413 opp-hz = /bits/ 64 <950000000>;
1414 required-opps = <&rpmpd_opp_turbo_plus>;
1415 opp-supported-hw = <0x4>;
1418 opp-980000000 {
1419 opp-hz = /bits/ 64 <980000000>;
1420 required-opps = <&rpmpd_opp_turbo_plus>;
1421 opp-supported-hw = <0x3>;
1427 compatible = "qcom,adreno-gmu-wrapper";
1429 reg-names = "gmu";
1430 power-domains = <&gpucc GPU_CX_GDSC>,
1432 power-domain-names = "cx", "gx";
1435 gpucc: clock-controller@5990000 {
1436 compatible = "qcom,sm6115-gpucc";
1441 #clock-cells = <1>;
1442 #reset-cells = <1>;
1443 #power-domain-cells = <1>;
1447 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
1448 "qcom,smmu-500", "arm,mmu-500";
1463 clock-names = "mem",
1466 power-domains = <&gpucc GPU_CX_GDSC>;
1468 #global-interrupts = <1>;
1469 #iommu-cells = <2>;
1472 mdss: display-subsystem@5e00000 {
1473 compatible = "qcom,sm6115-mdss";
1475 reg-names = "mdss";
1477 power-domains = <&dispcc MDSS_GDSC>;
1484 interrupt-controller;
1485 #interrupt-cells = <1>;
1490 #address-cells = <2>;
1491 #size-cells = <2>;
1496 mdp: display-controller@5e01000 {
1497 compatible = "qcom,sm6115-dpu";
1500 reg-names = "mdp", "vbif";
1508 clock-names = "bus",
1515 operating-points-v2 = <&mdp_opp_table>;
1516 power-domains = <&rpmpd SM6115_VDDCX>;
1518 interrupt-parent = <&mdss>;
1522 #address-cells = <1>;
1523 #size-cells = <0>;
1528 remote-endpoint = <&mdss_dsi0_in>;
1533 mdp_opp_table: opp-table {
1534 compatible = "operating-points-v2";
1536 opp-19200000 {
1537 opp-hz = /bits/ 64 <19200000>;
1538 required-opps = <&rpmpd_opp_min_svs>;
1541 opp-192000000 {
1542 opp-hz = /bits/ 64 <192000000>;
1543 required-opps = <&rpmpd_opp_low_svs>;
1546 opp-256000000 {
1547 opp-hz = /bits/ 64 <256000000>;
1548 required-opps = <&rpmpd_opp_svs>;
1551 opp-307200000 {
1552 opp-hz = /bits/ 64 <307200000>;
1553 required-opps = <&rpmpd_opp_svs_plus>;
1556 opp-384000000 {
1557 opp-hz = /bits/ 64 <384000000>;
1558 required-opps = <&rpmpd_opp_nom>;
1564 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1566 reg-names = "dsi_ctrl";
1568 interrupt-parent = <&mdss>;
1577 clock-names = "byte",
1584 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1586 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1588 operating-points-v2 = <&dsi_opp_table>;
1589 power-domains = <&rpmpd SM6115_VDDCX>;
1592 #address-cells = <1>;
1593 #size-cells = <0>;
1598 #address-cells = <1>;
1599 #size-cells = <0>;
1604 remote-endpoint = <&dpu_intf1_out>;
1615 dsi_opp_table: opp-table {
1616 compatible = "operating-points-v2";
1618 opp-19200000 {
1619 opp-hz = /bits/ 64 <19200000>;
1620 required-opps = <&rpmpd_opp_min_svs>;
1623 opp-164000000 {
1624 opp-hz = /bits/ 64 <164000000>;
1625 required-opps = <&rpmpd_opp_low_svs>;
1628 opp-187500000 {
1629 opp-hz = /bits/ 64 <187500000>;
1630 required-opps = <&rpmpd_opp_svs>;
1636 compatible = "qcom,dsi-phy-14nm-2290";
1640 reg-names = "dsi_phy",
1644 #clock-cells = <1>;
1645 #phy-cells = <0>;
1649 clock-names = "iface", "ref";
1655 dispcc: clock-controller@5f00000 {
1656 compatible = "qcom,sm6115-dispcc";
1663 #clock-cells = <1>;
1664 #reset-cells = <1>;
1665 #power-domain-cells = <1>;
1669 compatible = "qcom,sm6115-mpss-pas";
1672 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1678 interrupt-names = "wdog", "fatal", "ready", "handover",
1679 "stop-ack", "shutdown-ack";
1682 clock-names = "xo";
1684 power-domains = <&rpmpd SM6115_VDDCX>;
1686 memory-region = <&pil_modem_mem>;
1688 qcom,smem-states = <&modem_smp2p_out 0>;
1689 qcom,smem-state-names = "stop";
1693 glink-edge {
1696 qcom,remote-pid = <1>;
1702 compatible = "arm,coresight-stm", "arm,primecell";
1705 reg-names = "stm-base", "stm-stimulus-base";
1708 clock-names = "apb_pclk";
1712 out-ports {
1715 remote-endpoint = <&funnel_in0_in>;
1722 compatible = "arm,coresight-cti", "arm,primecell";
1726 clock-names = "apb_pclk";
1732 compatible = "arm,coresight-cti", "arm,primecell";
1736 clock-names = "apb_pclk";
1742 compatible = "arm,coresight-cti", "arm,primecell";
1746 clock-names = "apb_pclk";
1752 compatible = "arm,coresight-cti", "arm,primecell";
1756 clock-names = "apb_pclk";
1762 compatible = "arm,coresight-cti", "arm,primecell";
1766 clock-names = "apb_pclk";
1772 compatible = "arm,coresight-cti", "arm,primecell";
1776 clock-names = "apb_pclk";
1782 compatible = "arm,coresight-cti", "arm,primecell";
1786 clock-names = "apb_pclk";
1792 compatible = "arm,coresight-cti", "arm,primecell";
1796 clock-names = "apb_pclk";
1802 compatible = "arm,coresight-cti", "arm,primecell";
1806 clock-names = "apb_pclk";
1812 compatible = "arm,coresight-cti", "arm,primecell";
1816 clock-names = "apb_pclk";
1822 compatible = "arm,coresight-cti", "arm,primecell";
1826 clock-names = "apb_pclk";
1832 compatible = "arm,coresight-cti", "arm,primecell";
1836 clock-names = "apb_pclk";
1842 compatible = "arm,coresight-cti", "arm,primecell";
1846 clock-names = "apb_pclk";
1852 compatible = "arm,coresight-cti", "arm,primecell";
1856 clock-names = "apb_pclk";
1862 compatible = "arm,coresight-cti", "arm,primecell";
1866 clock-names = "apb_pclk";
1872 compatible = "arm,coresight-cti", "arm,primecell";
1876 clock-names = "apb_pclk";
1882 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1886 clock-names = "apb_pclk";
1890 out-ports {
1893 remote-endpoint = <&etr_in>;
1898 in-ports {
1901 remote-endpoint = <&etf_out>;
1908 compatible = "arm,coresight-tmc", "arm,primecell";
1912 clock-names = "apb_pclk";
1916 in-ports {
1919 remote-endpoint = <&merge_funnel_out>;
1924 out-ports {
1927 remote-endpoint = <&replicator_in>;
1934 compatible = "arm,coresight-tmc", "arm,primecell";
1938 clock-names = "apb_pclk";
1942 in-ports {
1945 remote-endpoint = <&replicator_out>;
1952 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1956 clock-names = "apb_pclk";
1960 out-ports {
1963 remote-endpoint = <&merge_funnel_in0>;
1968 in-ports {
1971 remote-endpoint = <&stm_out>;
1978 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1982 clock-names = "apb_pclk";
1986 out-ports {
1989 remote-endpoint = <&merge_funnel_in1>;
1994 in-ports {
1997 remote-endpoint = <&funnel_apss1_out>;
2004 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2008 clock-names = "apb_pclk";
2012 out-ports {
2015 remote-endpoint = <&etf_in>;
2020 in-ports {
2021 #address-cells = <1>;
2022 #size-cells = <0>;
2027 remote-endpoint = <&funnel_in0_out>;
2034 remote-endpoint = <&funnel_in1_out>;
2041 compatible = "arm,coresight-etm4x", "arm,primecell";
2045 clock-names = "apb_pclk";
2046 arm,coresight-loses-context-with-cpu;
2052 out-ports {
2055 remote-endpoint = <&funnel_apss0_in0>;
2062 compatible = "arm,coresight-etm4x", "arm,primecell";
2066 clock-names = "apb_pclk";
2067 arm,coresight-loses-context-with-cpu;
2073 out-ports {
2076 remote-endpoint = <&funnel_apss0_in1>;
2083 compatible = "arm,coresight-etm4x", "arm,primecell";
2087 clock-names = "apb_pclk";
2088 arm,coresight-loses-context-with-cpu;
2094 out-ports {
2097 remote-endpoint = <&funnel_apss0_in2>;
2104 compatible = "arm,coresight-etm4x", "arm,primecell";
2108 clock-names = "apb_pclk";
2109 arm,coresight-loses-context-with-cpu;
2115 out-ports {
2118 remote-endpoint = <&funnel_apss0_in3>;
2125 compatible = "arm,coresight-etm4x", "arm,primecell";
2129 clock-names = "apb_pclk";
2130 arm,coresight-loses-context-with-cpu;
2136 out-ports {
2139 remote-endpoint = <&funnel_apss0_in4>;
2146 compatible = "arm,coresight-etm4x", "arm,primecell";
2150 clock-names = "apb_pclk";
2151 arm,coresight-loses-context-with-cpu;
2157 out-ports {
2160 remote-endpoint = <&funnel_apss0_in5>;
2167 compatible = "arm,coresight-etm4x", "arm,primecell";
2171 clock-names = "apb_pclk";
2172 arm,coresight-loses-context-with-cpu;
2178 out-ports {
2181 remote-endpoint = <&funnel_apss0_in6>;
2188 compatible = "arm,coresight-etm4x", "arm,primecell";
2192 clock-names = "apb_pclk";
2193 arm,coresight-loses-context-with-cpu;
2199 out-ports {
2202 remote-endpoint = <&funnel_apss0_in7>;
2209 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2213 clock-names = "apb_pclk";
2217 out-ports {
2220 remote-endpoint = <&funnel_apss1_in>;
2225 in-ports {
2226 #address-cells = <1>;
2227 #size-cells = <0>;
2232 remote-endpoint = <&etm0_out>;
2239 remote-endpoint = <&etm1_out>;
2246 remote-endpoint = <&etm2_out>;
2253 remote-endpoint = <&etm3_out>;
2260 remote-endpoint = <&etm4_out>;
2267 remote-endpoint = <&etm5_out>;
2274 remote-endpoint = <&etm6_out>;
2281 remote-endpoint = <&etm7_out>;
2288 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2292 clock-names = "apb_pclk";
2296 out-ports {
2299 remote-endpoint = <&funnel_in1_in>;
2304 in-ports {
2307 remote-endpoint = <&funnel_apss0_out>;
2314 compatible = "qcom,sm6115-adsp-pas";
2317 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
2322 interrupt-names = "wdog", "fatal", "ready",
2323 "handover", "stop-ack";
2326 clock-names = "xo";
2328 power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
2331 memory-region = <&pil_adsp_mem>;
2333 qcom,smem-states = <&adsp_smp2p_out 0>;
2334 qcom,smem-state-names = "stop";
2338 glink-edge {
2341 qcom,remote-pid = <2>;
2346 qcom,glink-channels = "fastrpcglink-apps-dsp";
2348 qcom,non-secure-domain;
2349 #address-cells = <1>;
2350 #size-cells = <0>;
2352 compute-cb@3 {
2353 compatible = "qcom,fastrpc-compute-cb";
2358 compute-cb@4 {
2359 compatible = "qcom,fastrpc-compute-cb";
2364 compute-cb@5 {
2365 compatible = "qcom,fastrpc-compute-cb";
2370 compute-cb@6 {
2371 compatible = "qcom,fastrpc-compute-cb";
2376 compute-cb@7 {
2377 compatible = "qcom,fastrpc-compute-cb";
2386 compatible = "qcom,sm6115-cdsp-pas";
2389 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
2394 interrupt-names = "wdog", "fatal", "ready",
2395 "handover", "stop-ack";
2398 clock-names = "xo";
2400 power-domains = <&rpmpd SM6115_VDDCX>;
2402 memory-region = <&pil_cdsp_mem>;
2404 qcom,smem-states = <&cdsp_smp2p_out 0>;
2405 qcom,smem-state-names = "stop";
2409 glink-edge {
2412 qcom,remote-pid = <5>;
2417 qcom,glink-channels = "fastrpcglink-apps-dsp";
2419 qcom,non-secure-domain;
2420 #address-cells = <1>;
2421 #size-cells = <0>;
2423 compute-cb@1 {
2424 compatible = "qcom,fastrpc-compute-cb";
2429 compute-cb@2 {
2430 compatible = "qcom,fastrpc-compute-cb";
2435 compute-cb@3 {
2436 compatible = "qcom,fastrpc-compute-cb";
2441 compute-cb@4 {
2442 compatible = "qcom,fastrpc-compute-cb";
2447 compute-cb@5 {
2448 compatible = "qcom,fastrpc-compute-cb";
2453 compute-cb@6 {
2454 compatible = "qcom,fastrpc-compute-cb";
2465 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2467 #iommu-cells = <2>;
2468 #global-interrupts = <1>;
2538 compatible = "qcom,wcn3990-wifi";
2540 reg-names = "membase";
2541 memory-region = <&wlan_msa_mem>;
2555 qcom,msa-fixed-perm;
2560 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt";
2567 compatible = "qcom,sm6115-apcs-hmss-global",
2568 "qcom,msm8994-apcs-kpss-global";
2571 #mbox-cells = <1>;
2575 compatible = "arm,armv7-timer-mem";
2577 #address-cells = <2>;
2578 #size-cells = <2>;
2580 clock-frequency = <19200000>;
2584 frame-number = <0>;
2591 frame-number = <1>;
2598 frame-number = <2>;
2605 frame-number = <3>;
2612 frame-number = <4>;
2619 frame-number = <5>;
2626 frame-number = <6>;
2632 intc: interrupt-controller@f200000 {
2633 compatible = "arm,gic-v3";
2636 #interrupt-cells = <3>;
2637 interrupt-controller;
2638 interrupt-parent = <&intc>;
2639 #redistributor-regions = <1>;
2640 redistributor-stride = <0x0 0x20000>;
2645 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
2649 reg-names = "freq-domain0", "freq-domain1";
2651 clock-names = "xo", "alternate";
2653 #freq-domain-cells = <1>;
2654 #clock-cells = <1>;
2658 thermal-zones {
2659 mapss-thermal {
2660 polling-delay-passive = <0>;
2661 polling-delay = <0>;
2662 thermal-sensors = <&tsens0 0>;
2665 trip-point0 {
2671 trip-point1 {
2679 cdsp-hvx-thermal {
2680 polling-delay-passive = <0>;
2681 polling-delay = <0>;
2682 thermal-sensors = <&tsens0 1>;
2685 trip-point0 {
2691 trip-point1 {
2699 wlan-thermal {
2700 polling-delay-passive = <0>;
2701 polling-delay = <0>;
2702 thermal-sensors = <&tsens0 2>;
2705 trip-point0 {
2711 trip-point1 {
2719 camera-thermal {
2720 polling-delay-passive = <0>;
2721 polling-delay = <0>;
2722 thermal-sensors = <&tsens0 3>;
2725 trip-point0 {
2731 trip-point1 {
2739 video-thermal {
2740 polling-delay-passive = <0>;
2741 polling-delay = <0>;
2742 thermal-sensors = <&tsens0 4>;
2745 trip-point0 {
2751 trip-point1 {
2759 modem1-thermal {
2760 polling-delay-passive = <0>;
2761 polling-delay = <0>;
2762 thermal-sensors = <&tsens0 5>;
2765 trip-point0 {
2771 trip-point1 {
2779 cpu4-thermal {
2780 polling-delay-passive = <0>;
2781 polling-delay = <0>;
2782 thermal-sensors = <&tsens0 6>;
2785 cpu4_alert0: trip-point0 {
2791 cpu4_alert1: trip-point1 {
2805 cpu5-thermal {
2806 polling-delay-passive = <0>;
2807 polling-delay = <0>;
2808 thermal-sensors = <&tsens0 7>;
2811 cpu5_alert0: trip-point0 {
2817 cpu5_alert1: trip-point1 {
2831 cpu6-thermal {
2832 polling-delay-passive = <0>;
2833 polling-delay = <0>;
2834 thermal-sensors = <&tsens0 8>;
2837 cpu6_alert0: trip-point0 {
2843 cpu6_alert1: trip-point1 {
2857 cpu7-thermal {
2858 polling-delay-passive = <0>;
2859 polling-delay = <0>;
2860 thermal-sensors = <&tsens0 9>;
2863 cpu7_alert0: trip-point0 {
2869 cpu7_alert1: trip-point1 {
2883 cpu45-thermal {
2884 polling-delay-passive = <0>;
2885 polling-delay = <0>;
2886 thermal-sensors = <&tsens0 10>;
2889 cpu45_alert0: trip-point0 {
2895 cpu45_alert1: trip-point1 {
2909 cpu67-thermal {
2910 polling-delay-passive = <0>;
2911 polling-delay = <0>;
2912 thermal-sensors = <&tsens0 11>;
2915 cpu67_alert0: trip-point0 {
2921 cpu67_alert1: trip-point1 {
2935 cpu0123-thermal {
2936 polling-delay-passive = <0>;
2937 polling-delay = <0>;
2938 thermal-sensors = <&tsens0 12>;
2941 cpu0123_alert0: trip-point0 {
2947 cpu0123_alert1: trip-point1 {
2961 modem0-thermal {
2962 polling-delay-passive = <0>;
2963 polling-delay = <0>;
2964 thermal-sensors = <&tsens0 13>;
2967 trip-point0 {
2973 trip-point1 {
2981 display-thermal {
2982 polling-delay-passive = <0>;
2983 polling-delay = <0>;
2984 thermal-sensors = <&tsens0 14>;
2987 trip-point0 {
2993 trip-point1 {
3001 gpu-thermal {
3002 polling-delay-passive = <0>;
3003 polling-delay = <0>;
3004 thermal-sensors = <&tsens0 15>;
3007 trip-point0 {
3013 trip-point1 {
3023 compatible = "arm,armv8-timer";