Lines Matching +full:0 +full:x0007642c
27 #clock-cells = <0>;
32 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
44 clocks = <&cpufreq_hw 0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
62 reg = <0x0 0x1>;
63 clocks = <&cpufreq_hw 0>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x2>;
77 clocks = <&cpufreq_hw 0>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
90 reg = <0x0 0x3>;
91 clocks = <&cpufreq_hw 0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
104 reg = <0x0 0x100>;
123 reg = <0x0 0x101>;
137 reg = <0x0 0x102>;
151 reg = <0x0 0x103>;
203 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
206 arm,psci-suspend-param = <0x40000003>;
213 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
216 arm,psci-suspend-param = <0x40000003>;
225 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 {
228 arm,psci-suspend-param = <0x40000022>;
234 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 {
237 arm,psci-suspend-param = <0x41000044>;
243 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 {
246 arm,psci-suspend-param = <0x40000042>;
255 arm,psci-suspend-param = <0x41000044>;
273 reg = <0 0x80000000 0 0>;
286 #power-domain-cells = <0>;
292 #power-domain-cells = <0>;
298 #power-domain-cells = <0>;
304 #power-domain-cells = <0>;
310 #power-domain-cells = <0>;
316 #power-domain-cells = <0>;
322 #power-domain-cells = <0>;
328 #power-domain-cells = <0>;
334 #power-domain-cells = <0>;
339 #power-domain-cells = <0>;
352 mboxes = <&apcs_glb 0>;
416 reg = <0x0 0x45700000 0x0 0x600000>;
421 reg = <0x0 0x45e00000 0x0 0x140000>;
426 reg = <0x0 0x45fff000 0x0 0x1000>;
432 reg = <0x0 0x46000000 0x0 0x200000>;
440 reg = <0x0 0x46200000 0x0 0x1e00000>;
445 reg = <0x0 0x4ab00000 0x0 0x6900000>;
450 reg = <0x0 0x51400000 0x0 0x500000>;
455 reg = <0x0 0x51900000 0x0 0x100000>;
460 reg = <0x0 0x51a00000 0x0 0x1e00000>;
465 reg = <0x0 0x53800000 0x0 0x2800000>;
470 reg = <0x0 0x56100000 0x0 0x10000>;
475 reg = <0x0 0x56110000 0x0 0x5000>;
480 reg = <0x0 0x56115000 0x0 0x2000>;
485 reg = <0x0 0x5c000000 0x0 0x00f00000>;
490 reg = <0x0 0x5cf00000 0x0 0x0100000>;
495 reg = <0x0 0x60000000 0x0 0x3900000>;
501 reg = <0x0 0x89b01000 0x0 0x200000>;
517 qcom,local-pid = <0>;
541 qcom,local-pid = <0>;
565 qcom,local-pid = <0>;
581 soc: soc@0 {
585 ranges = <0 0 0 0 0x10 0>;
586 dma-ranges = <0 0 0 0 0x10 0>;
590 reg = <0x0 0x00340000 0x0 0x20000>;
596 reg = <0x0 0x003c0000 0x0 0x40000>;
601 reg = <0x0 0x00500000 0x0 0x400000>,
602 <0x0 0x00900000 0x0 0x400000>,
603 <0x0 0x00d00000 0x0 0x400000>;
607 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
789 reg = <0x0 0x01400000 0x0 0x1f0000>;
799 reg = <0x0 0x01613000 0x0 0x180>;
800 #phy-cells = <0>;
813 reg = <0x0 0x01b04000 0x0 0x24000>;
818 qcom,ee = <0>;
820 iommus = <&apps_smmu 0x92 0>,
821 <&apps_smmu 0x94 0x11>,
822 <&apps_smmu 0x96 0x11>,
823 <&apps_smmu 0x98 0x1>,
824 <&apps_smmu 0x9F 0>;
829 reg = <0x0 0x01b3a000 0x0 0x6000>;
835 iommus = <&apps_smmu 0x92 0>,
836 <&apps_smmu 0x94 0x11>,
837 <&apps_smmu 0x96 0x11>,
838 <&apps_smmu 0x98 0x1>,
839 <&apps_smmu 0x9F 0>;
844 reg = <0x0 0x01615000 0x0 0x1000>;
859 #clock-cells = <0>;
862 #phy-cells = <0>;
864 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
871 reg = <0x0 0x01b40000 0x0 0x7000>;
876 reg = <0x25b 0x1>;
881 reg = <0x6006 0x2>;
888 reg = <0x0 0x01b53000 0x0 0x1000>;
895 reg = <0x0 0x01c40000 0x0 0x1100>,
896 <0x0 0x01e00000 0x0 0x2000000>,
897 <0x0 0x03e00000 0x0 0x100000>,
898 <0x0 0x03f00000 0x0 0xa0000>,
899 <0x0 0x01c0a000 0x0 0x26000>;
903 qcom,ee = <0>;
904 qcom,channel = <0>;
906 #size-cells = <0>;
913 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */
914 <0x0 0x04410000 0x0 0x8>; /* SROT */
924 reg = <0x0 0x045f0000 0x0 0x7000>;
929 reg = <0x0 0x04690000 0x0 0x10000>;
934 reg = <0x0 0x04744000 0x0 0x1000>,
935 <0x0 0x04745000 0x0 0x1000>,
936 <0x0 0x04748000 0x0 0x8000>;
955 reg = <0x0 0x04784000 0x0 0x1000>;
969 iommus = <&apps_smmu 0x00a0 0x0>;
973 qcom,dll-config = <0x0007642c>;
974 qcom,ddr-config = <0x80040868>;
994 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
1005 iommus = <&apps_smmu 0x100 0>;
1025 <0 0>,
1026 <0 0>,
1028 <0 0>,
1029 <0 0>,
1030 <0 0>,
1038 reg = <0x0 0x04807000 0x0 0x1c4>;
1048 resets = <&ufs_mem_hc 0>;
1053 reg = <0x0 0x04807400 0x0 0x098>,
1054 <0x0 0x04807600 0x0 0x130>,
1055 <0x0 0x04807c00 0x0 0x16c>;
1056 #phy-cells = <0>;
1062 reg = <0x0 0x04a00000 0x0 0x60000>;
1074 dma-channel-mask = <0xf>;
1075 iommus = <&apps_smmu 0xf6 0x0>;
1082 reg = <0x0 0x04ac0000 0x0 0x2000>;
1088 iommus = <&apps_smmu 0xe3 0x0>;
1094 reg = <0x0 0x04a80000 0x0 0x4000>;
1098 pinctrl-0 = <&qup_i2c0_default>;
1100 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1101 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1104 #size-cells = <0>;
1110 reg = <0x0 0x04a80000 0x0 0x4000>;
1114 pinctrl-0 = <&qup_spi0_default>;
1116 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1117 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1120 #size-cells = <0>;
1126 reg = <0x0 0x04a84000 0x0 0x4000>;
1130 pinctrl-0 = <&qup_i2c1_default>;
1132 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1136 #size-cells = <0>;
1142 reg = <0x0 0x04a84000 0x0 0x4000>;
1146 pinctrl-0 = <&qup_spi1_default>;
1148 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1152 #size-cells = <0>;
1158 reg = <0x0 0x04a88000 0x0 0x4000>;
1162 pinctrl-0 = <&qup_i2c2_default>;
1164 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1168 #size-cells = <0>;
1174 reg = <0x0 0x04a88000 0x0 0x4000>;
1178 pinctrl-0 = <&qup_spi2_default>;
1180 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1184 #size-cells = <0>;
1190 reg = <0x0 0x04a8c000 0x0 0x4000>;
1194 pinctrl-0 = <&qup_i2c3_default>;
1196 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1200 #size-cells = <0>;
1206 reg = <0x0 0x04a8c000 0x0 0x4000>;
1210 pinctrl-0 = <&qup_spi3_default>;
1212 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1216 #size-cells = <0>;
1222 reg = <0x0 0x04a90000 0x0 0x4000>;
1226 pinctrl-0 = <&qup_i2c4_default>;
1228 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1232 #size-cells = <0>;
1238 reg = <0x0 0x04a90000 0x0 0x4000>;
1242 pinctrl-0 = <&qup_spi4_default>;
1244 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1248 #size-cells = <0>;
1254 reg = <0x0 0x04a90000 0x0 0x4000>;
1263 reg = <0x0 0x04a94000 0x0 0x4000>;
1267 pinctrl-0 = <&qup_i2c5_default>;
1269 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1273 #size-cells = <0>;
1279 reg = <0x0 0x04a94000 0x0 0x4000>;
1283 pinctrl-0 = <&qup_spi5_default>;
1285 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1289 #size-cells = <0>;
1296 reg = <0x0 0x04ef8800 0x0 0x400>;
1324 reg = <0x0 0x04e00000 0x0 0xcd00>;
1328 iommus = <&apps_smmu 0x120 0x0>;
1332 snps,hird-threshold = /bits/ 8 <0x10>;
1339 reg = <0x0 0x05900000 0x0 0x40000>;
1358 iommus = <&adreno_smmu 0 1>;
1378 opp-supported-hw = <0x1f>;
1384 opp-supported-hw = <0x1f>;
1390 opp-supported-hw = <0x1f>;
1396 opp-supported-hw = <0xf>;
1402 opp-supported-hw = <0x7>;
1408 opp-supported-hw = <0x7>;
1415 opp-supported-hw = <0x4>;
1421 opp-supported-hw = <0x3>;
1428 reg = <0x0 0x0596a000 0x0 0x30000>;
1437 reg = <0x0 0x05990000 0x0 0x9000>;
1449 reg = <0x0 0x059a0000 0x0 0x10000>;
1474 reg = <0x0 0x05e00000 0x0 0x1000>;
1487 iommus = <&apps_smmu 0x420 0x2>,
1488 <&apps_smmu 0x421 0x0>;
1498 reg = <0x0 0x05e01000 0x0 0x8f000>,
1499 <0x0 0x05eb0000 0x0 0x2008>;
1519 interrupts = <0>;
1523 #size-cells = <0>;
1525 port@0 {
1526 reg = <0>;
1565 reg = <0x0 0x05e94000 0x0 0x400>;
1586 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1593 #size-cells = <0>;
1599 #size-cells = <0>;
1601 port@0 {
1602 reg = <0>;
1637 reg = <0x0 0x05e94400 0x0 0x100>,
1638 <0x0 0x05e94500 0x0 0x300>,
1639 <0x0 0x05e94800 0x0 0x188>;
1645 #phy-cells = <0>;
1657 reg = <0x0 0x05f00000 0 0x20000>;
1660 <&mdss_dsi0_phy 0>,
1670 reg = <0x0 0x06080000 0x0 0x100>;
1673 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1688 qcom,smem-states = <&modem_smp2p_out 0>;
1703 reg = <0x0 0x08002000 0x0 0x1000>,
1704 <0x0 0x0e280000 0x0 0x180000>;
1723 reg = <0x0 0x08010000 0x0 0x1000>;
1733 reg = <0x0 0x08011000 0x0 0x1000>;
1743 reg = <0x0 0x08012000 0x0 0x1000>;
1753 reg = <0x0 0x08013000 0x0 0x1000>;
1763 reg = <0x0 0x08014000 0x0 0x1000>;
1773 reg = <0x0 0x08015000 0x0 0x1000>;
1783 reg = <0x0 0x08016000 0x0 0x1000>;
1793 reg = <0x0 0x08017000 0x0 0x1000>;
1803 reg = <0x0 0x08018000 0x0 0x1000>;
1813 reg = <0x0 0x08019000 0x0 0x1000>;
1823 reg = <0x0 0x0801a000 0x0 0x1000>;
1833 reg = <0x0 0x0801b000 0x0 0x1000>;
1843 reg = <0x0 0x0801c000 0x0 0x1000>;
1853 reg = <0x0 0x0801d000 0x0 0x1000>;
1863 reg = <0x0 0x0801e000 0x0 0x1000>;
1873 reg = <0x0 0x0801f000 0x0 0x1000>;
1883 reg = <0x0 0x08046000 0x0 0x1000>;
1909 reg = <0x0 0x08047000 0x0 0x1000>;
1935 reg = <0x0 0x08048000 0x0 0x1000>;
1953 reg = <0x0 0x08041000 0x0 0x1000>;
1979 reg = <0x0 0x08042000 0x0 0x1000>;
2005 reg = <0x0 0x08045000 0x0 0x1000>;
2022 #size-cells = <0>;
2024 port@0 {
2025 reg = <0>;
2042 reg = <0x0 0x09040000 0x0 0x1000>;
2063 reg = <0x0 0x09140000 0x0 0x1000>;
2084 reg = <0x0 0x09240000 0x0 0x1000>;
2105 reg = <0x0 0x09340000 0x0 0x1000>;
2126 reg = <0x0 0x09440000 0x0 0x1000>;
2147 reg = <0x0 0x09540000 0x0 0x1000>;
2168 reg = <0x0 0x09640000 0x0 0x1000>;
2189 reg = <0x0 0x09740000 0x0 0x1000>;
2210 reg = <0x0 0x09800000 0x0 0x1000>;
2227 #size-cells = <0>;
2229 port@0 {
2230 reg = <0>;
2289 reg = <0x0 0x09810000 0x0 0x1000>;
2315 reg = <0x0 0x0ab00000 0x0 0x100>;
2318 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2333 qcom,smem-states = <&adsp_smp2p_out 0>;
2350 #size-cells = <0>;
2355 iommus = <&apps_smmu 0x01c3 0x0>;
2361 iommus = <&apps_smmu 0x01c4 0x0>;
2367 iommus = <&apps_smmu 0x01c5 0x0>;
2373 iommus = <&apps_smmu 0x01c6 0x0>;
2379 iommus = <&apps_smmu 0x01c7 0x0>;
2387 reg = <0x0 0x0b300000 0x0 0x100000>;
2390 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2404 qcom,smem-states = <&cdsp_smp2p_out 0>;
2421 #size-cells = <0>;
2426 iommus = <&apps_smmu 0x0c01 0x0>;
2432 iommus = <&apps_smmu 0x0c02 0x0>;
2438 iommus = <&apps_smmu 0x0c03 0x0>;
2444 iommus = <&apps_smmu 0x0c04 0x0>;
2450 iommus = <&apps_smmu 0x0c05 0x0>;
2456 iommus = <&apps_smmu 0x0c06 0x0>;
2466 reg = <0x0 0x0c600000 0x0 0x80000>;
2539 reg = <0x0 0x0c800000 0x0 0x800000>;
2554 iommus = <&apps_smmu 0x1a0 0x1>;
2561 reg = <0x0 0x0f017000 0x0 0x1000>;
2569 reg = <0x0 0x0f111000 0x0 0x1000>;
2576 reg = <0x0 0x0f120000 0x0 0x1000>;
2583 reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>;
2584 frame-number = <0>;
2590 reg = <0x0 0x0f123000 0x0 0x1000>;
2597 reg = <0x0 0x0f124000 0x0 0x1000>;
2604 reg = <0x0 0x0f125000 0x0 0x1000>;
2611 reg = <0x0 0x0f126000 0x0 0x1000>;
2618 reg = <0x0 0x0f127000 0x0 0x1000>;
2625 reg = <0x0 0x0f128000 0x0 0x1000>;
2634 reg = <0x0 0x0f200000 0x0 0x10000>,
2635 <0x0 0x0f300000 0x0 0x100000>;
2640 redistributor-stride = <0x0 0x20000>;
2646 reg = <0x0 0x0f521000 0x0 0x1000>,
2647 <0x0 0x0f523000 0x0 0x1000>;
2660 polling-delay-passive = <0>;
2661 polling-delay = <0>;
2662 thermal-sensors = <&tsens0 0>;
2680 polling-delay-passive = <0>;
2681 polling-delay = <0>;
2700 polling-delay-passive = <0>;
2701 polling-delay = <0>;
2720 polling-delay-passive = <0>;
2721 polling-delay = <0>;
2740 polling-delay-passive = <0>;
2741 polling-delay = <0>;
2760 polling-delay-passive = <0>;
2761 polling-delay = <0>;
2780 polling-delay-passive = <0>;
2781 polling-delay = <0>;
2806 polling-delay-passive = <0>;
2807 polling-delay = <0>;
2832 polling-delay-passive = <0>;
2833 polling-delay = <0>;
2858 polling-delay-passive = <0>;
2859 polling-delay = <0>;
2884 polling-delay-passive = <0>;
2885 polling-delay = <0>;
2910 polling-delay-passive = <0>;
2911 polling-delay = <0>;
2936 polling-delay-passive = <0>;
2937 polling-delay = <0>;
2962 polling-delay-passive = <0>;
2963 polling-delay = <0>;
2982 polling-delay-passive = <0>;
2983 polling-delay = <0>;
3002 polling-delay-passive = <0>;
3003 polling-delay = <0>;
3027 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;