dts/qcom/sm4450.dtsi

1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 	interrupt-parent = <&intc>;
12 	#address-cells = <2>;
13 	#size-cells = <2>;
18 		xo_board: xo-board {
19 			compatible = "fixed-clock";
20 			clock-frequency = <76800000>;
21 			#clock-cells = <0>;
24 		sleep_clk: sleep-clk {
25 			compatible = "fixed-clock";
26 			clock-frequency = <32000>;
27 			#clock-cells = <0>;
32 		#address-cells = <2>;
33 		#size-cells = <0>;
37 			compatible = "arm,cortex-a55";
39 			enable-method = "psci";
40 			next-level-cache = <&L2_0>;
41 			power-domains = <&CPU_PD0>;
42 			power-domain-names = "psci";
43 			#cooling-cells = <2>;
45 			L2_0: l2-cache {
47 				cache-level = <2>;
48 				cache-unified;
49 				next-level-cache = <&L3_0>;
51 				L3_0: l3-cache {
53 					cache-level = <3>;
54 					cache-unified;
61 			compatible = "arm,cortex-a55";
63 			enable-method = "psci";
64 			next-level-cache = <&L2_100>;
65 			power-domains = <&CPU_PD0>;
66 			power-domain-names = "psci";
67 			#cooling-cells = <2>;
69 			L2_100: l2-cache {
71 				cache-level = <2>;
72 				cache-unified;
73 				next-level-cache = <&L3_0>;
79 			compatible = "arm,cortex-a55";
81 			enable-method = "psci";
82 			next-level-cache = <&L2_200>;
83 			power-domains = <&CPU_PD0>;
84 			power-domain-names = "psci";
85 			#cooling-cells = <2>;
87 			L2_200: l2-cache {
89 				cache-level = <2>;
90 				cache-unified;
91 				next-level-cache = <&L3_0>;
97 			compatible = "arm,cortex-a55";
99 			enable-method = "psci";
100 			next-level-cache = <&L2_300>;
101 			power-domains = <&CPU_PD0>;
102 			power-domain-names = "psci";
103 			#cooling-cells = <2>;
105 			L2_300: l2-cache {
107 				cache-level = <2>;
108 				cache-unified;
109 				next-level-cache = <&L3_0>;
115 			compatible = "arm,cortex-a55";
117 			enable-method = "psci";
118 			next-level-cache = <&L2_400>;
119 			power-domains = <&CPU_PD0>;
120 			power-domain-names = "psci";
121 			#cooling-cells = <2>;
123 			L2_400: l2-cache {
125 				cache-level = <2>;
126 				cache-unified;
127 				next-level-cache = <&L3_0>;
133 			compatible = "arm,cortex-a55";
135 			enable-method = "psci";
136 			next-level-cache = <&L2_500>;
137 			power-domains = <&CPU_PD0>;
138 			power-domain-names = "psci";
139 			#cooling-cells = <2>;
141 			L2_500: l2-cache {
143 				cache-level = <2>;
144 				cache-unified;
145 				next-level-cache = <&L3_0>;
151 			compatible = "arm,cortex-a78";
153 			enable-method = "psci";
154 			next-level-cache = <&L2_600>;
155 			power-domains = <&CPU_PD0>;
156 			power-domain-names = "psci";
157 			#cooling-cells = <2>;
159 			L2_600: l2-cache {
161 				cache-level = <2>;
162 				cache-unified;
163 				next-level-cache = <&L3_0>;
169 			compatible = "arm,cortex-a78";
171 			enable-method = "psci";
172 			next-level-cache = <&L2_700>;
173 			power-domains = <&CPU_PD0>;
174 			power-domain-names = "psci";
175 			#cooling-cells = <2>;
177 			L2_700: l2-cache {
179 				cache-level = <2>;
180 				cache-unified;
181 				next-level-cache = <&L3_0>;
185 		cpu-map {
221 		idle-states {
222 			entry-method = "psci";
224 			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
225 				compatible = "arm,idle-state";
226 				arm,psci-suspend-param = <0x40000004>;
227 				entry-latency-us = <800>;
228 				exit-latency-us = <750>;
229 				min-residency-us = <4090>;
230 				local-timer-stop;
233 			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
234 				compatible = "arm,idle-state";
235 				arm,psci-suspend-param = <0x40000004>;
236 				entry-latency-us = <600>;
237 				exit-latency-us = <1550>;
238 				min-residency-us = <4791>;
239 				local-timer-stop;
243 		domain-idle-states {
244 			CLUSTER_SLEEP_0: cluster-sleep-0 {
245 				compatible = "domain-idle-state";
246 				arm,psci-suspend-param = <0x41000044>;
247 				entry-latency-us = <1050>;
248 				exit-latency-us = <2500>;
249 				min-residency-us = <5309>;
252 			CLUSTER_SLEEP_1: cluster-sleep-1 {
253 				compatible = "domain-idle-state";
254 				arm,psci-suspend-param = <0x41003344>;
255 				entry-latency-us = <1561>;
256 				exit-latency-us = <2801>;
257 				min-residency-us = <8550>;
269 		compatible = "arm,armv8-pmuv3";
274 		compatible = "arm,psci-1.0";
277 		CPU_PD0: power-domain-cpu0 {
278 			#power-domain-cells = <0>;
279 			power-domains = <&CLUSTER_PD>;
280 			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
283 		CPU_PD1: power-domain-cpu1 {
284 			#power-domain-cells = <0>;
285 			power-domains = <&CLUSTER_PD>;
286 			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
289 		CPU_PD2: power-domain-cpu2 {
290 			#power-domain-cells = <0>;
291 			power-domains = <&CLUSTER_PD>;
292 			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
295 		CPU_PD3: power-domain-cpu3 {
296 			#power-domain-cells = <0>;
297 			power-domains = <&CLUSTER_PD>;
298 			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
301 		CPU_PD4: power-domain-cpu4 {
302 			#power-domain-cells = <0>;
303 			power-domains = <&CLUSTER_PD>;
304 			domain-idle-states = <&BIG_CPU_SLEEP_0>;
307 		CPU_PD5: power-domain-cpu5 {
308 			#power-domain-cells = <0>;
309 			power-domains = <&CLUSTER_PD>;
310 			domain-idle-states = <&BIG_CPU_SLEEP_0>;
313 		CPU_PD6: power-domain-cpu6 {
314 			#power-domain-cells = <0>;
315 			power-domains = <&CLUSTER_PD>;
316 			domain-idle-states = <&BIG_CPU_SLEEP_0>;
319 		CPU_PD7: power-domain-cpu7 {
320 			#power-domain-cells = <0>;
321 			power-domains = <&CLUSTER_PD>;
322 			domain-idle-states = <&BIG_CPU_SLEEP_0>;
325 		CLUSTER_PD: power-domain-cpu-cluster0 {
326 			#power-domain-cells = <0>;
327 			domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
332 		#address-cells = <2>;
333 		#size-cells = <2>;
335 		dma-ranges = <0 0 0 0 0x10 0>;
336 		compatible = "simple-bus";
339 			compatible = "qcom,tcsr-mutex";
341 			#hwlock-cells = <1>;
344 		pdc: interrupt-controller@b220000 {
345 			compatible = "qcom,sm4450-pdc", "qcom,pdc";
347 			qcom,pdc-ranges = <0 480 94>, <94 494 31>,
349 			#interrupt-cells = <2>;
350 			interrupt-parent = <&intc>;
351 			interrupt-controller;
354 		intc: interrupt-controller@17200000 {
355 			compatible = "arm,gic-v3";
359 			#interrupt-cells = <3>;
360 			interrupt-controller;
361 			#redistributor-regions = <1>;
362 			redistributor-stride = <0x0 0x20000>;
366 			compatible = "arm,armv7-timer-mem";
369 			#address-cells = <1>;
370 			#size-cells = <1>;
375 				frame-number = <0>;
382 				frame-number = <1>;
389 				frame-number = <2>;
396 				frame-number = <3>;
403 				frame-number = <4>;
410 				frame-number = <5>;
417 				frame-number = <6>;
425 		compatible = "arm,armv8-timer";