Lines Matching +full:domain +full:- +full:idle +full:- +full:states
1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom,rpmhpd.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
19 interrupt-parent = <&intc>;
24 xo_board: xo-board {
25 compatible = "fixed-clock";
26 clock-frequency = <76800000>;
27 #clock-cells = <0>;
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
32 clock-frequency = <32000>;
33 #clock-cells = <0>;
38 #address-cells = <2>;
39 #size-cells = <0>;
43 compatible = "arm,cortex-a55";
46 enable-method = "psci";
47 power-domains = <&CPU_PD0>;
48 power-domain-names = "psci";
49 qcom,freq-domain = <&cpufreq_hw 0>;
50 capacity-dmips-mhz = <1024>;
51 dynamic-power-coefficient = <100>;
52 next-level-cache = <&L2_0>;
54 L2_0: l2-cache {
56 cache-level = <2>;
57 cache-unified;
58 next-level-cache = <&L3_0>;
59 L3_0: l3-cache {
61 cache-level = <3>;
62 cache-unified;
69 compatible = "arm,cortex-a55";
72 enable-method = "psci";
73 power-domains = <&CPU_PD1>;
74 power-domain-names = "psci";
75 qcom,freq-domain = <&cpufreq_hw 0>;
76 capacity-dmips-mhz = <1024>;
77 dynamic-power-coefficient = <100>;
78 next-level-cache = <&L2_100>;
80 L2_100: l2-cache {
82 cache-level = <2>;
83 cache-unified;
84 next-level-cache = <&L3_0>;
90 compatible = "arm,cortex-a55";
93 enable-method = "psci";
94 power-domains = <&CPU_PD2>;
95 power-domain-names = "psci";
96 qcom,freq-domain = <&cpufreq_hw 0>;
97 capacity-dmips-mhz = <1024>;
98 dynamic-power-coefficient = <100>;
99 next-level-cache = <&L2_200>;
101 L2_200: l2-cache {
103 cache-level = <2>;
104 cache-unified;
105 next-level-cache = <&L3_0>;
111 compatible = "arm,cortex-a55";
114 enable-method = "psci";
115 power-domains = <&CPU_PD3>;
116 power-domain-names = "psci";
117 qcom,freq-domain = <&cpufreq_hw 0>;
118 capacity-dmips-mhz = <1024>;
119 dynamic-power-coefficient = <100>;
120 next-level-cache = <&L2_300>;
122 L2_300: l2-cache {
124 cache-level = <2>;
125 cache-unified;
126 next-level-cache = <&L3_0>;
130 cpu-map {
150 idle-states {
151 entry-method = "psci";
153 CPU_OFF: cpu-sleep-0 {
154 compatible = "arm,idle-state";
155 entry-latency-us = <235>;
156 exit-latency-us = <428>;
157 min-residency-us = <1774>;
158 arm,psci-suspend-param = <0x40000003>;
159 local-timer-stop;
162 CPU_RAIL_OFF: cpu-rail-sleep-1 {
163 compatible = "arm,idle-state";
164 entry-latency-us = <800>;
165 exit-latency-us = <750>;
166 min-residency-us = <4090>;
167 arm,psci-suspend-param = <0x40000004>;
168 local-timer-stop;
173 domain-idle-states {
174 CLUSTER_SLEEP_0: cluster-sleep-0 {
175 compatible = "domain-idle-state";
176 arm,psci-suspend-param = <0x41000044>;
177 entry-latency-us = <1050>;
178 exit-latency-us = <2500>;
179 min-residency-us = <5309>;
182 CLUSTER_SLEEP_1: cluster-sleep-1 {
183 compatible = "domain-idle-state";
184 arm,psci-suspend-param = <0x41001344>;
185 entry-latency-us = <2761>;
186 exit-latency-us = <3964>;
187 min-residency-us = <8467>;
190 CLUSTER_SLEEP_2: cluster-sleep-2 {
191 compatible = "domain-idle-state";
192 arm,psci-suspend-param = <0x4100b344>;
193 entry-latency-us = <2793>;
194 exit-latency-us = <4023>;
195 min-residency-us = <9826>;
202 compatible = "qcom,scm-sdx75", "qcom,scm";
212 compatible = "arm,armv8-pmuv3";
217 compatible = "arm,psci-1.0";
220 CPU_PD0: power-domain-cpu0 {
221 #power-domain-cells = <0>;
222 power-domains = <&CLUSTER_PD>;
223 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
226 CPU_PD1: power-domain-cpu1 {
227 #power-domain-cells = <0>;
228 power-domains = <&CLUSTER_PD>;
229 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
232 CPU_PD2: power-domain-cpu2 {
233 #power-domain-cells = <0>;
234 power-domains = <&CLUSTER_PD>;
235 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
238 CPU_PD3: power-domain-cpu3 {
239 #power-domain-cells = <0>;
240 power-domains = <&CLUSTER_PD>;
241 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
244 CLUSTER_PD: power-domain-cpu-cluster0 {
245 #power-domain-cells = <0>;
246 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
250 reserved-memory {
251 #address-cells = <2>;
252 #size-cells = <2>;
255 gunyah_hyp_mem: gunyah-hyp@80000000 {
257 no-map;
260 hyp_elf_package_mem: hyp-elf-package@80800000 {
262 no-map;
265 access_control_db_mem: access-control-db@81380000 {
267 no-map;
272 no-map;
275 trusted_apps_mem: trusted-apps@81780000 {
277 no-map;
280 xbl_ramdump_mem: xbl-ramdump@87a00000 {
282 no-map;
285 cpucp_fw_mem: cpucp-fw@87c00000 {
287 no-map;
290 xbl_dtlog_mem: xbl-dtlog@87d00000 {
292 no-map;
295 xbl_sc_mem: xbl-sc@87d40000 {
297 no-map;
300 modem_efs_shared_mem: modem-efs-shared@87d80000 {
302 no-map;
305 aop_image_mem: aop-image@87e00000 {
307 no-map;
312 no-map;
315 aop_cmd_db_mem: aop-cmd-db@87ee0000 {
316 compatible = "qcom,cmd-db";
318 no-map;
321 aop_config_mem: aop-config@87f00000 {
323 no-map;
326 ipa_fw_mem: ipa-fw@87f20000 {
328 no-map;
333 no-map;
336 tme_crashdump_mem: tme-crashdump@87f31000 {
338 no-map;
341 tme_log_mem: tme-log@87f71000 {
343 no-map;
346 uefi_log_mem: uefi-log@87f75000 {
348 no-map;
353 no-map;
356 audio_heap_mem: audio-heap@88b00000 {
357 compatible = "shared-dma-pool";
359 no-map;
362 mpss_dsmharq_mem: mpss-dsmharq@88f00000 {
364 no-map;
367 q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
369 no-map;
374 no-map;
377 gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
379 no-map;
382 smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
384 no-map;
387 hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
389 no-map;
395 memory-region = <&smem_mem>;
400 compatible = "simple-bus";
401 #address-cells = <2>;
402 #size-cells = <2>;
404 dma-ranges = <0 0 0 0 0x10 0>;
406 gcc: clock-controller@80000 {
407 compatible = "qcom,sdx75-gcc";
424 #clock-cells = <1>;
425 #reset-cells = <1>;
426 #power-domain-cells = <1>;
430 compatible = "qcom,geni-se-qup";
434 clock-names = "m-ahb",
435 "s-ahb";
437 #address-cells = <2>;
438 #size-cells = <2>;
443 compatible = "qcom,geni-debug-uart";
446 clock-names = "se";
448 pinctrl-0 = <&qupv3_se1_2uart_active>;
449 pinctrl-1 = <&qupv3_se1_2uart_sleep>;
450 pinctrl-names = "default",
457 compatible = "qcom,tcsr-mutex";
459 #hwlock-cells = <1>;
462 pdc: interrupt-controller@b220000 {
463 compatible = "qcom,sdx75-pdc", "qcom,pdc";
466 qcom,pdc-ranges = <0 147 52>,
469 #interrupt-cells = <2>;
470 interrupt-parent = <&intc>;
471 interrupt-controller;
475 compatible = "qcom,spmi-pmic-arb";
481 reg-names = "core",
486 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
487 interrupt-names = "periph_irq";
490 qcom,bus-id = <0>;
491 #address-cells = <2>;
492 #size-cells = <0>;
493 interrupt-controller;
494 #interrupt-cells = <4>;
498 compatible = "qcom,sdx75-tlmm";
501 gpio-controller;
502 #gpio-cells = <2>;
503 gpio-ranges = <&tlmm 0 0 133>;
504 interrupt-controller;
505 #interrupt-cells = <2>;
506 wakeup-parent = <&pdc>;
508 qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
509 tx-pins {
512 drive-strength = <2>;
513 bias-disable;
516 rx-pins {
519 drive-strength = <2>;
520 bias-disable;
524 qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
527 drive-strength = <2>;
528 bias-pull-down;
533 compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
535 #iommu-cells = <2>;
536 #global-interrupts = <2>;
537 dma-coherent;
573 intc: interrupt-controller@17200000 {
574 compatible = "arm,gic-v3";
575 #interrupt-cells = <3>;
576 interrupt-controller;
577 #redistributor-regions = <1>;
578 redistributor-stride = <0x0 0x20000>;
585 compatible = "arm,armv7-timer-mem";
587 #address-cells = <1>;
588 #size-cells = <1>;
594 frame-number = <0>;
601 frame-number = <1>;
608 frame-number = <2>;
615 frame-number = <3>;
622 frame-number = <4>;
629 frame-number = <5>;
636 frame-number = <6>;
644 compatible = "qcom,rpmh-rsc";
648 reg-names = "drv-0", "drv-1", "drv-2";
653 power-domains = <&CLUSTER_PD>;
654 qcom,tcs-offset = <0xd00>;
655 qcom,drv-id = <2>;
656 qcom,tcs-config = <ACTIVE_TCS 3>,
661 apps_bcm_voter: bcm-voter {
662 compatible = "qcom,bcm-voter";
665 rpmhcc: clock-controller {
666 compatible = "qcom,sdx75-rpmh-clk";
668 clock-names = "xo";
669 #clock-cells = <1>;
672 rpmhpd: power-controller {
673 compatible = "qcom,sdx75-rpmhpd";
674 #power-domain-cells = <1>;
675 operating-points-v2 = <&rpmhpd_opp_table>;
677 rpmhpd_opp_table: opp-table {
678 compatible = "operating-points-v2";
680 rpmhpd_opp_ret: opp-16 {
681 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
684 rpmhpd_opp_min_svs: opp-48 {
685 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
688 rpmhpd_opp_low_svs: opp-64 {
689 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
692 rpmhpd_opp_svs: opp-128 {
693 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
696 rpmhpd_opp_svs_l1: opp-192 {
697 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
700 rpmhpd_opp_nom: opp-256 {
701 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
704 rpmhpd_opp_nom_l1: opp-320 {
705 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
708 rpmhpd_opp_nom_l2: opp-336 {
709 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
712 rpmhpd_opp_turbo: opp-384 {
713 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
716 rpmhpd_opp_turbo_l1: opp-416 {
717 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
724 compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
726 reg-names = "freq-domain0";
729 clock-names = "xo",
732 interrupt-names = "dcvsh-irq-0";
733 #freq-domain-cells = <1>;
734 #clock-cells = <1>;
739 compatible = "arm,armv8-timer";