Lines Matching +full:0 +full:xb220000
27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
45 clocks = <&cpufreq_hw 0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x100>;
71 clocks = <&cpufreq_hw 0>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
91 reg = <0x0 0x200>;
92 clocks = <&cpufreq_hw 0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
112 reg = <0x0 0x300>;
113 clocks = <&cpufreq_hw 0>;
117 qcom,freq-domain = <&cpufreq_hw 0>;
153 CPU_OFF: cpu-sleep-0 {
158 arm,psci-suspend-param = <0x40000003>;
167 arm,psci-suspend-param = <0x40000004>;
174 CLUSTER_SLEEP_0: cluster-sleep-0 {
176 arm,psci-suspend-param = <0x41000044>;
184 arm,psci-suspend-param = <0x41001344>;
192 arm,psci-suspend-param = <0x4100b344>;
208 reg = <0x0 0x80000000 0x0 0x0>;
221 #power-domain-cells = <0>;
227 #power-domain-cells = <0>;
233 #power-domain-cells = <0>;
239 #power-domain-cells = <0>;
245 #power-domain-cells = <0>;
256 reg = <0x0 0x80000000 0x0 0x800000>;
261 reg = <0x0 0x80800000 0x0 0x200000>;
266 reg = <0x0 0x81380000 0x0 0x80000>;
271 reg = <0x0 0x814e0000 0x0 0x2a0000>;
276 reg = <0x0 0x81780000 0x0 0xa00000>;
281 reg = <0x0 0x87a00000 0x0 0x1c0000>;
286 reg = <0x0 0x87c00000 0x0 0x100000>;
291 reg = <0x0 0x87d00000 0x0 0x40000>;
296 reg = <0x0 0x87d40000 0x0 0x40000>;
301 reg = <0x0 0x87d80000 0x0 0x10000>;
306 reg = <0x0 0x87e00000 0x0 0x20000>;
311 reg = <0x0 0x87e20000 0x0 0xc0000>;
317 reg = <0x0 0x87ee0000 0x0 0x20000>;
322 reg = <0x0 0x87f00000 0x0 0x20000>;
327 reg = <0x0 0x87f20000 0x0 0x10000>;
332 reg = <0x0 0x87f30000 0x0 0x1000>;
337 reg = <0x0 0x87f31000 0x0 0x40000>;
342 reg = <0x0 0x87f71000 0x0 0x4000>;
347 reg = <0x0 0x87f75000 0x0 0x10000>;
352 reg = <0x0 0x88800000 0x0 0x300000>;
358 reg = <0x0 0x88b00000 0x0 0x400000>;
363 reg = <0x0 0x88f00000 0x0 0x5080000>;
368 reg = <0x0 0x8df80000 0x0 0x80000>;
373 reg = <0x0 0x8e000000 0x0 0xf400000>;
378 reg = <0x0 0xbdb00000 0x0 0x2000000>;
383 reg = <0x0 0xbfb00000 0x0 0x100000>;
388 reg = <0x0 0xbfc00000 0x0 0x400000>;
403 ranges = <0 0 0 0 0x10 0>;
404 dma-ranges = <0 0 0 0 0x10 0>;
408 reg = <0x0 0x0080000 0x0 0x1f7400>;
411 <0>,
412 <0>,
413 <0>,
414 <0>,
415 <0>,
416 <0>,
417 <0>,
418 <0>,
419 <0>,
420 <0>,
421 <0>,
422 <0>,
423 <0>;
431 reg = <0x0 0x009c0000 0x0 0x2000>;
436 iommus = <&apps_smmu 0xe3 0x0>;
444 reg = <0x0 0x00984000 0x0 0x4000>;
448 pinctrl-0 = <&qupv3_se1_2uart_active>;
458 reg = <0x0 0x01f40000 0x0 0x40000>;
464 reg = <0x0 0xb220000 0x0 0x30000>,
465 <0x0 0x174000f0 0x0 0x64>;
466 qcom,pdc-ranges = <0 147 52>,
476 reg = <0x0 0x0c400000 0x0 0x3000>,
477 <0x0 0x0c500000 0x0 0x400000>,
478 <0x0 0x0c440000 0x0 0x80000>,
479 <0x0 0x0c4c0000 0x0 0x10000>,
480 <0x0 0x0c42d000 0x0 0x4000>;
488 qcom,ee = <0>;
489 qcom,channel = <0>;
490 qcom,bus-id = <0>;
492 #size-cells = <0>;
499 reg = <0x0 0x0f000000 0x0 0x400000>;
503 gpio-ranges = <&tlmm 0 0 133>;
534 reg = <0x0 0x15000000 0x0 0x40000>;
578 redistributor-stride = <0x0 0x20000>;
579 reg = <0x0 0x17200000 0x0 0x10000>,
580 <0x0 0x17260000 0x0 0x80000>;
586 reg = <0x0 0x17420000 0x0 0x1000>;
589 ranges = <0 0 0 0x20000000>;
592 reg = <0x17421000 0x1000>,
593 <0x17422000 0x1000>;
594 frame-number = <0>;
600 reg = <0x17423000 0x1000>;
607 reg = <0x17425000 0x1000>;
614 reg = <0x17427000 0x1000>;
621 reg = <0x17429000 0x1000>;
628 reg = <0x1742b000 0x1000>;
635 reg = <0x1742d000 0x1000>;
645 reg = <0x0 0x17a00000 0x0 0x10000>,
646 <0x0 0x17a10000 0x0 0x10000>,
647 <0x0 0x17a20000 0x0 0x10000>;
648 reg-names = "drv-0", "drv-1", "drv-2";
654 qcom,tcs-offset = <0xd00>;
659 <CONTROL_TCS 0>;
725 reg = <0x0 0x17d91000 0x0 0x1000>;
732 interrupt-names = "dcvsh-irq-0";