Lines Matching +full:rpm +full:- +full:msg +full:- +full:ram
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/interconnect/qcom,sdm660.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/qcom,apr.h>
18 interrupt-parent = <&intc>;
20 #address-cells = <2>;
21 #size-cells = <2>;
31 xo_board: xo-board {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <19200000>;
35 clock-output-names = "xo_board";
38 sleep_clk: sleep-clk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <32764>;
42 clock-output-names = "sleep_clk";
47 #address-cells = <2>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
55 cpu-idle-states = <&PERF_CPU_SLEEP_0
60 capacity-dmips-mhz = <1126>;
61 #cooling-cells = <2>;
62 next-level-cache = <&L2_1>;
63 L2_1: l2-cache {
65 cache-level = <2>;
66 cache-unified;
72 compatible = "arm,cortex-a53";
74 enable-method = "psci";
75 cpu-idle-states = <&PERF_CPU_SLEEP_0
80 capacity-dmips-mhz = <1126>;
81 #cooling-cells = <2>;
82 next-level-cache = <&L2_1>;
87 compatible = "arm,cortex-a53";
89 enable-method = "psci";
90 cpu-idle-states = <&PERF_CPU_SLEEP_0
95 capacity-dmips-mhz = <1126>;
96 #cooling-cells = <2>;
97 next-level-cache = <&L2_1>;
102 compatible = "arm,cortex-a53";
104 enable-method = "psci";
105 cpu-idle-states = <&PERF_CPU_SLEEP_0
110 capacity-dmips-mhz = <1126>;
111 #cooling-cells = <2>;
112 next-level-cache = <&L2_1>;
117 compatible = "arm,cortex-a53";
119 enable-method = "psci";
120 cpu-idle-states = <&PWR_CPU_SLEEP_0
125 capacity-dmips-mhz = <1024>;
126 #cooling-cells = <2>;
127 next-level-cache = <&L2_0>;
128 L2_0: l2-cache {
130 cache-level = <2>;
131 cache-unified;
137 compatible = "arm,cortex-a53";
139 enable-method = "psci";
140 cpu-idle-states = <&PWR_CPU_SLEEP_0
145 capacity-dmips-mhz = <1024>;
146 #cooling-cells = <2>;
147 next-level-cache = <&L2_0>;
152 compatible = "arm,cortex-a53";
154 enable-method = "psci";
155 cpu-idle-states = <&PWR_CPU_SLEEP_0
160 capacity-dmips-mhz = <1024>;
161 #cooling-cells = <2>;
162 next-level-cache = <&L2_0>;
167 compatible = "arm,cortex-a53";
169 enable-method = "psci";
170 cpu-idle-states = <&PWR_CPU_SLEEP_0
175 capacity-dmips-mhz = <1024>;
176 #cooling-cells = <2>;
177 next-level-cache = <&L2_0>;
180 cpu-map {
218 idle-states {
219 entry-method = "psci";
221 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
222 compatible = "arm,idle-state";
223 idle-state-name = "pwr-retention";
224 arm,psci-suspend-param = <0x40000002>;
225 entry-latency-us = <338>;
226 exit-latency-us = <423>;
227 min-residency-us = <200>;
230 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
231 compatible = "arm,idle-state";
232 idle-state-name = "pwr-power-collapse";
233 arm,psci-suspend-param = <0x40000003>;
234 entry-latency-us = <515>;
235 exit-latency-us = <1821>;
236 min-residency-us = <1000>;
237 local-timer-stop;
240 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
241 compatible = "arm,idle-state";
242 idle-state-name = "perf-retention";
243 arm,psci-suspend-param = <0x40000002>;
244 entry-latency-us = <154>;
245 exit-latency-us = <87>;
246 min-residency-us = <200>;
249 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
250 compatible = "arm,idle-state";
251 idle-state-name = "perf-power-collapse";
252 arm,psci-suspend-param = <0x40000003>;
253 entry-latency-us = <262>;
254 exit-latency-us = <301>;
255 min-residency-us = <1000>;
256 local-timer-stop;
259 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
260 compatible = "arm,idle-state";
261 idle-state-name = "pwr-cluster-dynamic-retention";
262 arm,psci-suspend-param = <0x400000F2>;
263 entry-latency-us = <284>;
264 exit-latency-us = <384>;
265 min-residency-us = <9987>;
266 local-timer-stop;
269 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
270 compatible = "arm,idle-state";
271 idle-state-name = "pwr-cluster-retention";
272 arm,psci-suspend-param = <0x400000F3>;
273 entry-latency-us = <338>;
274 exit-latency-us = <423>;
275 min-residency-us = <9987>;
276 local-timer-stop;
279 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
280 compatible = "arm,idle-state";
281 idle-state-name = "pwr-cluster-retention";
282 arm,psci-suspend-param = <0x400000F4>;
283 entry-latency-us = <515>;
284 exit-latency-us = <1821>;
285 min-residency-us = <9987>;
286 local-timer-stop;
289 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
290 compatible = "arm,idle-state";
291 idle-state-name = "perf-cluster-dynamic-retention";
292 arm,psci-suspend-param = <0x400000F2>;
293 entry-latency-us = <272>;
294 exit-latency-us = <329>;
295 min-residency-us = <9987>;
296 local-timer-stop;
299 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
300 compatible = "arm,idle-state";
301 idle-state-name = "perf-cluster-retention";
302 arm,psci-suspend-param = <0x400000F3>;
303 entry-latency-us = <332>;
304 exit-latency-us = <368>;
305 min-residency-us = <9987>;
306 local-timer-stop;
309 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
310 compatible = "arm,idle-state";
311 idle-state-name = "perf-cluster-retention";
312 arm,psci-suspend-param = <0x400000F4>;
313 entry-latency-us = <545>;
314 exit-latency-us = <1609>;
315 min-residency-us = <9987>;
316 local-timer-stop;
323 compatible = "qcom,scm-msm8998", "qcom,scm";
333 dsi_opp_table: opp-table-dsi {
334 compatible = "operating-points-v2";
336 opp-131250000 {
337 opp-hz = /bits/ 64 <131250000>;
338 required-opps = <&rpmpd_opp_svs>;
341 opp-210000000 {
342 opp-hz = /bits/ 64 <210000000>;
343 required-opps = <&rpmpd_opp_svs_plus>;
346 opp-262500000 {
347 opp-hz = /bits/ 64 <262500000>;
348 required-opps = <&rpmpd_opp_nom>;
353 compatible = "arm,armv8-pmuv3";
358 compatible = "arm,psci-1.0";
362 rpm: remoteproc { label
363 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc";
365 glink-edge {
366 compatible = "qcom,glink-rpm";
369 qcom,rpm-msg-ram = <&rpm_msg_ram>;
372 rpm_requests: rpm-requests {
373 compatible = "qcom,rpm-sdm660";
374 qcom,glink-channels = "rpm_requests";
376 rpmcc: clock-controller {
377 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
378 #clock-cells = <1>;
381 rpmpd: power-controller {
382 compatible = "qcom,sdm660-rpmpd";
383 #power-domain-cells = <1>;
384 operating-points-v2 = <&rpmpd_opp_table>;
386 rpmpd_opp_table: opp-table {
387 compatible = "operating-points-v2";
390 opp-level = <RPM_SMD_LEVEL_RETENTION>;
394 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
398 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
402 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
406 opp-level = <RPM_SMD_LEVEL_SVS>;
410 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
414 opp-level = <RPM_SMD_LEVEL_NOM>;
418 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
422 opp-level = <RPM_SMD_LEVEL_TURBO>;
430 reserved-memory {
431 #address-cells = <2>;
432 #size-cells = <2>;
435 wlan_msa_guard: wlan-msa-guard@85600000 {
437 no-map;
440 wlan_msa_mem: wlan-msa-mem@85700000 {
442 no-map;
445 qhee_code: qhee-code@85800000 {
447 no-map;
451 compatible = "qcom,rmtfs-mem";
453 no-map;
455 qcom,client-id = <1>;
459 smem_region: smem-mem@86000000 {
461 no-map;
466 no-map;
471 no-map;
476 no-map;
481 no-map;
486 no-map;
491 no-map;
494 adsp_mem: adsp-region@f6000000 {
496 no-map;
499 qseecom_mem: qseecom-region@f6800000 {
501 no-map;
505 compatible = "shared-dma-pool";
507 no-map;
513 memory-region = <&smem_region>;
517 smp2p-adsp {
522 qcom,local-pid = <0>;
523 qcom,remote-pid = <2>;
525 adsp_smp2p_out: master-kernel {
526 qcom,entry-name = "master-kernel";
527 #qcom,smem-state-cells = <1>;
530 adsp_smp2p_in: slave-kernel {
531 qcom,entry-name = "slave-kernel";
532 interrupt-controller;
533 #interrupt-cells = <2>;
537 smp2p-mpss {
542 qcom,local-pid = <0>;
543 qcom,remote-pid = <1>;
545 modem_smp2p_out: master-kernel {
546 qcom,entry-name = "master-kernel";
547 #qcom,smem-state-cells = <1>;
550 modem_smp2p_in: slave-kernel {
551 qcom,entry-name = "slave-kernel";
552 interrupt-controller;
553 #interrupt-cells = <2>;
558 #address-cells = <1>;
559 #size-cells = <1>;
561 compatible = "simple-bus";
563 gcc: clock-controller@100000 {
564 compatible = "qcom,gcc-sdm630";
565 #clock-cells = <1>;
566 #reset-cells = <1>;
567 #power-domain-cells = <1>;
570 clock-names = "xo", "sleep_clk";
576 compatible = "qcom,rpm-msg-ram";
581 compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
583 #address-cells = <1>;
584 #size-cells = <1>;
586 qusb2_hstx_trim: hstx-trim@240 {
591 gpu_speed_bin: gpu-speed-bin@41a0 {
598 compatible = "qcom,prng-ee";
601 clock-names = "core";
605 compatible = "qcom,sdm660-bimc";
607 #interconnect-cells = <1>;
608 clock-names = "bus", "bus_a";
619 compatible = "qcom,sdm660-cnoc";
621 #interconnect-cells = <1>;
622 clock-names = "bus", "bus_a";
628 compatible = "qcom,sdm660-snoc";
630 #interconnect-cells = <1>;
631 clock-names = "bus", "bus_a";
637 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
640 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
641 assigned-clock-rates = <1000>;
643 clock-names = "bus";
644 #global-interrupts = <2>;
645 #iommu-cells = <1>;
685 compatible = "qcom,sdm660-a2noc";
687 #interconnect-cells = <1>;
688 clock-names = "bus",
705 compatible = "qcom,sdm660-mnoc";
707 #interconnect-cells = <1>;
708 clock-names = "bus", "bus_a", "iface";
714 tsens: thermal-sensor@10ae000 {
715 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
721 interrupt-names = "uplow", "critical";
722 #thermal-sensor-cells = <1>;
726 compatible = "qcom,tcsr-mutex";
728 #hwlock-cells = <1>;
732 compatible = "qcom,sdm630-tcsr", "syscon";
737 compatible = "qcom,sdm630-pinctrl";
741 reg-names = "south", "center", "north";
743 gpio-controller;
744 gpio-ranges = <&tlmm 0 0 114>;
745 #gpio-cells = <2>;
746 interrupt-controller;
747 #interrupt-cells = <2>;
749 blsp1_uart1_default: blsp1-uart1-default-state {
752 drive-strength = <2>;
753 bias-disable;
756 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
759 drive-strength = <2>;
760 bias-disable;
763 blsp1_uart2_default: blsp1-uart2-default-state {
766 drive-strength = <2>;
767 bias-disable;
770 blsp2_uart1_default: blsp2-uart1-active-state {
771 tx-rts-pins {
774 drive-strength = <2>;
775 bias-disable;
778 rx-pins {
785 drive-strength = <2>;
786 bias-pull-up;
789 cts-pins {
793 drive-strength = <2>;
794 bias-pull-down;
798 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
799 tx-pins {
802 drive-strength = <2>;
803 bias-pull-up;
806 rx-cts-rts-pins {
809 drive-strength = <2>;
810 bias-disable;
814 i2c1_default: i2c1-default-state {
817 drive-strength = <2>;
818 bias-disable;
821 i2c1_sleep: i2c1-sleep-state {
824 drive-strength = <2>;
825 bias-pull-up;
828 i2c2_default: i2c2-default-state {
831 drive-strength = <2>;
832 bias-disable;
835 i2c2_sleep: i2c2-sleep-state {
838 drive-strength = <2>;
839 bias-pull-up;
842 i2c3_default: i2c3-default-state {
845 drive-strength = <2>;
846 bias-disable;
849 i2c3_sleep: i2c3-sleep-state {
852 drive-strength = <2>;
853 bias-pull-up;
856 i2c4_default: i2c4-default-state {
859 drive-strength = <2>;
860 bias-disable;
863 i2c4_sleep: i2c4-sleep-state {
866 drive-strength = <2>;
867 bias-pull-up;
870 i2c5_default: i2c5-default-state {
873 drive-strength = <2>;
874 bias-disable;
877 i2c5_sleep: i2c5-sleep-state {
880 drive-strength = <2>;
881 bias-pull-up;
884 i2c6_default: i2c6-default-state {
887 drive-strength = <2>;
888 bias-disable;
891 i2c6_sleep: i2c6-sleep-state {
894 drive-strength = <2>;
895 bias-pull-up;
898 i2c7_default: i2c7-default-state {
901 drive-strength = <2>;
902 bias-disable;
905 i2c7_sleep: i2c7-sleep-state {
908 drive-strength = <2>;
909 bias-pull-up;
912 i2c8_default: i2c8-default-state {
915 drive-strength = <2>;
916 bias-disable;
919 i2c8_sleep: i2c8-sleep-state {
922 drive-strength = <2>;
923 bias-pull-up;
926 cci0_default: cci0-default-state {
929 bias-pull-up;
930 drive-strength = <2>;
933 cci1_default: cci1-default-state {
936 bias-pull-up;
937 drive-strength = <2>;
940 sdc1_state_on: sdc1-on-state {
941 clk-pins {
943 bias-disable;
944 drive-strength = <16>;
947 cmd-pins {
949 bias-pull-up;
950 drive-strength = <10>;
953 data-pins {
955 bias-pull-up;
956 drive-strength = <10>;
959 rclk-pins {
961 bias-pull-down;
965 sdc1_state_off: sdc1-off-state {
966 clk-pins {
968 bias-disable;
969 drive-strength = <2>;
972 cmd-pins {
974 bias-pull-up;
975 drive-strength = <2>;
978 data-pins {
980 bias-pull-up;
981 drive-strength = <2>;
984 rclk-pins {
986 bias-pull-down;
990 sdc2_state_on: sdc2-on-state {
991 clk-pins {
993 bias-disable;
994 drive-strength = <16>;
997 cmd-pins {
999 bias-pull-up;
1000 drive-strength = <10>;
1003 data-pins {
1005 bias-pull-up;
1006 drive-strength = <10>;
1010 sdc2_state_off: sdc2-off-state {
1011 clk-pins {
1013 bias-disable;
1014 drive-strength = <2>;
1017 cmd-pins {
1019 bias-pull-up;
1020 drive-strength = <2>;
1023 data-pins {
1025 bias-pull-up;
1026 drive-strength = <2>;
1032 compatible = "qcom,adreno-508.0", "qcom,adreno";
1035 reg-names = "kgsl_3d0_reg_memory";
1046 clock-names = "iface",
1053 power-domains = <&rpmpd SDM660_VDDMX>;
1056 nvmem-cells = <&gpu_speed_bin>;
1057 nvmem-cell-names = "speed_bin";
1060 interconnect-names = "gfx-mem";
1062 operating-points-v2 = <&gpu_sdm630_opp_table>;
1066 gpu_sdm630_opp_table: opp-table {
1067 compatible = "operating-points-v2";
1068 opp-775000000 {
1069 opp-hz = /bits/ 64 <775000000>;
1070 opp-level = <RPM_SMD_LEVEL_TURBO>;
1071 opp-peak-kBps = <5412000>;
1072 opp-supported-hw = <0xa2>;
1074 opp-647000000 {
1075 opp-hz = /bits/ 64 <647000000>;
1076 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1077 opp-peak-kBps = <4068000>;
1078 opp-supported-hw = <0xff>;
1080 opp-588000000 {
1081 opp-hz = /bits/ 64 <588000000>;
1082 opp-level = <RPM_SMD_LEVEL_NOM>;
1083 opp-peak-kBps = <3072000>;
1084 opp-supported-hw = <0xff>;
1086 opp-465000000 {
1087 opp-hz = /bits/ 64 <465000000>;
1088 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1089 opp-peak-kBps = <2724000>;
1090 opp-supported-hw = <0xff>;
1092 opp-370000000 {
1093 opp-hz = /bits/ 64 <370000000>;
1094 opp-level = <RPM_SMD_LEVEL_SVS>;
1095 opp-peak-kBps = <2188000>;
1096 opp-supported-hw = <0xff>;
1098 opp-240000000 {
1099 opp-hz = /bits/ 64 <240000000>;
1100 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1101 opp-peak-kBps = <1648000>;
1102 opp-supported-hw = <0xff>;
1104 opp-160000000 {
1105 opp-hz = /bits/ 64 <160000000>;
1106 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1107 opp-peak-kBps = <1200000>;
1108 opp-supported-hw = <0xff>;
1114 compatible = "qcom,sdm630-smmu-v2",
1115 "qcom,adreno-smmu", "qcom,smmu-v2";
1123 * RPM Power Domain in the Adreno driver.
1125 power-domains = <&gpucc GPU_GX_GDSC>;
1129 clock-names = "iface", "mem", "mem_iface";
1130 #global-interrupts = <2>;
1131 #iommu-cells = <1>;
1149 gpucc: clock-controller@5065000 {
1150 compatible = "qcom,gpucc-sdm630";
1151 #clock-cells = <1>;
1152 #reset-cells = <1>;
1153 #power-domain-cells = <1>;
1159 clock-names = "xo",
1166 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1168 #iommu-cells = <1>;
1170 #global-interrupts = <2>;
1197 compatible = "qcom,rpm-stats";
1202 compatible = "qcom,spmi-pmic-arb";
1208 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1209 interrupt-names = "periph_irq";
1213 #address-cells = <2>;
1214 #size-cells = <0>;
1215 interrupt-controller;
1216 #interrupt-cells = <4>;
1220 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1223 #address-cells = <1>;
1224 #size-cells = <1>;
1233 clock-names = "cfg_noc",
1240 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1243 assigned-clock-rates = <19200000>, <120000000>,
1248 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1250 power-domains = <&gcc USB_30_GDSC>;
1251 qcom,select-utmi-as-pipe-clk;
1261 snps,parkmode-disable-ss-quirk;
1267 maximum-speed = "high-speed";
1269 phy-names = "usb2-phy";
1270 snps,hird-threshold = /bits/ 8 <0>;
1275 compatible = "qcom,sdm660-qusb2-phy";
1277 #phy-cells = <0>;
1281 clock-names = "cfg_ahb", "ref";
1284 nvmem-cells = <&qusb2_hstx_trim>;
1289 compatible = "qcom,sdm660-qusb2-phy";
1291 #phy-cells = <0>;
1295 clock-names = "cfg_ahb", "ref";
1298 nvmem-cells = <&qusb2_hstx_trim>;
1303 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1305 reg-names = "hc";
1309 interrupt-names = "hc_irq", "pwr_irq";
1311 bus-width = <4>;
1316 clock-names = "iface", "core", "xo";
1321 interconnect-names = "sdhc-ddr","cpu-sdhc";
1322 operating-points-v2 = <&sdhc2_opp_table>;
1324 pinctrl-names = "default", "sleep";
1325 pinctrl-0 = <&sdc2_state_on>;
1326 pinctrl-1 = <&sdc2_state_off>;
1327 power-domains = <&rpmpd SDM660_VDDCX>;
1331 sdhc2_opp_table: opp-table {
1332 compatible = "operating-points-v2";
1334 opp-50000000 {
1335 opp-hz = /bits/ 64 <50000000>;
1336 required-opps = <&rpmpd_opp_low_svs>;
1337 opp-peak-kBps = <200000 140000>;
1338 opp-avg-kBps = <130718 133320>;
1340 opp-100000000 {
1341 opp-hz = /bits/ 64 <100000000>;
1342 required-opps = <&rpmpd_opp_svs>;
1343 opp-peak-kBps = <250000 160000>;
1344 opp-avg-kBps = <196078 150000>;
1346 opp-200000000 {
1347 opp-hz = /bits/ 64 <200000000>;
1348 required-opps = <&rpmpd_opp_nom>;
1349 opp-peak-kBps = <4096000 4096000>;
1350 opp-avg-kBps = <1338562 1338562>;
1356 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1360 reg-names = "hc", "cqhci", "ice";
1364 interrupt-names = "hc_irq", "pwr_irq";
1370 clock-names = "iface", "core", "xo", "ice";
1374 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1375 operating-points-v2 = <&sdhc1_opp_table>;
1376 pinctrl-names = "default", "sleep";
1377 pinctrl-0 = <&sdc1_state_on>;
1378 pinctrl-1 = <&sdc1_state_off>;
1379 power-domains = <&rpmpd SDM660_VDDCX>;
1381 bus-width = <8>;
1382 non-removable;
1386 sdhc1_opp_table: opp-table {
1387 compatible = "operating-points-v2";
1389 opp-50000000 {
1390 opp-hz = /bits/ 64 <50000000>;
1391 required-opps = <&rpmpd_opp_low_svs>;
1392 opp-peak-kBps = <200000 140000>;
1393 opp-avg-kBps = <130718 133320>;
1395 opp-100000000 {
1396 opp-hz = /bits/ 64 <100000000>;
1397 required-opps = <&rpmpd_opp_svs>;
1398 opp-peak-kBps = <250000 160000>;
1399 opp-avg-kBps = <196078 150000>;
1401 opp-384000000 {
1402 opp-hz = /bits/ 64 <384000000>;
1403 required-opps = <&rpmpd_opp_nom>;
1404 opp-peak-kBps = <4096000 4096000>;
1405 opp-avg-kBps = <1338562 1338562>;
1411 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1414 #address-cells = <1>;
1415 #size-cells = <1>;
1422 clock-names = "cfg_noc", "core",
1425 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1427 assigned-clock-rates = <19200000>, <60000000>;
1430 interrupt-names = "hs_phy_irq";
1432 qcom,select-utmi-as-pipe-clk;
1443 /* This is the HS-only host */
1444 maximum-speed = "high-speed";
1446 phy-names = "usb2-phy";
1447 snps,hird-threshold = /bits/ 8 <0>;
1451 mmcc: clock-controller@c8c0000 {
1452 compatible = "qcom,mmcc-sdm630";
1454 #clock-cells = <1>;
1455 #reset-cells = <1>;
1456 #power-domain-cells = <1>;
1457 clock-names = "xo",
1479 mdss: display-subsystem@c900000 {
1483 reg-names = "mdss_phys", "vbif_phys";
1485 power-domains = <&mmcc MDSS_GDSC>;
1491 clock-names = "iface",
1498 interrupt-controller;
1499 #interrupt-cells = <1>;
1501 #address-cells = <1>;
1502 #size-cells = <1>;
1506 mdp: display-controller@c901000 {
1507 compatible = "qcom,sdm630-mdp5", "qcom,mdp5";
1509 reg-names = "mdp_phys";
1511 interrupt-parent = <&mdss>;
1514 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1516 assigned-clock-rates = <300000000>,
1522 clock-names = "iface",
1530 interconnect-names = "mdp0-mem",
1531 "mdp1-mem",
1532 "rotator-mem";
1534 operating-points-v2 = <&mdp_opp_table>;
1535 power-domains = <&rpmpd SDM660_VDDCX>;
1538 #address-cells = <1>;
1539 #size-cells = <0>;
1544 remote-endpoint = <&mdss_dsi0_in>;
1549 mdp_opp_table: opp-table {
1550 compatible = "operating-points-v2";
1552 opp-150000000 {
1553 opp-hz = /bits/ 64 <150000000>;
1554 opp-peak-kBps = <320000 320000 76800>;
1555 required-opps = <&rpmpd_opp_low_svs>;
1557 opp-275000000 {
1558 opp-hz = /bits/ 64 <275000000>;
1559 opp-peak-kBps = <6400000 6400000 160000>;
1560 required-opps = <&rpmpd_opp_svs>;
1562 opp-300000000 {
1563 opp-hz = /bits/ 64 <300000000>;
1564 opp-peak-kBps = <6400000 6400000 190000>;
1565 required-opps = <&rpmpd_opp_svs_plus>;
1567 opp-330000000 {
1568 opp-hz = /bits/ 64 <330000000>;
1569 opp-peak-kBps = <6400000 6400000 240000>;
1570 required-opps = <&rpmpd_opp_nom>;
1572 opp-412500000 {
1573 opp-hz = /bits/ 64 <412500000>;
1574 opp-peak-kBps = <6400000 6400000 320000>;
1575 required-opps = <&rpmpd_opp_turbo>;
1581 compatible = "qcom,sdm660-dsi-ctrl",
1582 "qcom,mdss-dsi-ctrl";
1584 reg-names = "dsi_ctrl";
1586 operating-points-v2 = <&dsi_opp_table>;
1587 power-domains = <&rpmpd SDM660_VDDCX>;
1589 interrupt-parent = <&mdss>;
1592 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1594 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1606 clock-names = "mdp_core",
1621 #address-cells = <1>;
1622 #size-cells = <0>;
1627 remote-endpoint = <&mdp5_intf1_out>;
1640 compatible = "qcom,dsi-phy-14nm-660";
1644 reg-names = "dsi_phy",
1648 #clock-cells = <1>;
1649 #phy-cells = <0>;
1652 clock-names = "iface", "ref";
1657 blsp1_dma: dma-controller@c144000 {
1658 compatible = "qcom,bam-v1.7.0";
1662 clock-names = "bam_clk";
1663 #dma-cells = <1>;
1665 qcom,controlled-remotely;
1666 num-channels = <18>;
1667 qcom,num-ees = <4>;
1671 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1676 clock-names = "core", "iface";
1678 dma-names = "tx", "rx";
1679 pinctrl-names = "default", "sleep";
1680 pinctrl-0 = <&blsp1_uart1_default>;
1681 pinctrl-1 = <&blsp1_uart1_sleep>;
1686 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1691 clock-names = "core", "iface";
1693 dma-names = "tx", "rx";
1694 pinctrl-names = "default";
1695 pinctrl-0 = <&blsp1_uart2_default>;
1700 compatible = "qcom,i2c-qup-v2.2.1";
1706 clock-names = "core", "iface";
1707 clock-frequency = <400000>;
1709 dma-names = "tx", "rx";
1711 pinctrl-names = "default", "sleep";
1712 pinctrl-0 = <&i2c1_default>;
1713 pinctrl-1 = <&i2c1_sleep>;
1714 #address-cells = <1>;
1715 #size-cells = <0>;
1720 compatible = "qcom,i2c-qup-v2.2.1";
1726 clock-names = "core", "iface";
1727 clock-frequency = <400000>;
1729 dma-names = "tx", "rx";
1731 pinctrl-names = "default", "sleep";
1732 pinctrl-0 = <&i2c2_default>;
1733 pinctrl-1 = <&i2c2_sleep>;
1734 #address-cells = <1>;
1735 #size-cells = <0>;
1740 compatible = "qcom,i2c-qup-v2.2.1";
1746 clock-names = "core", "iface";
1747 clock-frequency = <400000>;
1749 dma-names = "tx", "rx";
1751 pinctrl-names = "default", "sleep";
1752 pinctrl-0 = <&i2c3_default>;
1753 pinctrl-1 = <&i2c3_sleep>;
1754 #address-cells = <1>;
1755 #size-cells = <0>;
1760 compatible = "qcom,i2c-qup-v2.2.1";
1766 clock-names = "core", "iface";
1767 clock-frequency = <400000>;
1769 dma-names = "tx", "rx";
1771 pinctrl-names = "default", "sleep";
1772 pinctrl-0 = <&i2c4_default>;
1773 pinctrl-1 = <&i2c4_sleep>;
1774 #address-cells = <1>;
1775 #size-cells = <0>;
1779 blsp2_dma: dma-controller@c184000 {
1780 compatible = "qcom,bam-v1.7.0";
1784 clock-names = "bam_clk";
1785 #dma-cells = <1>;
1787 qcom,controlled-remotely;
1788 num-channels = <18>;
1789 qcom,num-ees = <4>;
1793 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1798 clock-names = "core", "iface";
1800 dma-names = "tx", "rx";
1801 pinctrl-names = "default", "sleep";
1802 pinctrl-0 = <&blsp2_uart1_default>;
1803 pinctrl-1 = <&blsp2_uart1_sleep>;
1808 compatible = "qcom,i2c-qup-v2.2.1";
1814 clock-names = "core", "iface";
1815 clock-frequency = <400000>;
1817 dma-names = "tx", "rx";
1819 pinctrl-names = "default", "sleep";
1820 pinctrl-0 = <&i2c5_default>;
1821 pinctrl-1 = <&i2c5_sleep>;
1822 #address-cells = <1>;
1823 #size-cells = <0>;
1828 compatible = "qcom,i2c-qup-v2.2.1";
1834 clock-names = "core", "iface";
1835 clock-frequency = <400000>;
1837 dma-names = "tx", "rx";
1839 pinctrl-names = "default", "sleep";
1840 pinctrl-0 = <&i2c6_default>;
1841 pinctrl-1 = <&i2c6_sleep>;
1842 #address-cells = <1>;
1843 #size-cells = <0>;
1848 compatible = "qcom,i2c-qup-v2.2.1";
1854 clock-names = "core", "iface";
1855 clock-frequency = <400000>;
1857 dma-names = "tx", "rx";
1859 pinctrl-names = "default", "sleep";
1860 pinctrl-0 = <&i2c7_default>;
1861 pinctrl-1 = <&i2c7_sleep>;
1862 #address-cells = <1>;
1863 #size-cells = <0>;
1868 compatible = "qcom,i2c-qup-v2.2.1";
1874 clock-names = "core", "iface";
1875 clock-frequency = <400000>;
1877 dma-names = "tx", "rx";
1879 pinctrl-names = "default", "sleep";
1880 pinctrl-0 = <&i2c8_default>;
1881 pinctrl-1 = <&i2c8_sleep>;
1882 #address-cells = <1>;
1883 #size-cells = <0>;
1888 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
1891 #address-cells = <1>;
1892 #size-cells = <1>;
1896 pil-reloc@94c {
1897 compatible = "qcom,pil-reloc-info";
1903 compatible = "qcom,sdm660-camss";
1918 reg-names = "csi_clk_mux",
1942 interrupt-names = "csid0",
1994 clock-names = "ahb",
2037 interconnect-names = "vfe-mem";
2042 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2047 #address-cells = <1>;
2048 #size-cells = <0>;
2053 compatible = "qcom,msm8996-cci";
2054 #address-cells = <1>;
2055 #size-cells = <0>;
2059 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2061 assigned-clock-rates = <80800000>, <37500000>;
2066 clock-names = "camss_top_ahb",
2071 pinctrl-names = "default";
2072 pinctrl-0 = <&cci0_default &cci1_default>;
2073 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2076 cci_i2c0: i2c-bus@0 {
2078 clock-frequency = <400000>;
2079 #address-cells = <1>;
2080 #size-cells = <0>;
2083 cci_i2c1: i2c-bus@1 {
2085 clock-frequency = <400000>;
2086 #address-cells = <1>;
2087 #size-cells = <0>;
2091 venus: video-codec@cc00000 {
2092 compatible = "qcom,sdm660-venus";
2098 clock-names = "core", "iface", "bus", "bus_throttle";
2101 interconnect-names = "cpu-cfg", "video-mem";
2123 memory-region = <&venus_region>;
2124 power-domains = <&mmcc VENUS_GDSC>;
2127 video-decoder {
2128 compatible = "venus-decoder";
2130 clock-names = "vcodec0_core";
2131 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2134 video-encoder {
2135 compatible = "venus-encoder";
2137 clock-names = "vcodec0_core";
2138 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2143 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2150 clock-names = "iface-mm", "iface-smmu",
2151 "bus-mm", "bus-smmu";
2152 #global-interrupts = <2>;
2153 #iommu-cells = <1>;
2188 compatible = "qcom,sdm660-adsp-pas";
2191 interrupts-extended =
2197 interrupt-names = "wdog", "fatal", "ready",
2198 "handover", "stop-ack";
2201 clock-names = "xo";
2203 memory-region = <&adsp_region>;
2204 power-domains = <&rpmpd SDM660_VDDCX>;
2205 power-domain-names = "cx";
2207 qcom,smem-states = <&adsp_smp2p_out 0>;
2208 qcom,smem-state-names = "stop";
2210 glink-edge {
2215 qcom,remote-pid = <2>;
2218 compatible = "qcom,apr-v2";
2219 qcom,glink-channels = "apr_audio_svc";
2221 #address-cells = <1>;
2222 #size-cells = <0>;
2233 compatible = "qcom,q6afe-dais";
2234 #address-cells = <1>;
2235 #size-cells = <0>;
2236 #sound-dai-cells = <1>;
2244 compatible = "qcom,q6asm-dais";
2245 #address-cells = <1>;
2246 #size-cells = <0>;
2247 #sound-dai-cells = <1>;
2256 compatible = "qcom,q6adm-routing";
2257 #sound-dai-cells = <0>;
2265 compatible = "qcom,sdm660-gnoc";
2267 #interconnect-cells = <1>;
2272 clock-names = "bus", "bus_a";
2277 compatible = "qcom,sdm660-apcs-hmss-global",
2278 "qcom,msm8994-apcs-kpss-global";
2281 #mbox-cells = <1>;
2285 #address-cells = <1>;
2286 #size-cells = <1>;
2288 compatible = "arm,armv7-timer-mem";
2290 clock-frequency = <19200000>;
2293 frame-number = <0>;
2301 frame-number = <1>;
2308 frame-number = <2>;
2315 frame-number = <3>;
2322 frame-number = <4>;
2329 frame-number = <5>;
2336 frame-number = <6>;
2343 intc: interrupt-controller@17a00000 {
2344 compatible = "arm,gic-v3";
2347 #interrupt-cells = <3>;
2348 #address-cells = <1>;
2349 #size-cells = <1>;
2351 interrupt-controller;
2352 #redistributor-regions = <1>;
2353 redistributor-stride = <0x0 0x20000>;
2361 thermal-zones {
2362 aoss-thermal {
2363 polling-delay-passive = <250>;
2364 polling-delay = <1000>;
2366 thermal-sensors = <&tsens 0>;
2369 aoss_alert0: trip-point0 {
2377 cpuss0-thermal {
2378 polling-delay-passive = <250>;
2379 polling-delay = <1000>;
2381 thermal-sensors = <&tsens 1>;
2384 cpuss0_alert0: trip-point0 {
2392 cpuss1-thermal {
2393 polling-delay-passive = <250>;
2394 polling-delay = <1000>;
2396 thermal-sensors = <&tsens 2>;
2399 cpuss1_alert0: trip-point0 {
2407 cpu0-thermal {
2408 polling-delay-passive = <250>;
2409 polling-delay = <1000>;
2411 thermal-sensors = <&tsens 3>;
2414 cpu0_alert0: trip-point0 {
2420 cpu0_crit: cpu-crit {
2428 cpu1-thermal {
2429 polling-delay-passive = <250>;
2430 polling-delay = <1000>;
2432 thermal-sensors = <&tsens 4>;
2435 cpu1_alert0: trip-point0 {
2441 cpu1_crit: cpu-crit {
2449 cpu2-thermal {
2450 polling-delay-passive = <250>;
2451 polling-delay = <1000>;
2453 thermal-sensors = <&tsens 5>;
2456 cpu2_alert0: trip-point0 {
2462 cpu2_crit: cpu-crit {
2470 cpu3-thermal {
2471 polling-delay-passive = <250>;
2472 polling-delay = <1000>;
2474 thermal-sensors = <&tsens 6>;
2477 cpu3_alert0: trip-point0 {
2483 cpu3_crit: cpu-crit {
2497 pwr-cluster-thermal {
2498 polling-delay-passive = <250>;
2499 polling-delay = <1000>;
2501 thermal-sensors = <&tsens 7>;
2504 pwr_cluster_alert0: trip-point0 {
2510 pwr_cluster_crit: cpu-crit {
2518 gpu-thermal {
2519 polling-delay-passive = <250>;
2520 polling-delay = <1000>;
2522 thermal-sensors = <&tsens 8>;
2525 gpu_alert0: trip-point0 {
2535 compatible = "arm,armv8-timer";