Lines Matching +full:opp +full:- +full:2
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
12 #include <dt-bindings/interconnect/qcom,osm-l3.h>
13 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/soc/qcom,gpr.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 #include <dt-bindings/sound/qcom,q6afe.h>
21 #include <dt-bindings/thermal/thermal.h>
24 interrupt-parent = <&intc>;
26 #address-cells = <2>;
27 #size-cells = <2>;
30 xo_board_clk: xo-board-clk {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32764>;
43 #address-cells = <2>;
44 #size-cells = <0>;
48 compatible = "arm,cortex-a78c";
51 enable-method = "psci";
52 capacity-dmips-mhz = <602>;
53 next-level-cache = <&L2_0>;
54 power-domains = <&CPU_PD0>;
55 power-domain-names = "psci";
56 qcom,freq-domain = <&cpufreq_hw 0>;
57 operating-points-v2 = <&cpu0_opp_table>;
59 #cooling-cells = <2>;
60 L2_0: l2-cache {
62 cache-level = <2>;
63 cache-unified;
64 next-level-cache = <&L3_0>;
65 L3_0: l3-cache {
67 cache-level = <3>;
68 cache-unified;
75 compatible = "arm,cortex-a78c";
78 enable-method = "psci";
79 capacity-dmips-mhz = <602>;
80 next-level-cache = <&L2_100>;
81 power-domains = <&CPU_PD1>;
82 power-domain-names = "psci";
83 qcom,freq-domain = <&cpufreq_hw 0>;
84 operating-points-v2 = <&cpu0_opp_table>;
86 #cooling-cells = <2>;
87 L2_100: l2-cache {
89 cache-level = <2>;
90 cache-unified;
91 next-level-cache = <&L3_0>;
97 compatible = "arm,cortex-a78c";
100 enable-method = "psci";
101 capacity-dmips-mhz = <602>;
102 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_PD2>;
104 power-domain-names = "psci";
105 qcom,freq-domain = <&cpufreq_hw 0>;
106 operating-points-v2 = <&cpu0_opp_table>;
108 #cooling-cells = <2>;
109 L2_200: l2-cache {
111 cache-level = <2>;
112 cache-unified;
113 next-level-cache = <&L3_0>;
119 compatible = "arm,cortex-a78c";
122 enable-method = "psci";
123 capacity-dmips-mhz = <602>;
124 next-level-cache = <&L2_300>;
125 power-domains = <&CPU_PD3>;
126 power-domain-names = "psci";
127 qcom,freq-domain = <&cpufreq_hw 0>;
128 operating-points-v2 = <&cpu0_opp_table>;
130 #cooling-cells = <2>;
131 L2_300: l2-cache {
133 cache-level = <2>;
134 cache-unified;
135 next-level-cache = <&L3_0>;
141 compatible = "arm,cortex-x1c";
144 enable-method = "psci";
145 capacity-dmips-mhz = <1024>;
146 next-level-cache = <&L2_400>;
147 power-domains = <&CPU_PD4>;
148 power-domain-names = "psci";
149 qcom,freq-domain = <&cpufreq_hw 1>;
150 operating-points-v2 = <&cpu4_opp_table>;
152 #cooling-cells = <2>;
153 L2_400: l2-cache {
155 cache-level = <2>;
156 cache-unified;
157 next-level-cache = <&L3_0>;
163 compatible = "arm,cortex-x1c";
166 enable-method = "psci";
167 capacity-dmips-mhz = <1024>;
168 next-level-cache = <&L2_500>;
169 power-domains = <&CPU_PD5>;
170 power-domain-names = "psci";
171 qcom,freq-domain = <&cpufreq_hw 1>;
172 operating-points-v2 = <&cpu4_opp_table>;
174 #cooling-cells = <2>;
175 L2_500: l2-cache {
177 cache-level = <2>;
178 cache-unified;
179 next-level-cache = <&L3_0>;
185 compatible = "arm,cortex-x1c";
188 enable-method = "psci";
189 capacity-dmips-mhz = <1024>;
190 next-level-cache = <&L2_600>;
191 power-domains = <&CPU_PD6>;
192 power-domain-names = "psci";
193 qcom,freq-domain = <&cpufreq_hw 1>;
194 operating-points-v2 = <&cpu4_opp_table>;
196 #cooling-cells = <2>;
197 L2_600: l2-cache {
199 cache-level = <2>;
200 cache-unified;
201 next-level-cache = <&L3_0>;
207 compatible = "arm,cortex-x1c";
210 enable-method = "psci";
211 capacity-dmips-mhz = <1024>;
212 next-level-cache = <&L2_700>;
213 power-domains = <&CPU_PD7>;
214 power-domain-names = "psci";
215 qcom,freq-domain = <&cpufreq_hw 1>;
216 operating-points-v2 = <&cpu4_opp_table>;
218 #cooling-cells = <2>;
219 L2_700: l2-cache {
221 cache-level = <2>;
222 cache-unified;
223 next-level-cache = <&L3_0>;
227 cpu-map {
263 idle-states {
264 entry-method = "psci";
266 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
267 compatible = "arm,idle-state";
268 idle-state-name = "little-rail-power-collapse";
269 arm,psci-suspend-param = <0x40000004>;
270 entry-latency-us = <355>;
271 exit-latency-us = <909>;
272 min-residency-us = <3934>;
273 local-timer-stop;
276 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
277 compatible = "arm,idle-state";
278 idle-state-name = "big-rail-power-collapse";
279 arm,psci-suspend-param = <0x40000004>;
280 entry-latency-us = <241>;
281 exit-latency-us = <1461>;
282 min-residency-us = <4488>;
283 local-timer-stop;
287 domain-idle-states {
288 CLUSTER_SLEEP_0: cluster-sleep-0 {
289 compatible = "domain-idle-state";
290 arm,psci-suspend-param = <0x4100c344>;
291 entry-latency-us = <3263>;
292 exit-latency-us = <6562>;
293 min-residency-us = <9987>;
300 compatible = "qcom,scm-sc8280xp", "qcom,scm";
305 aggre1_noc: interconnect-aggre1-noc {
306 compatible = "qcom,sc8280xp-aggre1-noc";
307 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_voter>;
311 aggre2_noc: interconnect-aggre2-noc {
312 compatible = "qcom,sc8280xp-aggre2-noc";
313 #interconnect-cells = <2>;
314 qcom,bcm-voters = <&apps_bcm_voter>;
317 clk_virt: interconnect-clk-virt {
318 compatible = "qcom,sc8280xp-clk-virt";
319 #interconnect-cells = <2>;
320 qcom,bcm-voters = <&apps_bcm_voter>;
323 config_noc: interconnect-config-noc {
324 compatible = "qcom,sc8280xp-config-noc";
325 #interconnect-cells = <2>;
326 qcom,bcm-voters = <&apps_bcm_voter>;
329 dc_noc: interconnect-dc-noc {
330 compatible = "qcom,sc8280xp-dc-noc";
331 #interconnect-cells = <2>;
332 qcom,bcm-voters = <&apps_bcm_voter>;
335 gem_noc: interconnect-gem-noc {
336 compatible = "qcom,sc8280xp-gem-noc";
337 #interconnect-cells = <2>;
338 qcom,bcm-voters = <&apps_bcm_voter>;
341 lpass_noc: interconnect-lpass-ag-noc {
342 compatible = "qcom,sc8280xp-lpass-ag-noc";
343 #interconnect-cells = <2>;
344 qcom,bcm-voters = <&apps_bcm_voter>;
347 mc_virt: interconnect-mc-virt {
348 compatible = "qcom,sc8280xp-mc-virt";
349 #interconnect-cells = <2>;
350 qcom,bcm-voters = <&apps_bcm_voter>;
353 mmss_noc: interconnect-mmss-noc {
354 compatible = "qcom,sc8280xp-mmss-noc";
355 #interconnect-cells = <2>;
356 qcom,bcm-voters = <&apps_bcm_voter>;
359 nspa_noc: interconnect-nspa-noc {
360 compatible = "qcom,sc8280xp-nspa-noc";
361 #interconnect-cells = <2>;
362 qcom,bcm-voters = <&apps_bcm_voter>;
365 nspb_noc: interconnect-nspb-noc {
366 compatible = "qcom,sc8280xp-nspb-noc";
367 #interconnect-cells = <2>;
368 qcom,bcm-voters = <&apps_bcm_voter>;
371 system_noc: interconnect-system-noc {
372 compatible = "qcom,sc8280xp-system-noc";
373 #interconnect-cells = <2>;
374 qcom,bcm-voters = <&apps_bcm_voter>;
383 cpu0_opp_table: opp-table-cpu0 {
384 compatible = "operating-points-v2";
385 opp-shared;
387 opp-300000000 {
388 opp-hz = /bits/ 64 <300000000>;
389 opp-peak-kBps = <(300000 * 32)>;
391 opp-403200000 {
392 opp-hz = /bits/ 64 <403200000>;
393 opp-peak-kBps = <(384000 * 32)>;
395 opp-499200000 {
396 opp-hz = /bits/ 64 <499200000>;
397 opp-peak-kBps = <(480000 * 32)>;
399 opp-595200000 {
400 opp-hz = /bits/ 64 <595200000>;
401 opp-peak-kBps = <(576000 * 32)>;
403 opp-691200000 {
404 opp-hz = /bits/ 64 <691200000>;
405 opp-peak-kBps = <(672000 * 32)>;
407 opp-806400000 {
408 opp-hz = /bits/ 64 <806400000>;
409 opp-peak-kBps = <(768000 * 32)>;
411 opp-902400000 {
412 opp-hz = /bits/ 64 <902400000>;
413 opp-peak-kBps = <(864000 * 32)>;
415 opp-1017600000 {
416 opp-hz = /bits/ 64 <1017600000>;
417 opp-peak-kBps = <(960000 * 32)>;
419 opp-1113600000 {
420 opp-hz = /bits/ 64 <1113600000>;
421 opp-peak-kBps = <(1075200 * 32)>;
423 opp-1209600000 {
424 opp-hz = /bits/ 64 <1209600000>;
425 opp-peak-kBps = <(1171200 * 32)>;
427 opp-1324800000 {
428 opp-hz = /bits/ 64 <1324800000>;
429 opp-peak-kBps = <(1267200 * 32)>;
431 opp-1440000000 {
432 opp-hz = /bits/ 64 <1440000000>;
433 opp-peak-kBps = <(1363200 * 32)>;
435 opp-1555200000 {
436 opp-hz = /bits/ 64 <1555200000>;
437 opp-peak-kBps = <(1536000 * 32)>;
439 opp-1670400000 {
440 opp-hz = /bits/ 64 <1670400000>;
441 opp-peak-kBps = <(1612800 * 32)>;
443 opp-1785600000 {
444 opp-hz = /bits/ 64 <1785600000>;
445 opp-peak-kBps = <(1689600 * 32)>;
447 opp-1881600000 {
448 opp-hz = /bits/ 64 <1881600000>;
449 opp-peak-kBps = <(1689600 * 32)>;
451 opp-1996800000 {
452 opp-hz = /bits/ 64 <1996800000>;
453 opp-peak-kBps = <(1689600 * 32)>;
455 opp-2112000000 {
456 opp-hz = /bits/ 64 <2112000000>;
457 opp-peak-kBps = <(1689600 * 32)>;
459 opp-2227200000 {
460 opp-hz = /bits/ 64 <2227200000>;
461 opp-peak-kBps = <(1689600 * 32)>;
463 opp-2342400000 {
464 opp-hz = /bits/ 64 <2342400000>;
465 opp-peak-kBps = <(1689600 * 32)>;
467 opp-2438400000 {
468 opp-hz = /bits/ 64 <2438400000>;
469 opp-peak-kBps = <(1689600 * 32)>;
473 cpu4_opp_table: opp-table-cpu4 {
474 compatible = "operating-points-v2";
475 opp-shared;
477 opp-825600000 {
478 opp-hz = /bits/ 64 <825600000>;
479 opp-peak-kBps = <(768000 * 32)>;
481 opp-940800000 {
482 opp-hz = /bits/ 64 <940800000>;
483 opp-peak-kBps = <(864000 * 32)>;
485 opp-1056000000 {
486 opp-hz = /bits/ 64 <1056000000>;
487 opp-peak-kBps = <(960000 * 32)>;
489 opp-1171200000 {
490 opp-hz = /bits/ 64 <1171200000>;
491 opp-peak-kBps = <(1171200 * 32)>;
493 opp-1286400000 {
494 opp-hz = /bits/ 64 <1286400000>;
495 opp-peak-kBps = <(1267200 * 32)>;
497 opp-1401600000 {
498 opp-hz = /bits/ 64 <1401600000>;
499 opp-peak-kBps = <(1363200 * 32)>;
501 opp-1516800000 {
502 opp-hz = /bits/ 64 <1516800000>;
503 opp-peak-kBps = <(1459200 * 32)>;
505 opp-1632000000 {
506 opp-hz = /bits/ 64 <1632000000>;
507 opp-peak-kBps = <(1612800 * 32)>;
509 opp-1747200000 {
510 opp-hz = /bits/ 64 <1747200000>;
511 opp-peak-kBps = <(1689600 * 32)>;
513 opp-1862400000 {
514 opp-hz = /bits/ 64 <1862400000>;
515 opp-peak-kBps = <(1689600 * 32)>;
517 opp-1977600000 {
518 opp-hz = /bits/ 64 <1977600000>;
519 opp-peak-kBps = <(1689600 * 32)>;
521 opp-2073600000 {
522 opp-hz = /bits/ 64 <2073600000>;
523 opp-peak-kBps = <(1689600 * 32)>;
525 opp-2169600000 {
526 opp-hz = /bits/ 64 <2169600000>;
527 opp-peak-kBps = <(1689600 * 32)>;
529 opp-2284800000 {
530 opp-hz = /bits/ 64 <2284800000>;
531 opp-peak-kBps = <(1689600 * 32)>;
533 opp-2400000000 {
534 opp-hz = /bits/ 64 <2400000000>;
535 opp-peak-kBps = <(1689600 * 32)>;
537 opp-2496000000 {
538 opp-hz = /bits/ 64 <2496000000>;
539 opp-peak-kBps = <(1689600 * 32)>;
541 opp-2592000000 {
542 opp-hz = /bits/ 64 <2592000000>;
543 opp-peak-kBps = <(1689600 * 32)>;
545 opp-2688000000 {
546 opp-hz = /bits/ 64 <2688000000>;
547 opp-peak-kBps = <(1689600 * 32)>;
549 opp-2803200000 {
550 opp-hz = /bits/ 64 <2803200000>;
551 opp-peak-kBps = <(1689600 * 32)>;
553 opp-2899200000 {
554 opp-hz = /bits/ 64 <2899200000>;
555 opp-peak-kBps = <(1689600 * 32)>;
557 opp-2995200000 {
558 opp-hz = /bits/ 64 <2995200000>;
559 opp-peak-kBps = <(1689600 * 32)>;
563 qup_opp_table_100mhz: opp-table-qup100mhz {
564 compatible = "operating-points-v2";
566 opp-75000000 {
567 opp-hz = /bits/ 64 <75000000>;
568 required-opps = <&rpmhpd_opp_low_svs>;
571 opp-100000000 {
572 opp-hz = /bits/ 64 <100000000>;
573 required-opps = <&rpmhpd_opp_svs>;
578 compatible = "arm,armv8-pmuv3";
583 compatible = "arm,psci-1.0";
586 CPU_PD0: power-domain-cpu0 {
587 #power-domain-cells = <0>;
588 power-domains = <&CLUSTER_PD>;
589 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
592 CPU_PD1: power-domain-cpu1 {
593 #power-domain-cells = <0>;
594 power-domains = <&CLUSTER_PD>;
595 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
598 CPU_PD2: power-domain-cpu2 {
599 #power-domain-cells = <0>;
600 power-domains = <&CLUSTER_PD>;
601 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
604 CPU_PD3: power-domain-cpu3 {
605 #power-domain-cells = <0>;
606 power-domains = <&CLUSTER_PD>;
607 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
610 CPU_PD4: power-domain-cpu4 {
611 #power-domain-cells = <0>;
612 power-domains = <&CLUSTER_PD>;
613 domain-idle-states = <&BIG_CPU_SLEEP_0>;
616 CPU_PD5: power-domain-cpu5 {
617 #power-domain-cells = <0>;
618 power-domains = <&CLUSTER_PD>;
619 domain-idle-states = <&BIG_CPU_SLEEP_0>;
622 CPU_PD6: power-domain-cpu6 {
623 #power-domain-cells = <0>;
624 power-domains = <&CLUSTER_PD>;
625 domain-idle-states = <&BIG_CPU_SLEEP_0>;
628 CPU_PD7: power-domain-cpu7 {
629 #power-domain-cells = <0>;
630 power-domains = <&CLUSTER_PD>;
631 domain-idle-states = <&BIG_CPU_SLEEP_0>;
634 CLUSTER_PD: power-domain-cpu-cluster0 {
635 #power-domain-cells = <0>;
636 domain-idle-states = <&CLUSTER_SLEEP_0>;
640 reserved-memory {
641 #address-cells = <2>;
642 #size-cells = <2>;
645 reserved-region@80000000 {
647 no-map;
650 cmd_db: cmd-db-region@80860000 {
651 compatible = "qcom,cmd-db";
653 no-map;
656 reserved-region@80880000 {
658 no-map;
661 smem_mem: smem-region@80900000 {
664 no-map;
668 reserved-region@80b00000 {
670 no-map;
673 reserved-region@83b00000 {
675 no-map;
678 reserved-region@85b00000 {
680 no-map;
683 pil_adsp_mem: adsp-region@86c00000 {
685 no-map;
688 pil_nsp0_mem: cdsp0-region@8a100000 {
690 no-map;
693 pil_nsp1_mem: cdsp1-region@8c600000 {
695 no-map;
698 reserved-region@aeb00000 {
700 no-map;
704 smp2p-adsp {
707 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
713 qcom,local-pid = <0>;
714 qcom,remote-pid = <2>;
716 smp2p_adsp_out: master-kernel {
717 qcom,entry-name = "master-kernel";
718 #qcom,smem-state-cells = <1>;
721 smp2p_adsp_in: slave-kernel {
722 qcom,entry-name = "slave-kernel";
723 interrupt-controller;
724 #interrupt-cells = <2>;
728 smp2p-nsp0 {
731 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
737 qcom,local-pid = <0>;
738 qcom,remote-pid = <5>;
740 smp2p_nsp0_out: master-kernel {
741 qcom,entry-name = "master-kernel";
742 #qcom,smem-state-cells = <1>;
745 smp2p_nsp0_in: slave-kernel {
746 qcom,entry-name = "slave-kernel";
747 interrupt-controller;
748 #interrupt-cells = <2>;
752 smp2p-nsp1 {
755 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
761 qcom,local-pid = <0>;
762 qcom,remote-pid = <12>;
764 smp2p_nsp1_out: master-kernel {
765 qcom,entry-name = "master-kernel";
766 #qcom,smem-state-cells = <1>;
769 smp2p_nsp1_in: slave-kernel {
770 qcom,entry-name = "slave-kernel";
771 interrupt-controller;
772 #interrupt-cells = <2>;
777 compatible = "simple-bus";
778 #address-cells = <2>;
779 #size-cells = <2>;
781 dma-ranges = <0 0 0 0 0x10 0>;
784 compatible = "qcom,sc8280xp-ethqos";
787 reg-names = "stmmaceth", "rgmii";
793 clock-names = "stmmaceth",
800 interrupt-names = "macirq", "eth_lpi";
803 power-domains = <&gcc EMAC_0_GDSC>;
807 rx-fifo-depth = <4096>;
808 tx-fifo-depth = <4096>;
813 gcc: clock-controller@100000 {
814 compatible = "qcom,gcc-sc8280xp";
816 #clock-cells = <1>;
817 #reset-cells = <1>;
818 #power-domain-cells = <1>;
852 power-domains = <&rpmhpd SC8280XP_CX>;
856 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
859 interrupt-controller;
860 #interrupt-cells = <3>;
861 #mbox-cells = <2>;
865 compatible = "qcom,geni-se-qup";
869 clock-names = "m-ahb", "s-ahb";
872 #address-cells = <2>;
873 #size-cells = <2>;
879 compatible = "qcom,geni-i2c";
881 #address-cells = <1>;
882 #size-cells = <0>;
884 clock-names = "se";
886 power-domains = <&rpmhpd SC8280XP_CX>;
890 interconnect-names = "qup-core", "qup-config", "qup-memory";
895 compatible = "qcom,geni-spi";
897 #address-cells = <1>;
898 #size-cells = <0>;
900 clock-names = "se";
902 power-domains = <&rpmhpd SC8280XP_CX>;
906 interconnect-names = "qup-core", "qup-config", "qup-memory";
911 compatible = "qcom,geni-i2c";
913 #address-cells = <1>;
914 #size-cells = <0>;
916 clock-names = "se";
918 power-domains = <&rpmhpd SC8280XP_CX>;
922 interconnect-names = "qup-core", "qup-config", "qup-memory";
927 compatible = "qcom,geni-spi";
929 #address-cells = <1>;
930 #size-cells = <0>;
932 clock-names = "se";
934 power-domains = <&rpmhpd SC8280XP_CX>;
938 interconnect-names = "qup-core", "qup-config", "qup-memory";
943 compatible = "qcom,geni-uart";
946 clock-names = "se";
948 operating-points-v2 = <&qup_opp_table_100mhz>;
949 power-domains = <&rpmhpd SC8280XP_CX>;
952 interconnect-names = "qup-core", "qup-config";
957 compatible = "qcom,geni-i2c";
959 #address-cells = <1>;
960 #size-cells = <0>;
962 clock-names = "se";
964 power-domains = <&rpmhpd SC8280XP_CX>;
968 interconnect-names = "qup-core", "qup-config", "qup-memory";
973 compatible = "qcom,geni-spi";
975 #address-cells = <1>;
976 #size-cells = <0>;
978 clock-names = "se";
980 power-domains = <&rpmhpd SC8280XP_CX>;
984 interconnect-names = "qup-core", "qup-config", "qup-memory";
989 compatible = "qcom,geni-i2c";
991 #address-cells = <1>;
992 #size-cells = <0>;
994 clock-names = "se";
996 power-domains = <&rpmhpd SC8280XP_CX>;
1000 interconnect-names = "qup-core", "qup-config", "qup-memory";
1005 compatible = "qcom,geni-spi";
1007 #address-cells = <1>;
1008 #size-cells = <0>;
1010 clock-names = "se";
1012 power-domains = <&rpmhpd SC8280XP_CX>;
1016 interconnect-names = "qup-core", "qup-config", "qup-memory";
1021 compatible = "qcom,geni-i2c";
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1026 clock-names = "se";
1028 power-domains = <&rpmhpd SC8280XP_CX>;
1032 interconnect-names = "qup-core", "qup-config", "qup-memory";
1037 compatible = "qcom,geni-spi";
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1042 clock-names = "se";
1044 power-domains = <&rpmhpd SC8280XP_CX>;
1048 interconnect-names = "qup-core", "qup-config", "qup-memory";
1053 compatible = "qcom,geni-i2c";
1055 clock-names = "se";
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1060 power-domains = <&rpmhpd SC8280XP_CX>;
1064 interconnect-names = "qup-core", "qup-config", "qup-memory";
1069 compatible = "qcom,geni-spi";
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1074 clock-names = "se";
1076 power-domains = <&rpmhpd SC8280XP_CX>;
1080 interconnect-names = "qup-core", "qup-config", "qup-memory";
1085 compatible = "qcom,geni-i2c";
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1089 clock-names = "se";
1092 power-domains = <&rpmhpd SC8280XP_CX>;
1096 interconnect-names = "qup-core", "qup-config", "qup-memory";
1101 compatible = "qcom,geni-spi";
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1106 clock-names = "se";
1108 power-domains = <&rpmhpd SC8280XP_CX>;
1112 interconnect-names = "qup-core", "qup-config", "qup-memory";
1117 compatible = "qcom,geni-i2c";
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1121 clock-names = "se";
1124 power-domains = <&rpmhpd SC8280XP_CX>;
1128 interconnect-names = "qup-core", "qup-config", "qup-memory";
1133 compatible = "qcom,geni-spi";
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1138 clock-names = "se";
1140 power-domains = <&rpmhpd SC8280XP_CX>;
1144 interconnect-names = "qup-core", "qup-config", "qup-memory";
1150 compatible = "qcom,geni-se-qup";
1154 clock-names = "m-ahb", "s-ahb";
1157 #address-cells = <2>;
1158 #size-cells = <2>;
1164 compatible = "qcom,geni-i2c";
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1168 clock-names = "se";
1171 power-domains = <&rpmhpd SC8280XP_CX>;
1175 interconnect-names = "qup-core", "qup-config", "qup-memory";
1180 compatible = "qcom,geni-spi";
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1185 clock-names = "se";
1187 power-domains = <&rpmhpd SC8280XP_CX>;
1191 interconnect-names = "qup-core", "qup-config", "qup-memory";
1196 compatible = "qcom,geni-i2c";
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1200 clock-names = "se";
1203 power-domains = <&rpmhpd SC8280XP_CX>;
1207 interconnect-names = "qup-core", "qup-config", "qup-memory";
1212 compatible = "qcom,geni-spi";
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1217 clock-names = "se";
1219 power-domains = <&rpmhpd SC8280XP_CX>;
1223 interconnect-names = "qup-core", "qup-config", "qup-memory";
1228 compatible = "qcom,geni-i2c";
1230 #address-cells = <1>;
1231 #size-cells = <0>;
1232 clock-names = "se";
1235 power-domains = <&rpmhpd SC8280XP_CX>;
1239 interconnect-names = "qup-core", "qup-config", "qup-memory";
1244 compatible = "qcom,geni-spi";
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1249 clock-names = "se";
1251 power-domains = <&rpmhpd SC8280XP_CX>;
1255 interconnect-names = "qup-core", "qup-config", "qup-memory";
1260 compatible = "qcom,geni-uart";
1263 clock-names = "se";
1265 operating-points-v2 = <&qup_opp_table_100mhz>;
1266 power-domains = <&rpmhpd SC8280XP_CX>;
1269 interconnect-names = "qup-core", "qup-config";
1274 compatible = "qcom,geni-i2c";
1276 #address-cells = <1>;
1277 #size-cells = <0>;
1278 clock-names = "se";
1281 power-domains = <&rpmhpd SC8280XP_CX>;
1285 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 compatible = "qcom,geni-spi";
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1295 clock-names = "se";
1297 power-domains = <&rpmhpd SC8280XP_CX>;
1301 interconnect-names = "qup-core", "qup-config", "qup-memory";
1306 compatible = "qcom,geni-i2c";
1308 clock-names = "se";
1311 #address-cells = <1>;
1312 #size-cells = <0>;
1313 power-domains = <&rpmhpd SC8280XP_CX>;
1317 interconnect-names = "qup-core", "qup-config", "qup-memory";
1322 compatible = "qcom,geni-spi";
1324 #address-cells = <1>;
1325 #size-cells = <0>;
1327 clock-names = "se";
1329 power-domains = <&rpmhpd SC8280XP_CX>;
1333 interconnect-names = "qup-core", "qup-config", "qup-memory";
1338 compatible = "qcom,geni-i2c";
1340 #address-cells = <1>;
1341 #size-cells = <0>;
1342 clock-names = "se";
1345 power-domains = <&rpmhpd SC8280XP_CX>;
1349 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 compatible = "qcom,geni-spi";
1356 #address-cells = <1>;
1357 #size-cells = <0>;
1359 clock-names = "se";
1361 power-domains = <&rpmhpd SC8280XP_CX>;
1365 interconnect-names = "qup-core", "qup-config", "qup-memory";
1370 compatible = "qcom,geni-i2c";
1372 #address-cells = <1>;
1373 #size-cells = <0>;
1374 clock-names = "se";
1377 power-domains = <&rpmhpd SC8280XP_CX>;
1381 interconnect-names = "qup-core", "qup-config", "qup-memory";
1386 compatible = "qcom,geni-spi";
1388 #address-cells = <1>;
1389 #size-cells = <0>;
1391 clock-names = "se";
1393 power-domains = <&rpmhpd SC8280XP_CX>;
1397 interconnect-names = "qup-core", "qup-config", "qup-memory";
1402 compatible = "qcom,geni-i2c";
1404 #address-cells = <1>;
1405 #size-cells = <0>;
1406 clock-names = "se";
1409 power-domains = <&rpmhpd SC8280XP_CX>;
1413 interconnect-names = "qup-core", "qup-config", "qup-memory";
1418 compatible = "qcom,geni-spi";
1420 #address-cells = <1>;
1421 #size-cells = <0>;
1423 clock-names = "se";
1425 power-domains = <&rpmhpd SC8280XP_CX>;
1429 interconnect-names = "qup-core", "qup-config", "qup-memory";
1435 compatible = "qcom,geni-se-qup";
1439 clock-names = "m-ahb", "s-ahb";
1442 #address-cells = <2>;
1443 #size-cells = <2>;
1449 compatible = "qcom,geni-i2c";
1451 #address-cells = <1>;
1452 #size-cells = <0>;
1454 clock-names = "se";
1456 power-domains = <&rpmhpd SC8280XP_CX>;
1460 interconnect-names = "qup-core", "qup-config", "qup-memory";
1465 compatible = "qcom,geni-spi";
1467 #address-cells = <1>;
1468 #size-cells = <0>;
1470 clock-names = "se";
1472 power-domains = <&rpmhpd SC8280XP_CX>;
1476 interconnect-names = "qup-core", "qup-config", "qup-memory";
1481 compatible = "qcom,geni-i2c";
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1486 clock-names = "se";
1488 power-domains = <&rpmhpd SC8280XP_CX>;
1492 interconnect-names = "qup-core", "qup-config", "qup-memory";
1497 compatible = "qcom,geni-spi";
1499 #address-cells = <1>;
1500 #size-cells = <0>;
1502 clock-names = "se";
1504 power-domains = <&rpmhpd SC8280XP_CX>;
1508 interconnect-names = "qup-core", "qup-config", "qup-memory";
1513 compatible = "qcom,geni-i2c";
1515 #address-cells = <1>;
1516 #size-cells = <0>;
1518 clock-names = "se";
1520 power-domains = <&rpmhpd SC8280XP_CX>;
1524 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 compatible = "qcom,geni-spi";
1531 #address-cells = <1>;
1532 #size-cells = <0>;
1534 clock-names = "se";
1536 power-domains = <&rpmhpd SC8280XP_CX>;
1540 interconnect-names = "qup-core", "qup-config", "qup-memory";
1545 compatible = "qcom,geni-i2c";
1547 #address-cells = <1>;
1548 #size-cells = <0>;
1550 clock-names = "se";
1552 power-domains = <&rpmhpd SC8280XP_CX>;
1556 interconnect-names = "qup-core", "qup-config", "qup-memory";
1561 compatible = "qcom,geni-spi";
1563 #address-cells = <1>;
1564 #size-cells = <0>;
1566 clock-names = "se";
1568 power-domains = <&rpmhpd SC8280XP_CX>;
1572 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577 compatible = "qcom,geni-i2c";
1579 #address-cells = <1>;
1580 #size-cells = <0>;
1582 clock-names = "se";
1584 power-domains = <&rpmhpd SC8280XP_CX>;
1588 interconnect-names = "qup-core", "qup-config", "qup-memory";
1593 compatible = "qcom,geni-spi";
1595 #address-cells = <1>;
1596 #size-cells = <0>;
1598 clock-names = "se";
1600 power-domains = <&rpmhpd SC8280XP_CX>;
1604 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609 compatible = "qcom,geni-i2c";
1611 #address-cells = <1>;
1612 #size-cells = <0>;
1614 clock-names = "se";
1616 power-domains = <&rpmhpd SC8280XP_CX>;
1620 interconnect-names = "qup-core", "qup-config", "qup-memory";
1625 compatible = "qcom,geni-spi";
1627 #address-cells = <1>;
1628 #size-cells = <0>;
1630 clock-names = "se";
1632 power-domains = <&rpmhpd SC8280XP_CX>;
1636 interconnect-names = "qup-core", "qup-config", "qup-memory";
1641 compatible = "qcom,geni-i2c";
1643 #address-cells = <1>;
1644 #size-cells = <0>;
1646 clock-names = "se";
1648 power-domains = <&rpmhpd SC8280XP_CX>;
1652 interconnect-names = "qup-core", "qup-config", "qup-memory";
1657 compatible = "qcom,geni-spi";
1659 #address-cells = <1>;
1660 #size-cells = <0>;
1662 clock-names = "se";
1664 power-domains = <&rpmhpd SC8280XP_CX>;
1668 interconnect-names = "qup-core", "qup-config", "qup-memory";
1673 compatible = "qcom,geni-i2c";
1675 #address-cells = <1>;
1676 #size-cells = <0>;
1678 clock-names = "se";
1680 power-domains = <&rpmhpd SC8280XP_CX>;
1684 interconnect-names = "qup-core", "qup-config", "qup-memory";
1689 compatible = "qcom,geni-spi";
1691 #address-cells = <1>;
1692 #size-cells = <0>;
1694 clock-names = "se";
1696 power-domains = <&rpmhpd SC8280XP_CX>;
1700 interconnect-names = "qup-core", "qup-config", "qup-memory";
1706 compatible = "qcom,prng-ee";
1709 clock-names = "core";
1714 compatible = "qcom,pcie-sc8280xp";
1721 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1722 #address-cells = <3>;
1723 #size-cells = <2>;
1726 bus-range = <0x00 0xff>;
1728 dma-coherent;
1730 linux,pci-domain = <6>;
1731 num-lanes = <1>;
1737 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1739 #interrupt-cells = <1>;
1740 interrupt-map-mask = <0 0 0 0x7>;
1741 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1742 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1755 clock-names = "aux",
1765 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1766 assigned-clock-rates = <19200000>;
1770 interconnect-names = "pcie-mem", "cpu-pcie";
1773 reset-names = "pci";
1775 power-domains = <&gcc PCIE_4_GDSC>;
1776 required-opps = <&rpmhpd_opp_nom>;
1779 phy-names = "pciephy";
1785 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
1794 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1797 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1798 assigned-clock-rates = <100000000>;
1800 power-domains = <&gcc PCIE_4_GDSC>;
1801 required-opps = <&rpmhpd_opp_nom>;
1804 reset-names = "phy";
1806 #clock-cells = <0>;
1807 clock-output-names = "pcie_4_pipe_clk";
1809 #phy-cells = <0>;
1816 compatible = "qcom,pcie-sc8280xp";
1823 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1824 #address-cells = <3>;
1825 #size-cells = <2>;
1828 bus-range = <0x00 0xff>;
1830 dma-coherent;
1832 linux,pci-domain = <5>;
1833 num-lanes = <2>;
1839 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1841 #interrupt-cells = <1>;
1842 interrupt-map-mask = <0 0 0 0x7>;
1843 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1844 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1856 clock-names = "aux",
1865 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1866 assigned-clock-rates = <19200000>;
1870 interconnect-names = "pcie-mem", "cpu-pcie";
1873 reset-names = "pci";
1875 power-domains = <&gcc PCIE_3B_GDSC>;
1876 required-opps = <&rpmhpd_opp_nom>;
1879 phy-names = "pciephy";
1885 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1894 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1897 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1898 assigned-clock-rates = <100000000>;
1900 power-domains = <&gcc PCIE_3B_GDSC>;
1901 required-opps = <&rpmhpd_opp_nom>;
1904 reset-names = "phy";
1906 #clock-cells = <0>;
1907 clock-output-names = "pcie_3b_pipe_clk";
1909 #phy-cells = <0>;
1916 compatible = "qcom,pcie-sc8280xp";
1923 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1924 #address-cells = <3>;
1925 #size-cells = <2>;
1928 bus-range = <0x00 0xff>;
1930 dma-coherent;
1932 linux,pci-domain = <4>;
1933 num-lanes = <4>;
1939 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1941 #interrupt-cells = <1>;
1942 interrupt-map-mask = <0 0 0 0x7>;
1943 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1944 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1956 clock-names = "aux",
1965 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
1966 assigned-clock-rates = <19200000>;
1970 interconnect-names = "pcie-mem", "cpu-pcie";
1973 reset-names = "pci";
1975 power-domains = <&gcc PCIE_3A_GDSC>;
1976 required-opps = <&rpmhpd_opp_nom>;
1979 phy-names = "pciephy";
1985 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
1995 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1998 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
1999 assigned-clock-rates = <100000000>;
2001 power-domains = <&gcc PCIE_3A_GDSC>;
2002 required-opps = <&rpmhpd_opp_nom>;
2005 reset-names = "phy";
2007 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2009 #clock-cells = <0>;
2010 clock-output-names = "pcie_3a_pipe_clk";
2012 #phy-cells = <0>;
2019 compatible = "qcom,pcie-sc8280xp";
2026 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2027 #address-cells = <3>;
2028 #size-cells = <2>;
2031 bus-range = <0x00 0xff>;
2033 dma-coherent;
2035 linux,pci-domain = <3>;
2036 num-lanes = <2>;
2042 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2044 #interrupt-cells = <1>;
2045 interrupt-map-mask = <0 0 0 0x7>;
2046 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2047 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2059 clock-names = "aux",
2068 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2069 assigned-clock-rates = <19200000>;
2073 interconnect-names = "pcie-mem", "cpu-pcie";
2076 reset-names = "pci";
2078 power-domains = <&gcc PCIE_2B_GDSC>;
2079 required-opps = <&rpmhpd_opp_nom>;
2082 phy-names = "pciephy";
2088 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2097 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2100 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2101 assigned-clock-rates = <100000000>;
2103 power-domains = <&gcc PCIE_2B_GDSC>;
2104 required-opps = <&rpmhpd_opp_nom>;
2107 reset-names = "phy";
2109 #clock-cells = <0>;
2110 clock-output-names = "pcie_2b_pipe_clk";
2112 #phy-cells = <0>;
2119 compatible = "qcom,pcie-sc8280xp";
2126 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2127 #address-cells = <3>;
2128 #size-cells = <2>;
2131 bus-range = <0x00 0xff>;
2133 dma-coherent;
2135 linux,pci-domain = <2>;
2136 num-lanes = <4>;
2142 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2144 #interrupt-cells = <1>;
2145 interrupt-map-mask = <0 0 0 0x7>;
2146 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2147 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
2159 clock-names = "aux",
2168 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2169 assigned-clock-rates = <19200000>;
2173 interconnect-names = "pcie-mem", "cpu-pcie";
2176 reset-names = "pci";
2178 power-domains = <&gcc PCIE_2A_GDSC>;
2179 required-opps = <&rpmhpd_opp_nom>;
2182 phy-names = "pciephy";
2188 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2198 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2201 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2202 assigned-clock-rates = <100000000>;
2204 power-domains = <&gcc PCIE_2A_GDSC>;
2205 required-opps = <&rpmhpd_opp_nom>;
2208 reset-names = "phy";
2210 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2212 #clock-cells = <0>;
2213 clock-output-names = "pcie_2a_pipe_clk";
2215 #phy-cells = <0>;
2221 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2222 "jedec,ufs-2.0";
2226 phy-names = "ufsphy";
2227 lanes-per-direction = <2>;
2228 #reset-cells = <1>;
2230 reset-names = "rst";
2232 power-domains = <&gcc UFS_PHY_GDSC>;
2233 required-opps = <&rpmhpd_opp_nom>;
2236 dma-coherent;
2246 clock-names = "core_clk",
2254 freq-table-hz = <75000000 300000000>,
2266 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2271 clock-names = "ref", "ref_aux";
2273 power-domains = <&gcc UFS_PHY_GDSC>;
2276 reset-names = "ufsphy";
2278 #phy-cells = <0>;
2284 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2285 "jedec,ufs-2.0";
2289 phy-names = "ufsphy";
2290 lanes-per-direction = <2>;
2291 #reset-cells = <1>;
2293 reset-names = "rst";
2295 power-domains = <&gcc UFS_CARD_GDSC>;
2298 dma-coherent;
2308 clock-names = "core_clk",
2316 freq-table-hz = <75000000 300000000>,
2328 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2333 clock-names = "ref", "ref_aux";
2335 power-domains = <&gcc UFS_CARD_GDSC>;
2338 reset-names = "ufsphy";
2340 #phy-cells = <0>;
2346 compatible = "qcom,tcsr-mutex";
2348 #hwlock-cells = <1>;
2352 compatible = "qcom,sc8280xp-tcsr", "syscon";
2357 compatible = "qcom,adreno-690.0", "qcom,adreno";
2362 reg-names = "kgsl_3d0_reg_memory",
2367 operating-points-v2 = <&gpu_opp_table>;
2371 interconnect-names = "gfx-mem";
2372 #cooling-cells = <2>;
2376 gpu_opp_table: opp-table {
2377 compatible = "operating-points-v2";
2379 opp-270000000 {
2380 opp-hz = /bits/ 64 <270000000>;
2381 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2382 opp-peak-kBps = <451000>;
2385 opp-410000000 {
2386 opp-hz = /bits/ 64 <410000000>;
2387 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2388 opp-peak-kBps = <1555000>;
2391 opp-500000000 {
2392 opp-hz = /bits/ 64 <500000000>;
2393 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2394 opp-peak-kBps = <1555000>;
2397 opp-547000000 {
2398 opp-hz = /bits/ 64 <547000000>;
2399 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2400 opp-peak-kBps = <1555000>;
2403 opp-606000000 {
2404 opp-hz = /bits/ 64 <606000000>;
2405 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2406 opp-peak-kBps = <2736000>;
2409 opp-640000000 {
2410 opp-hz = /bits/ 64 <640000000>;
2411 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2412 opp-peak-kBps = <2736000>;
2415 opp-655000000 {
2416 opp-hz = /bits/ 64 <655000000>;
2417 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2418 opp-peak-kBps = <2736000>;
2421 opp-690000000 {
2422 opp-hz = /bits/ 64 <690000000>;
2423 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2424 opp-peak-kBps = <2736000>;
2430 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
2434 reg-names = "gmu", "rscc", "gmu_pdc";
2437 interrupt-names = "hfi", "gmu";
2445 clock-names = "gmu",
2452 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2454 power-domain-names = "cx",
2457 operating-points-v2 = <&gmu_opp_table>;
2459 gmu_opp_table: opp-table {
2460 compatible = "operating-points-v2";
2462 opp-200000000 {
2463 opp-hz = /bits/ 64 <200000000>;
2464 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2467 opp-500000000 {
2468 opp-hz = /bits/ 64 <500000000>;
2469 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2474 gpucc: clock-controller@3d90000 {
2475 compatible = "qcom,sc8280xp-gpucc";
2480 clock-names = "bi_tcxo",
2484 power-domains = <&rpmhpd SC8280XP_GFX>;
2485 #clock-cells = <1>;
2486 #reset-cells = <1>;
2487 #power-domain-cells = <1>;
2491 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
2492 "qcom,smmu-500", "arm,mmu-500";
2494 #iommu-cells = <2>;
2495 #global-interrupts = <2>;
2518 clock-names = "gcc_gpu_memnoc_gfx_clk",
2526 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2527 dma-coherent;
2531 compatible = "qcom,sc8280xp-usb-hs-phy",
2532 "qcom,usb-snps-hs-5nm-phy";
2535 clock-names = "ref";
2538 #phy-cells = <0>;
2544 compatible = "qcom,sc8280xp-usb-hs-phy",
2545 "qcom,usb-snps-hs-5nm-phy";
2548 clock-names = "ref";
2551 #phy-cells = <0>;
2557 compatible = "qcom,sc8280xp-usb-hs-phy",
2558 "qcom,usb-snps-hs-5nm-phy";
2561 clock-names = "ref";
2564 #phy-cells = <0>;
2570 compatible = "qcom,sc8280xp-usb-hs-phy",
2571 "qcom,usb-snps-hs-5nm-phy";
2574 clock-names = "ref";
2577 #phy-cells = <0>;
2583 compatible = "qcom,sc8280xp-usb-hs-phy",
2584 "qcom,usb-snps-hs-5nm-phy";
2587 clock-names = "ref";
2590 #phy-cells = <0>;
2596 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2603 clock-names = "aux", "ref", "com_aux", "pipe";
2607 reset-names = "phy", "phy_phy";
2609 power-domains = <&gcc USB30_MP_GDSC>;
2611 #clock-cells = <0>;
2612 clock-output-names = "usb2_phy0_pipe_clk";
2614 #phy-cells = <0>;
2620 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2627 clock-names = "aux", "ref", "com_aux", "pipe";
2631 reset-names = "phy", "phy_phy";
2633 power-domains = <&gcc USB30_MP_GDSC>;
2635 #clock-cells = <0>;
2636 clock-output-names = "usb2_phy1_pipe_clk";
2638 #phy-cells = <0>;
2644 compatible = "qcom,sc8280xp-adsp-pas";
2647 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2650 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2653 interrupt-names = "wdog", "fatal", "ready",
2654 "handover", "stop-ack", "shutdown-ack";
2657 clock-names = "xo";
2659 power-domains = <&rpmhpd SC8280XP_LCX>,
2661 power-domain-names = "lcx", "lmx";
2663 memory-region = <&pil_adsp_mem>;
2667 qcom,smem-states = <&smp2p_adsp_out 0>;
2668 qcom,smem-state-names = "stop";
2672 remoteproc_adsp_glink: glink-edge {
2673 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2680 qcom,remote-pid = <2>;
2684 qcom,glink-channels = "adsp_apps";
2687 #address-cells = <1>;
2688 #size-cells = <0>;
2693 #sound-dai-cells = <0>;
2694 qcom,protection-domain = "avs/audio",
2697 compatible = "qcom,q6apm-dais";
2702 compatible = "qcom,q6apm-lpass-dais";
2703 #sound-dai-cells = <1>;
2707 q6prm: service@2 {
2710 qcom,protection-domain = "avs/audio",
2712 q6prmcc: clock-controller {
2713 compatible = "qcom,q6prm-lpass-clocks";
2714 #clock-cells = <2>;
2722 compatible = "qcom,sc8280xp-lpass-rx-macro";
2729 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2730 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2732 assigned-clock-rates = <19200000>, <19200000>;
2734 clock-output-names = "mclk";
2735 #clock-cells = <0>;
2736 #sound-dai-cells = <1>;
2738 pinctrl-names = "default";
2739 pinctrl-0 = <&rx_swr_default>;
2744 swr1: soundwire-controller@3210000 {
2745 compatible = "qcom,soundwire-v1.6.0";
2749 clock-names = "iface";
2751 reset-names = "swr_audio_cgcr";
2754 qcom,din-ports = <0>;
2755 qcom,dout-ports = <5>;
2757 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2758 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2759 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2760 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2761 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2762 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2763 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2764 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2765 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2767 #sound-dai-cells = <1>;
2768 #address-cells = <2>;
2769 #size-cells = <0>;
2775 compatible = "qcom,sc8280xp-lpass-tx-macro";
2777 pinctrl-names = "default";
2778 pinctrl-0 = <&tx_swr_default>;
2785 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2786 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2788 assigned-clock-rates = <19200000>, <19200000>;
2789 clock-output-names = "mclk";
2791 #clock-cells = <0>;
2792 #sound-dai-cells = <1>;
2798 compatible = "qcom,sc8280xp-lpass-wsa-macro";
2805 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2806 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2808 assigned-clock-rates = <19200000>, <19200000>;
2810 #clock-cells = <0>;
2811 clock-output-names = "mclk";
2812 #sound-dai-cells = <1>;
2814 pinctrl-names = "default";
2815 pinctrl-0 = <&wsa_swr_default>;
2820 swr0: soundwire-controller@3250000 {
2822 compatible = "qcom,soundwire-v1.6.0";
2825 clock-names = "iface";
2827 reset-names = "swr_audio_cgcr";
2830 qcom,din-ports = <2>;
2831 qcom,dout-ports = <6>;
2833 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2834 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2835 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2836 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2837 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2838 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2839 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2840 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2841 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2843 #sound-dai-cells = <1>;
2844 #address-cells = <2>;
2845 #size-cells = <0>;
2850 lpass_audiocc: clock-controller@32a9000 {
2851 compatible = "qcom,sc8280xp-lpassaudiocc";
2853 #clock-cells = <1>;
2854 #reset-cells = <1>;
2857 swr2: soundwire-controller@3330000 {
2858 compatible = "qcom,soundwire-v1.6.0";
2862 interrupt-names = "core", "wakeup";
2865 clock-names = "iface";
2867 reset-names = "swr_audio_cgcr";
2869 #sound-dai-cells = <1>;
2870 #address-cells = <2>;
2871 #size-cells = <0>;
2873 qcom,din-ports = <4>;
2874 qcom,dout-ports = <0>;
2875 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2876 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2877 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2878 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2879 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2880 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2881 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2882 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2883 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2889 compatible = "qcom,sc8280xp-lpass-va-macro";
2895 clock-names = "mclk", "macro", "dcodec", "npl";
2896 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2897 assigned-clock-rates = <19200000>;
2899 #clock-cells = <0>;
2900 clock-output-names = "fsgen";
2901 #sound-dai-cells = <1>;
2907 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
2910 gpio-controller;
2911 #gpio-cells = <2>;
2912 gpio-ranges = <&lpass_tlmm 0 0 19>;
2916 clock-names = "core", "audio";
2920 tx_swr_default: tx-swr-default-state {
2921 clk-pins {
2924 drive-strength = <2>;
2925 slew-rate = <1>;
2926 bias-disable;
2929 data-pins {
2932 drive-strength = <2>;
2933 slew-rate = <1>;
2934 bias-bus-hold;
2938 rx_swr_default: rx-swr-default-state {
2939 clk-pins {
2942 drive-strength = <2>;
2943 slew-rate = <1>;
2944 bias-disable;
2947 data-pins {
2950 drive-strength = <2>;
2951 slew-rate = <1>;
2952 bias-bus-hold;
2956 dmic01_default: dmic01-default-state {
2957 clk-pins {
2960 drive-strength = <8>;
2961 output-high;
2964 data-pins {
2967 drive-strength = <8>;
2968 input-enable;
2972 dmic01_sleep: dmic01-sleep-state {
2973 clk-pins {
2976 drive-strength = <2>;
2977 bias-disable;
2978 output-low;
2981 data-pins {
2984 drive-strength = <2>;
2985 bias-pull-down;
2986 input-enable;
2990 dmic02_default: dmic02-default-state {
2991 clk-pins {
2994 drive-strength = <8>;
2995 output-high;
2998 data-pins {
3001 drive-strength = <8>;
3002 input-enable;
3006 dmic02_sleep: dmic02-sleep-state {
3007 clk-pins {
3010 drive-strength = <2>;
3011 bias-disable;
3012 output-low;
3015 data-pins {
3018 drive-strength = <2>;
3019 bias-pull-down;
3020 input-enable;
3024 wsa_swr_default: wsa-swr-default-state {
3025 clk-pins {
3028 drive-strength = <2>;
3029 slew-rate = <1>;
3030 bias-disable;
3033 data-pins {
3036 drive-strength = <2>;
3037 slew-rate = <1>;
3038 bias-bus-hold;
3042 wsa2_swr_default: wsa2-swr-default-state {
3043 clk-pins {
3046 drive-strength = <2>;
3047 slew-rate = <1>;
3048 bias-disable;
3051 data-pins {
3054 drive-strength = <2>;
3055 slew-rate = <1>;
3056 bias-bus-hold;
3061 lpasscc: clock-controller@33e0000 {
3062 compatible = "qcom,sc8280xp-lpasscc";
3064 #clock-cells = <1>;
3065 #reset-cells = <1>;
3069 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
3074 interrupt-names = "hc_irq", "pwr_irq";
3079 clock-names = "iface", "core", "xo";
3083 interconnect-names = "sdhc-ddr","cpu-sdhc";
3085 power-domains = <&rpmhpd SC8280XP_CX>;
3086 operating-points-v2 = <&sdc2_opp_table>;
3087 bus-width = <4>;
3088 dma-coherent;
3092 sdc2_opp_table: opp-table {
3093 compatible = "operating-points-v2";
3095 opp-100000000 {
3096 opp-hz = /bits/ 64 <100000000>;
3097 required-opps = <&rpmhpd_opp_low_svs>;
3098 opp-peak-kBps = <1800000 400000>;
3099 opp-avg-kBps = <100000 0>;
3102 opp-202000000 {
3103 opp-hz = /bits/ 64 <202000000>;
3104 required-opps = <&rpmhpd_opp_svs_l1>;
3105 opp-peak-kBps = <5400000 1600000>;
3106 opp-avg-kBps = <200000 0>;
3112 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3119 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3121 power-domains = <&gcc USB30_PRIM_GDSC>;
3125 reset-names = "phy", "common";
3127 #clock-cells = <1>;
3128 #phy-cells = <1>;
3133 #address-cells = <1>;
3134 #size-cells = <0>;
3142 port@2 {
3143 reg = <2>;
3151 compatible = "qcom,sc8280xp-usb-hs-phy",
3152 "qcom,usb-snps-hs-5nm-phy";
3154 #phy-cells = <0>;
3157 clock-names = "ref";
3165 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3172 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3174 power-domains = <&gcc USB30_SEC_GDSC>;
3178 reset-names = "phy", "common";
3180 #clock-cells = <1>;
3181 #phy-cells = <1>;
3186 #address-cells = <1>;
3187 #size-cells = <0>;
3195 port@2 {
3196 reg = <2>;
3204 compatible = "qcom,sc8280xp-dp-phy";
3212 clock-names = "aux", "cfg_ahb";
3213 power-domains = <&rpmhpd SC8280XP_MX>;
3215 #clock-cells = <1>;
3216 #phy-cells = <0>;
3222 compatible = "qcom,sc8280xp-dp-phy";
3230 clock-names = "aux", "cfg_ahb";
3231 power-domains = <&rpmhpd SC8280XP_MX>;
3233 #clock-cells = <1>;
3234 #phy-cells = <0>;
3240 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3247 operating-points-v2 = <&llcc_bwmon_opp_table>;
3249 llcc_bwmon_opp_table: opp-table {
3250 compatible = "operating-points-v2";
3252 opp-0 {
3253 opp-peak-kBps = <762000>;
3255 opp-1 {
3256 opp-peak-kBps = <1720000>;
3258 opp-2 {
3259 opp-peak-kBps = <2086000>;
3261 opp-3 {
3262 opp-peak-kBps = <2597000>;
3264 opp-4 {
3265 opp-peak-kBps = <2929000>;
3267 opp-5 {
3268 opp-peak-kBps = <3879000>;
3270 opp-6 {
3271 opp-peak-kBps = <5161000>;
3273 opp-7 {
3274 opp-peak-kBps = <5931000>;
3276 opp-8 {
3277 opp-peak-kBps = <6515000>;
3279 opp-9 {
3280 opp-peak-kBps = <7980000>;
3282 opp-10 {
3283 opp-peak-kBps = <8136000>;
3285 opp-11 {
3286 opp-peak-kBps = <10437000>;
3288 opp-12 {
3289 opp-peak-kBps = <12191000>;
3295 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
3301 operating-points-v2 = <&cpu_bwmon_opp_table>;
3303 cpu_bwmon_opp_table: opp-table {
3304 compatible = "operating-points-v2";
3306 opp-0 {
3307 opp-peak-kBps = <2288000>;
3309 opp-1 {
3310 opp-peak-kBps = <4577000>;
3312 opp-2 {
3313 opp-peak-kBps = <7110000>;
3315 opp-3 {
3316 opp-peak-kBps = <9155000>;
3318 opp-4 {
3319 opp-peak-kBps = <12298000>;
3321 opp-5 {
3322 opp-peak-kBps = <14236000>;
3324 opp-6 {
3325 opp-peak-kBps = <15258001>;
3330 system-cache-controller@9200000 {
3331 compatible = "qcom,sc8280xp-llcc";
3337 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3344 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3346 #address-cells = <2>;
3347 #size-cells = <2>;
3359 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3362 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3364 assigned-clock-rates = <19200000>, <200000000>;
3366 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3370 interrupt-names = "pwr_event",
3375 power-domains = <&gcc USB30_PRIM_GDSC>;
3376 required-opps = <&rpmhpd_opp_nom>;
3382 interconnect-names = "usb-ddr", "apps-usb";
3384 wakeup-source;
3394 phy-names = "usb2-phy", "usb3-phy";
3404 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3406 #address-cells = <2>;
3407 #size-cells = <2>;
3419 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3422 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3424 assigned-clock-rates = <19200000>, <200000000>;
3426 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3430 interrupt-names = "pwr_event",
3435 power-domains = <&gcc USB30_SEC_GDSC>;
3436 required-opps = <&rpmhpd_opp_nom>;
3442 interconnect-names = "usb-ddr", "apps-usb";
3444 wakeup-source;
3454 phy-names = "usb2-phy", "usb3-phy";
3463 mdss0: display-subsystem@ae00000 {
3464 compatible = "qcom,sc8280xp-mdss";
3466 reg-names = "mdss";
3471 clock-names = "iface",
3477 interconnect-names = "mdp0-mem", "mdp1-mem";
3479 power-domains = <&dispcc0 MDSS_GDSC>;
3482 interrupt-controller;
3483 #interrupt-cells = <1>;
3484 #address-cells = <2>;
3485 #size-cells = <2>;
3490 mdss0_mdp: display-controller@ae01000 {
3491 compatible = "qcom,sc8280xp-dpu";
3494 reg-names = "mdp", "vbif";
3502 clock-names = "bus",
3508 interrupt-parent = <&mdss0>;
3510 power-domains = <&rpmhpd SC8280XP_MMCX>;
3512 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
3513 assigned-clock-rates = <19200000>;
3514 operating-points-v2 = <&mdss0_mdp_opp_table>;
3517 #address-cells = <1>;
3518 #size-cells = <0>;
3523 remote-endpoint = <&mdss0_dp0_in>;
3530 remote-endpoint = <&mdss0_dp1_in>;
3537 remote-endpoint = <&mdss0_dp3_in>;
3544 remote-endpoint = <&mdss0_dp2_in>;
3549 mdss0_mdp_opp_table: opp-table {
3550 compatible = "operating-points-v2";
3552 opp-200000000 {
3553 opp-hz = /bits/ 64 <200000000>;
3554 required-opps = <&rpmhpd_opp_low_svs>;
3557 opp-300000000 {
3558 opp-hz = /bits/ 64 <300000000>;
3559 required-opps = <&rpmhpd_opp_svs>;
3562 opp-375000000 {
3563 opp-hz = /bits/ 64 <375000000>;
3564 required-opps = <&rpmhpd_opp_svs_l1>;
3567 opp-500000000 {
3568 opp-hz = /bits/ 64 <500000000>;
3569 required-opps = <&rpmhpd_opp_nom>;
3571 opp-600000000 {
3572 opp-hz = /bits/ 64 <600000000>;
3573 required-opps = <&rpmhpd_opp_turbo_l1>;
3578 mdss0_dp0: displayport-controller@ae90000 {
3579 compatible = "qcom,sc8280xp-dp";
3585 interrupt-parent = <&mdss0>;
3592 clock-names = "core_iface", "core_aux",
3597 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3599 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3603 phy-names = "dp";
3605 #sound-dai-cells = <0>;
3607 operating-points-v2 = <&mdss0_dp0_opp_table>;
3608 power-domains = <&rpmhpd SC8280XP_MMCX>;
3613 #address-cells = <1>;
3614 #size-cells = <0>;
3620 remote-endpoint = <&mdss0_intf0_out>;
3632 mdss0_dp0_opp_table: opp-table {
3633 compatible = "operating-points-v2";
3635 opp-160000000 {
3636 opp-hz = /bits/ 64 <160000000>;
3637 required-opps = <&rpmhpd_opp_low_svs>;
3640 opp-270000000 {
3641 opp-hz = /bits/ 64 <270000000>;
3642 required-opps = <&rpmhpd_opp_svs>;
3645 opp-540000000 {
3646 opp-hz = /bits/ 64 <540000000>;
3647 required-opps = <&rpmhpd_opp_svs_l1>;
3650 opp-810000000 {
3651 opp-hz = /bits/ 64 <810000000>;
3652 required-opps = <&rpmhpd_opp_nom>;
3657 mdss0_dp1: displayport-controller@ae98000 {
3658 compatible = "qcom,sc8280xp-dp";
3664 interrupt-parent = <&mdss0>;
3671 clock-names = "core_iface", "core_aux",
3675 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
3677 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3681 phy-names = "dp";
3683 #sound-dai-cells = <0>;
3685 operating-points-v2 = <&mdss0_dp1_opp_table>;
3686 power-domains = <&rpmhpd SC8280XP_MMCX>;
3691 #address-cells = <1>;
3692 #size-cells = <0>;
3698 remote-endpoint = <&mdss0_intf4_out>;
3710 mdss0_dp1_opp_table: opp-table {
3711 compatible = "operating-points-v2";
3713 opp-160000000 {
3714 opp-hz = /bits/ 64 <160000000>;
3715 required-opps = <&rpmhpd_opp_low_svs>;
3718 opp-270000000 {
3719 opp-hz = /bits/ 64 <270000000>;
3720 required-opps = <&rpmhpd_opp_svs>;
3723 opp-540000000 {
3724 opp-hz = /bits/ 64 <540000000>;
3725 required-opps = <&rpmhpd_opp_svs_l1>;
3728 opp-810000000 {
3729 opp-hz = /bits/ 64 <810000000>;
3730 required-opps = <&rpmhpd_opp_nom>;
3735 mdss0_dp2: displayport-controller@ae9a000 {
3736 compatible = "qcom,sc8280xp-dp";
3748 clock-names = "core_iface", "core_aux",
3751 interrupt-parent = <&mdss0>;
3754 phy-names = "dp";
3755 power-domains = <&rpmhpd SC8280XP_MMCX>;
3757 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
3759 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
3760 operating-points-v2 = <&mdss0_dp2_opp_table>;
3762 #sound-dai-cells = <0>;
3767 #address-cells = <1>;
3768 #size-cells = <0>;
3773 remote-endpoint = <&mdss0_intf6_out>;
3782 mdss0_dp2_opp_table: opp-table {
3783 compatible = "operating-points-v2";
3785 opp-160000000 {
3786 opp-hz = /bits/ 64 <160000000>;
3787 required-opps = <&rpmhpd_opp_low_svs>;
3790 opp-270000000 {
3791 opp-hz = /bits/ 64 <270000000>;
3792 required-opps = <&rpmhpd_opp_svs>;
3795 opp-540000000 {
3796 opp-hz = /bits/ 64 <540000000>;
3797 required-opps = <&rpmhpd_opp_svs_l1>;
3800 opp-810000000 {
3801 opp-hz = /bits/ 64 <810000000>;
3802 required-opps = <&rpmhpd_opp_nom>;
3807 mdss0_dp3: displayport-controller@aea0000 {
3808 compatible = "qcom,sc8280xp-dp";
3820 clock-names = "core_iface", "core_aux",
3823 interrupt-parent = <&mdss0>;
3826 phy-names = "dp";
3827 power-domains = <&rpmhpd SC8280XP_MMCX>;
3829 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
3831 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
3832 operating-points-v2 = <&mdss0_dp3_opp_table>;
3834 #sound-dai-cells = <0>;
3839 #address-cells = <1>;
3840 #size-cells = <0>;
3845 remote-endpoint = <&mdss0_intf5_out>;
3854 mdss0_dp3_opp_table: opp-table {
3855 compatible = "operating-points-v2";
3857 opp-160000000 {
3858 opp-hz = /bits/ 64 <160000000>;
3859 required-opps = <&rpmhpd_opp_low_svs>;
3862 opp-270000000 {
3863 opp-hz = /bits/ 64 <270000000>;
3864 required-opps = <&rpmhpd_opp_svs>;
3867 opp-540000000 {
3868 opp-hz = /bits/ 64 <540000000>;
3869 required-opps = <&rpmhpd_opp_svs_l1>;
3872 opp-810000000 {
3873 opp-hz = /bits/ 64 <810000000>;
3874 required-opps = <&rpmhpd_opp_nom>;
3881 compatible = "qcom,sc8280xp-dp-phy";
3889 clock-names = "aux", "cfg_ahb";
3890 power-domains = <&rpmhpd SC8280XP_MX>;
3892 #clock-cells = <1>;
3893 #phy-cells = <0>;
3899 compatible = "qcom,sc8280xp-dp-phy";
3907 clock-names = "aux", "cfg_ahb";
3908 power-domains = <&rpmhpd SC8280XP_MX>;
3910 #clock-cells = <1>;
3911 #phy-cells = <0>;
3916 dispcc0: clock-controller@af00000 {
3917 compatible = "qcom,sc8280xp-dispcc0";
3935 power-domains = <&rpmhpd SC8280XP_MMCX>;
3937 #clock-cells = <1>;
3938 #power-domain-cells = <1>;
3939 #reset-cells = <1>;
3944 pdc: interrupt-controller@b220000 {
3945 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
3947 qcom,pdc-ranges = <0 480 40>,
3952 <62 374 2>,
3953 <64 434 2>,
3962 <199 416 2>,
3995 <250 799 2>,
4001 <259 786 2>,
4002 <261 370 2>,
4003 <263 158 2>;
4004 #interrupt-cells = <2>;
4005 interrupt-parent = <&intc>;
4006 interrupt-controller;
4009 tsens0: thermal-sensor@c263000 {
4010 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4014 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
4016 interrupt-names = "uplow", "critical";
4017 #thermal-sensor-cells = <1>;
4020 tsens1: thermal-sensor@c265000 {
4021 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4025 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
4027 interrupt-names = "uplow", "critical";
4028 #thermal-sensor-cells = <1>;
4031 aoss_qmp: power-management@c300000 {
4032 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
4034 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
4037 #clock-cells = <0>;
4041 compatible = "qcom,rpmh-stats";
4046 compatible = "qcom,spmi-pmic-arb";
4052 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4053 interrupt-names = "periph_irq";
4054 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4057 #address-cells = <2>;
4058 #size-cells = <0>;
4059 interrupt-controller;
4060 #interrupt-cells = <4>;
4064 compatible = "qcom,sc8280xp-tlmm";
4067 gpio-controller;
4068 #gpio-cells = <2>;
4069 interrupt-controller;
4070 #interrupt-cells = <2>;
4071 gpio-ranges = <&tlmm 0 0 230>;
4072 wakeup-parent = <&pdc>;
4076 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
4078 #iommu-cells = <2>;
4079 #global-interrupts = <2>;
4212 intc: interrupt-controller@17a00000 {
4213 compatible = "arm,gic-v3";
4214 interrupt-controller;
4215 #interrupt-cells = <3>;
4219 #redistributor-regions = <1>;
4220 redistributor-stride = <0 0x20000>;
4222 #address-cells = <2>;
4223 #size-cells = <2>;
4226 msi-controller@17a40000 {
4227 compatible = "arm,gic-v3-its";
4229 msi-controller;
4230 #msi-cells = <1>;
4235 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
4242 compatible = "arm,armv7-timer-mem";
4244 #address-cells = <1>;
4245 #size-cells = <1>;
4249 frame-number = <0>;
4257 frame-number = <1>;
4264 frame-number = <2>;
4271 frame-number = <3>;
4278 frame-number = <4>;
4285 frame-number = <5>;
4292 frame-number = <6>;
4300 compatible = "qcom,rpmh-rsc";
4304 reg-names = "drv-0", "drv-1", "drv-2";
4308 qcom,tcs-offset = <0xd00>;
4309 qcom,drv-id = <2>;
4310 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
4313 power-domains = <&CLUSTER_PD>;
4315 apps_bcm_voter: bcm-voter {
4316 compatible = "qcom,bcm-voter";
4319 rpmhcc: clock-controller {
4320 compatible = "qcom,sc8280xp-rpmh-clk";
4321 #clock-cells = <1>;
4322 clock-names = "xo";
4326 rpmhpd: power-controller {
4327 compatible = "qcom,sc8280xp-rpmhpd";
4328 #power-domain-cells = <1>;
4329 operating-points-v2 = <&rpmhpd_opp_table>;
4331 rpmhpd_opp_table: opp-table {
4332 compatible = "operating-points-v2";
4335 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4339 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4343 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4347 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4351 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4355 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4359 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4363 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4367 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4371 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4378 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
4382 clock-names = "xo", "alternate";
4384 #interconnect-cells = <1>;
4388 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
4391 reg-names = "freq-domain0", "freq-domain1";
4394 clock-names = "xo", "alternate";
4396 #freq-domain-cells = <1>;
4397 #clock-cells = <1>;
4401 compatible = "qcom,sc8280xp-nsp0-pas";
4404 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
4407 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
4409 interrupt-names = "wdog", "fatal", "ready",
4410 "handover", "stop-ack";
4413 clock-names = "xo";
4415 power-domains = <&rpmhpd SC8280XP_NSP>;
4416 power-domain-names = "nsp";
4418 memory-region = <&pil_nsp0_mem>;
4420 qcom,smem-states = <&smp2p_nsp0_out 0>;
4421 qcom,smem-state-names = "stop";
4427 glink-edge {
4428 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4435 qcom,remote-pid = <5>;
4439 qcom,glink-channels = "fastrpcglink-apps-dsp";
4441 #address-cells = <1>;
4442 #size-cells = <0>;
4444 compute-cb@1 {
4445 compatible = "qcom,fastrpc-compute-cb";
4450 compute-cb@2 {
4451 compatible = "qcom,fastrpc-compute-cb";
4452 reg = <2>;
4456 compute-cb@3 {
4457 compatible = "qcom,fastrpc-compute-cb";
4462 compute-cb@4 {
4463 compatible = "qcom,fastrpc-compute-cb";
4468 compute-cb@5 {
4469 compatible = "qcom,fastrpc-compute-cb";
4474 compute-cb@6 {
4475 compatible = "qcom,fastrpc-compute-cb";
4480 compute-cb@7 {
4481 compatible = "qcom,fastrpc-compute-cb";
4486 compute-cb@8 {
4487 compatible = "qcom,fastrpc-compute-cb";
4492 compute-cb@9 {
4493 compatible = "qcom,fastrpc-compute-cb";
4498 compute-cb@10 {
4499 compatible = "qcom,fastrpc-compute-cb";
4504 compute-cb@11 {
4505 compatible = "qcom,fastrpc-compute-cb";
4510 compute-cb@12 {
4511 compatible = "qcom,fastrpc-compute-cb";
4516 compute-cb@13 {
4517 compatible = "qcom,fastrpc-compute-cb";
4522 compute-cb@14 {
4523 compatible = "qcom,fastrpc-compute-cb";
4532 compatible = "qcom,sc8280xp-nsp1-pas";
4535 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
4538 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
4540 interrupt-names = "wdog", "fatal", "ready",
4541 "handover", "stop-ack";
4544 clock-names = "xo";
4546 power-domains = <&rpmhpd SC8280XP_NSP>;
4547 power-domain-names = "nsp";
4549 memory-region = <&pil_nsp1_mem>;
4551 qcom,smem-states = <&smp2p_nsp1_out 0>;
4552 qcom,smem-state-names = "stop";
4558 glink-edge {
4559 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
4566 qcom,remote-pid = <12>;
4570 mdss1: display-subsystem@22000000 {
4571 compatible = "qcom,sc8280xp-mdss";
4573 reg-names = "mdss";
4578 clock-names = "iface",
4583 interconnect-names = "mdp0-mem", "mdp1-mem";
4587 power-domains = <&dispcc1 MDSS_GDSC>;
4590 interrupt-controller;
4591 #interrupt-cells = <1>;
4592 #address-cells = <2>;
4593 #size-cells = <2>;
4598 mdss1_mdp: display-controller@22001000 {
4599 compatible = "qcom,sc8280xp-dpu";
4602 reg-names = "mdp", "vbif";
4610 clock-names = "bus",
4616 interrupt-parent = <&mdss1>;
4618 power-domains = <&rpmhpd SC8280XP_MMCX>;
4620 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
4621 assigned-clock-rates = <19200000>;
4622 operating-points-v2 = <&mdss1_mdp_opp_table>;
4625 #address-cells = <1>;
4626 #size-cells = <0>;
4631 remote-endpoint = <&mdss1_dp0_in>;
4638 remote-endpoint = <&mdss1_dp1_in>;
4645 remote-endpoint = <&mdss1_dp3_in>;
4652 remote-endpoint = <&mdss1_dp2_in>;
4657 mdss1_mdp_opp_table: opp-table {
4658 compatible = "operating-points-v2";
4660 opp-200000000 {
4661 opp-hz = /bits/ 64 <200000000>;
4662 required-opps = <&rpmhpd_opp_low_svs>;
4665 opp-300000000 {
4666 opp-hz = /bits/ 64 <300000000>;
4667 required-opps = <&rpmhpd_opp_svs>;
4670 opp-375000000 {
4671 opp-hz = /bits/ 64 <375000000>;
4672 required-opps = <&rpmhpd_opp_svs_l1>;
4675 opp-500000000 {
4676 opp-hz = /bits/ 64 <500000000>;
4677 required-opps = <&rpmhpd_opp_nom>;
4679 opp-600000000 {
4680 opp-hz = /bits/ 64 <600000000>;
4681 required-opps = <&rpmhpd_opp_turbo_l1>;
4686 mdss1_dp0: displayport-controller@22090000 {
4687 compatible = "qcom,sc8280xp-dp";
4699 clock-names = "core_iface", "core_aux",
4702 interrupt-parent = <&mdss1>;
4705 phy-names = "dp";
4706 power-domains = <&rpmhpd SC8280XP_MMCX>;
4708 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4710 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
4711 operating-points-v2 = <&mdss1_dp0_opp_table>;
4713 #sound-dai-cells = <0>;
4718 #address-cells = <1>;
4719 #size-cells = <0>;
4724 remote-endpoint = <&mdss1_intf0_out>;
4733 mdss1_dp0_opp_table: opp-table {
4734 compatible = "operating-points-v2";
4736 opp-160000000 {
4737 opp-hz = /bits/ 64 <160000000>;
4738 required-opps = <&rpmhpd_opp_low_svs>;
4741 opp-270000000 {
4742 opp-hz = /bits/ 64 <270000000>;
4743 required-opps = <&rpmhpd_opp_svs>;
4746 opp-540000000 {
4747 opp-hz = /bits/ 64 <540000000>;
4748 required-opps = <&rpmhpd_opp_svs_l1>;
4751 opp-810000000 {
4752 opp-hz = /bits/ 64 <810000000>;
4753 required-opps = <&rpmhpd_opp_nom>;
4758 mdss1_dp1: displayport-controller@22098000 {
4759 compatible = "qcom,sc8280xp-dp";
4771 clock-names = "core_iface", "core_aux",
4774 interrupt-parent = <&mdss1>;
4777 phy-names = "dp";
4778 power-domains = <&rpmhpd SC8280XP_MMCX>;
4780 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4782 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
4783 operating-points-v2 = <&mdss1_dp1_opp_table>;
4785 #sound-dai-cells = <0>;
4790 #address-cells = <1>;
4791 #size-cells = <0>;
4796 remote-endpoint = <&mdss1_intf4_out>;
4805 mdss1_dp1_opp_table: opp-table {
4806 compatible = "operating-points-v2";
4808 opp-160000000 {
4809 opp-hz = /bits/ 64 <160000000>;
4810 required-opps = <&rpmhpd_opp_low_svs>;
4813 opp-270000000 {
4814 opp-hz = /bits/ 64 <270000000>;
4815 required-opps = <&rpmhpd_opp_svs>;
4818 opp-540000000 {
4819 opp-hz = /bits/ 64 <540000000>;
4820 required-opps = <&rpmhpd_opp_svs_l1>;
4823 opp-810000000 {
4824 opp-hz = /bits/ 64 <810000000>;
4825 required-opps = <&rpmhpd_opp_nom>;
4830 mdss1_dp2: displayport-controller@2209a000 {
4831 compatible = "qcom,sc8280xp-dp";
4843 clock-names = "core_iface", "core_aux",
4846 interrupt-parent = <&mdss1>;
4849 phy-names = "dp";
4850 power-domains = <&rpmhpd SC8280XP_MMCX>;
4852 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4854 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
4855 operating-points-v2 = <&mdss1_dp2_opp_table>;
4857 #sound-dai-cells = <0>;
4862 #address-cells = <1>;
4863 #size-cells = <0>;
4868 remote-endpoint = <&mdss1_intf6_out>;
4877 mdss1_dp2_opp_table: opp-table {
4878 compatible = "operating-points-v2";
4880 opp-160000000 {
4881 opp-hz = /bits/ 64 <160000000>;
4882 required-opps = <&rpmhpd_opp_low_svs>;
4885 opp-270000000 {
4886 opp-hz = /bits/ 64 <270000000>;
4887 required-opps = <&rpmhpd_opp_svs>;
4890 opp-540000000 {
4891 opp-hz = /bits/ 64 <540000000>;
4892 required-opps = <&rpmhpd_opp_svs_l1>;
4895 opp-810000000 {
4896 opp-hz = /bits/ 64 <810000000>;
4897 required-opps = <&rpmhpd_opp_nom>;
4902 mdss1_dp3: displayport-controller@220a0000 {
4903 compatible = "qcom,sc8280xp-dp";
4915 clock-names = "core_iface", "core_aux",
4918 interrupt-parent = <&mdss1>;
4921 phy-names = "dp";
4922 power-domains = <&rpmhpd SC8280XP_MMCX>;
4924 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4926 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
4927 operating-points-v2 = <&mdss1_dp3_opp_table>;
4929 #sound-dai-cells = <0>;
4934 #address-cells = <1>;
4935 #size-cells = <0>;
4940 remote-endpoint = <&mdss1_intf5_out>;
4949 mdss1_dp3_opp_table: opp-table {
4950 compatible = "operating-points-v2";
4952 opp-160000000 {
4953 opp-hz = /bits/ 64 <160000000>;
4954 required-opps = <&rpmhpd_opp_low_svs>;
4957 opp-270000000 {
4958 opp-hz = /bits/ 64 <270000000>;
4959 required-opps = <&rpmhpd_opp_svs>;
4962 opp-540000000 {
4963 opp-hz = /bits/ 64 <540000000>;
4964 required-opps = <&rpmhpd_opp_svs_l1>;
4967 opp-810000000 {
4968 opp-hz = /bits/ 64 <810000000>;
4969 required-opps = <&rpmhpd_opp_nom>;
4976 compatible = "qcom,sc8280xp-dp-phy";
4984 clock-names = "aux", "cfg_ahb";
4985 power-domains = <&rpmhpd SC8280XP_MX>;
4987 #clock-cells = <1>;
4988 #phy-cells = <0>;
4994 compatible = "qcom,sc8280xp-dp-phy";
5002 clock-names = "aux", "cfg_ahb";
5003 power-domains = <&rpmhpd SC8280XP_MX>;
5005 #clock-cells = <1>;
5006 #phy-cells = <0>;
5011 dispcc1: clock-controller@22100000 {
5012 compatible = "qcom,sc8280xp-dispcc1";
5030 power-domains = <&rpmhpd SC8280XP_MMCX>;
5032 #clock-cells = <1>;
5033 #power-domain-cells = <1>;
5034 #reset-cells = <1>;
5040 compatible = "qcom,sc8280xp-ethqos";
5043 reg-names = "stmmaceth", "rgmii";
5049 clock-names = "stmmaceth",
5056 interrupt-names = "macirq", "eth_lpi";
5059 power-domains = <&gcc EMAC_1_GDSC>;
5063 rx-fifo-depth = <4096>;
5064 tx-fifo-depth = <4096>;
5073 thermal-zones {
5074 cpu0-thermal {
5075 polling-delay-passive = <250>;
5076 polling-delay = <1000>;
5078 thermal-sensors = <&tsens0 1>;
5081 cpu-crit {
5089 cpu1-thermal {
5090 polling-delay-passive = <250>;
5091 polling-delay = <1000>;
5093 thermal-sensors = <&tsens0 2>;
5096 cpu-crit {
5104 cpu2-thermal {
5105 polling-delay-passive = <250>;
5106 polling-delay = <1000>;
5108 thermal-sensors = <&tsens0 3>;
5111 cpu-crit {
5119 cpu3-thermal {
5120 polling-delay-passive = <250>;
5121 polling-delay = <1000>;
5123 thermal-sensors = <&tsens0 4>;
5126 cpu-crit {
5134 cpu4-thermal {
5135 polling-delay-passive = <250>;
5136 polling-delay = <1000>;
5138 thermal-sensors = <&tsens0 5>;
5141 cpu-crit {
5149 cpu5-thermal {
5150 polling-delay-passive = <250>;
5151 polling-delay = <1000>;
5153 thermal-sensors = <&tsens0 6>;
5156 cpu-crit {
5164 cpu6-thermal {
5165 polling-delay-passive = <250>;
5166 polling-delay = <1000>;
5168 thermal-sensors = <&tsens0 7>;
5171 cpu-crit {
5179 cpu7-thermal {
5180 polling-delay-passive = <250>;
5181 polling-delay = <1000>;
5183 thermal-sensors = <&tsens0 8>;
5186 cpu-crit {
5194 cluster0-thermal {
5195 polling-delay-passive = <250>;
5196 polling-delay = <1000>;
5198 thermal-sensors = <&tsens0 9>;
5201 cpu-crit {
5209 mem-thermal {
5210 polling-delay-passive = <250>;
5211 polling-delay = <1000>;
5213 thermal-sensors = <&tsens1 15>;
5216 trip-point0 {
5226 compatible = "arm,armv8-timer";