dts/qcom/sc8280xp.dtsi

143 			clocks = <&cpufreq_hw 1>;
149 			qcom,freq-domain = <&cpufreq_hw 1>;
165 			clocks = <&cpufreq_hw 1>;
171 			qcom,freq-domain = <&cpufreq_hw 1>;
187 			clocks = <&cpufreq_hw 1>;
193 			qcom,freq-domain = <&cpufreq_hw 1>;
209 			clocks = <&cpufreq_hw 1>;
215 			qcom,freq-domain = <&cpufreq_hw 1>;
276 			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
718 			#qcom,smem-state-cells = <1>;
742 			#qcom,smem-state-cells = <1>;
766 			#qcom,smem-state-cells = <1>;
816 			#clock-cells = <1>;
817 			#reset-cells = <1>;
818 			#power-domain-cells = <1>;
881 				#address-cells = <1>;
897 				#address-cells = <1>;
913 				#address-cells = <1>;
929 				#address-cells = <1>;
959 				#address-cells = <1>;
975 				#address-cells = <1>;
991 				#address-cells = <1>;
1007 				#address-cells = <1>;
1023 				#address-cells = <1>;
1039 				#address-cells = <1>;
1058 				#address-cells = <1>;
1071 				#address-cells = <1>;
1087 				#address-cells = <1>;
1103 				#address-cells = <1>;
1119 				#address-cells = <1>;
1135 				#address-cells = <1>;
1166 				#address-cells = <1>;
1182 				#address-cells = <1>;
1198 				#address-cells = <1>;
1214 				#address-cells = <1>;
1230 				#address-cells = <1>;
1246 				#address-cells = <1>;
1276 				#address-cells = <1>;
1292 				#address-cells = <1>;
1311 				#address-cells = <1>;
1324 				#address-cells = <1>;
1340 				#address-cells = <1>;
1356 				#address-cells = <1>;
1372 				#address-cells = <1>;
1388 				#address-cells = <1>;
1404 				#address-cells = <1>;
1420 				#address-cells = <1>;
1451 				#address-cells = <1>;
1467 				#address-cells = <1>;
1483 				#address-cells = <1>;
1499 				#address-cells = <1>;
1515 				#address-cells = <1>;
1531 				#address-cells = <1>;
1547 				#address-cells = <1>;
1563 				#address-cells = <1>;
1579 				#address-cells = <1>;
1595 				#address-cells = <1>;
1611 				#address-cells = <1>;
1627 				#address-cells = <1>;
1643 				#address-cells = <1>;
1659 				#address-cells = <1>;
1675 				#address-cells = <1>;
1691 				#address-cells = <1>;
1712 		pcie4: pcie@1c00000 {
1731 			num-lanes = <1>;
1739 			#interrupt-cells = <1>;
1741 			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1784 		pcie4_phy: phy@1c06000 {
1814 		pcie3b: pcie@1c08000 {
1841 			#interrupt-cells = <1>;
1843 			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1884 		pcie3b_phy: phy@1c0e000 {
1914 		pcie3a: pcie@1c10000 {
1941 			#interrupt-cells = <1>;
1943 			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1984 		pcie3a_phy: phy@1c14000 {
2007 			qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2017 		pcie2b: pcie@1c18000 {
2044 			#interrupt-cells = <1>;
2046 			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2087 		pcie2b_phy: phy@1c1e000 {
2117 		pcie2a: pcie@1c20000 {
2144 			#interrupt-cells = <1>;
2146 			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2187 		pcie2a_phy: phy@1c24000 {
2220 		ufs_mem_hc: ufs@1d84000 {
2228 			#reset-cells = <1>;
2265 		ufs_mem_phy: phy@1d87000 {
2283 		ufs_card_hc: ufs@1da4000 {
2291 			#reset-cells = <1>;
2327 		ufs_card_phy: phy@1da7000 {
2345 		tcsr_mutex: hwlock@1f40000 {
2348 			#hwlock-cells = <1>;
2351 		tcsr: syscon@1fc0000 {
2366 			iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
2485 			#clock-cells = <1>;
2486 			#reset-cells = <1>;
2487 			#power-domain-cells = <1>;
2649 					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2687 					#address-cells = <1>;
2690 					q6apm: service@1 {
2703 							#sound-dai-cells = <1>;
2736 			#sound-dai-cells = <1>;
2767 			#sound-dai-cells = <1>;
2792 			#sound-dai-cells = <1>;
2812 			#sound-dai-cells = <1>;
2843 			#sound-dai-cells = <1>;
2853 			#clock-cells = <1>;
2854 			#reset-cells = <1>;
2869 			#sound-dai-cells = <1>;
2901 			#sound-dai-cells = <1>;
2925 					slew-rate = <1>;
2933 					slew-rate = <1>;
2943 					slew-rate = <1>;
2951 					slew-rate = <1>;
3029 					slew-rate = <1>;
3037 					slew-rate = <1>;
3047 					slew-rate = <1>;
3055 					slew-rate = <1>;
3064 			#clock-cells = <1>;
3065 			#reset-cells = <1>;
3127 			#clock-cells = <1>;
3128 			#phy-cells = <1>;
3133 				#address-cells = <1>;
3180 			#clock-cells = <1>;
3181 			#phy-cells = <1>;
3186 				#address-cells = <1>;
3215 			#clock-cells = <1>;
3233 			#clock-cells = <1>;
3255 				opp-1 {
3309 				opp-1 {
3483 			#interrupt-cells = <1>;
3517 					#address-cells = <1>;
3613 					#address-cells = <1>;
3624 					port@1 {
3625 						reg = <1>;
3691 					#address-cells = <1>;
3702 					port@1 {
3703 						reg = <1>;
3759 				assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
3767 					#address-cells = <1>;
3777 					port@1 {
3778 						reg = <1>;
3831 				assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
3839 					#address-cells = <1>;
3849 					port@1 {
3850 						reg = <1>;
3892 			#clock-cells = <1>;
3910 			#clock-cells = <1>;
3928 				 <&mdss0_dp2_phy 1>,
3930 				 <&mdss0_dp3_phy 1>,
3937 			#clock-cells = <1>;
3938 			#power-domain-cells = <1>;
3939 			#reset-cells = <1>;
3949 					  <54 263 1>,
3955 					  <69 86 1>,
3958 					  <159 638 1>,
3960 					  <168 801 1>,
3963 					  <201 449 1>,
3964 					  <202 89 1>,
3965 					  <203 451 1>,
3966 					  <204 462 1>,
3967 					  <205 264 1>,
3968 					  <206 579 1>,
3969 					  <207 653 1>,
3970 					  <208 656 1>,
3971 					  <209 659 1>,
3972 					  <210 122 1>,
3973 					  <211 699 1>,
3974 					  <212 705 1>,
3975 					  <213 450 1>,
3976 					  <214 643 1>,
3981 					  <232 269 1>,
3982 					  <233 377 1>,
3983 					  <234 372 1>,
3984 					  <235 138 1>,
3985 					  <236 857 1>,
3986 					  <237 860 1>,
3987 					  <238 137 1>,
3988 					  <239 668 1>,
3989 					  <240 366 1>,
3990 					  <241 949 1>,
3992 					  <247 769 1>,
3993 					  <248 768 1>,
3994 					  <249 663 1>,
3996 					  <252 798 1>,
3997 					  <253 765 1>,
3998 					  <254 763 1>,
3999 					  <255 454 1>,
4000 					  <258 139 1>,
4017 			#thermal-sensor-cells = <1>;
4028 			#thermal-sensor-cells = <1>;
4054 			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4219 			#redistributor-regions = <1>;
4230 				#msi-cells = <1>;
4244 			#address-cells = <1>;
4245 			#size-cells = <1>;
4257 				frame-number = <1>;
4263 			frame@17c25000 {
4304 			reg-names = "drv-0", "drv-1", "drv-2";
4311 					  <WAKE_TCS    3>, <CONTROL_TCS 1>;
4321 				#clock-cells = <1>;
4328 				#power-domain-cells = <1>;
4384 			#interconnect-cells = <1>;
4396 			#freq-domain-cells = <1>;
4397 			#clock-cells = <1>;
4400 		remoteproc_nsp0: remoteproc@1b300000 {
4406 					      <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
4441 					#address-cells = <1>;
4444 					compute-cb@1 {
4446 						reg = <1>;
4537 					      <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
4591 			#interrupt-cells = <1>;
4625 					#address-cells = <1>;
4710 				assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
4718 					#address-cells = <1>;
4728 					port@1 {
4729 						reg = <1>;
4782 				assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
4790 					#address-cells = <1>;
4800 					port@1 {
4801 						reg = <1>;
4854 				assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
4862 					#address-cells = <1>;
4872 					port@1 {
4873 						reg = <1>;
4926 				assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
4934 					#address-cells = <1>;
4944 					port@1 {
4945 						reg = <1>;
4987 			#clock-cells = <1>;
5005 			#clock-cells = <1>;
5019 				 <&mdss1_dp0_phy 1>,
5021 				 <&mdss1_dp1_phy 1>,
5023 				 <&mdss1_dp2_phy 1>,
5025 				 <&mdss1_dp3_phy 1>,
5032 			#clock-cells = <1>;
5033 			#power-domain-cells = <1>;
5034 			#reset-cells = <1>;
5078 			thermal-sensors = <&tsens0 1>;