Lines Matching +full:0 +full:x0aec2000
32 #clock-cells = <0>;
37 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x100>;
77 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0x0 0x200>;
99 clocks = <&cpufreq_hw 0>;
105 qcom,freq-domain = <&cpufreq_hw 0>;
120 reg = <0x0 0x300>;
121 clocks = <&cpufreq_hw 0>;
127 qcom,freq-domain = <&cpufreq_hw 0>;
142 reg = <0x0 0x400>;
164 reg = <0x0 0x500>;
186 reg = <0x0 0x600>;
208 reg = <0x0 0x700>;
266 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
269 arm,psci-suspend-param = <0x40000004>;
276 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
279 arm,psci-suspend-param = <0x40000004>;
288 CLUSTER_SLEEP_0: cluster-sleep-0 {
290 arm,psci-suspend-param = <0x4100c344>;
301 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
380 reg = <0x0 0x80000000 0x0 0x0>;
587 #power-domain-cells = <0>;
593 #power-domain-cells = <0>;
599 #power-domain-cells = <0>;
605 #power-domain-cells = <0>;
611 #power-domain-cells = <0>;
617 #power-domain-cells = <0>;
623 #power-domain-cells = <0>;
629 #power-domain-cells = <0>;
635 #power-domain-cells = <0>;
646 reg = <0 0x80000000 0 0x860000>;
652 reg = <0 0x80860000 0 0x20000>;
657 reg = <0 0x80880000 0 0x80000>;
663 reg = <0 0x80900000 0 0x200000>;
669 reg = <0 0x80b00000 0 0x100000>;
674 reg = <0 0x83b00000 0 0x1700000>;
679 reg = <0 0x85b00000 0 0xc00000>;
684 reg = <0 0x86c00000 0 0x2000000>;
689 reg = <0 0x8a100000 0 0x1e00000>;
694 reg = <0 0x8c600000 0 0x1e00000>;
699 reg = <0 0xaeb00000 0 0x16600000>;
713 qcom,local-pid = <0>;
737 qcom,local-pid = <0>;
761 qcom,local-pid = <0>;
776 soc: soc@0 {
780 ranges = <0 0 0 0 0x10 0>;
781 dma-ranges = <0 0 0 0 0x10 0>;
785 reg = <0x0 0x00020000 0x0 0x10000>,
786 <0x0 0x00036000 0x0 0x100>;
802 iommus = <&apps_smmu 0x4c0 0xf>;
815 reg = <0x0 0x00100000 0x0 0x1f0000>;
821 <0>,
822 <0>,
823 <0>,
824 <0>,
825 <0>,
826 <0>,
828 <0>,
829 <0>,
830 <0>,
831 <0>,
832 <0>,
833 <0>,
834 <0>,
836 <0>,
837 <0>,
838 <0>,
839 <0>,
840 <0>,
841 <0>,
842 <0>,
843 <0>,
844 <0>,
850 <0>,
851 <0>;
857 reg = <0 0x00408000 0 0x1000>;
866 reg = <0 0x008c0000 0 0x2000>;
870 iommus = <&apps_smmu 0xa3 0>;
880 reg = <0 0x00880000 0 0x4000>;
882 #size-cells = <0>;
887 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
888 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
889 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
896 reg = <0 0x00880000 0 0x4000>;
898 #size-cells = <0>;
903 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
904 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
905 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
912 reg = <0 0x00884000 0 0x4000>;
914 #size-cells = <0>;
919 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
920 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
921 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
928 reg = <0 0x00884000 0 0x4000>;
930 #size-cells = <0>;
935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
937 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
944 reg = <0 0x00884000 0 0x4000>;
950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
958 reg = <0 0x00888000 0 0x4000>;
960 #size-cells = <0>;
965 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
966 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
967 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
974 reg = <0 0x00888000 0 0x4000>;
976 #size-cells = <0>;
981 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
982 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
983 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
990 reg = <0 0x0088c000 0 0x4000>;
992 #size-cells = <0>;
997 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
998 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
999 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1006 reg = <0 0x0088c000 0 0x4000>;
1008 #size-cells = <0>;
1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1015 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1022 reg = <0 0x00890000 0 0x4000>;
1024 #size-cells = <0>;
1029 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1030 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1031 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1038 reg = <0 0x00890000 0 0x4000>;
1040 #size-cells = <0>;
1045 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1047 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1054 reg = <0 0x00894000 0 0x4000>;
1059 #size-cells = <0>;
1061 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1062 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1063 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1070 reg = <0 0x00894000 0 0x4000>;
1072 #size-cells = <0>;
1077 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1078 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1079 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1086 reg = <0 0x00898000 0 0x4000>;
1088 #size-cells = <0>;
1093 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1094 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1095 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1102 reg = <0 0x00898000 0 0x4000>;
1104 #size-cells = <0>;
1109 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1110 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1111 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1118 reg = <0 0x0089c000 0 0x4000>;
1120 #size-cells = <0>;
1125 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1126 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1127 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1134 reg = <0 0x0089c000 0 0x4000>;
1136 #size-cells = <0>;
1141 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1142 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1143 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1151 reg = <0 0x009c0000 0 0x6000>;
1155 iommus = <&apps_smmu 0x563 0>;
1165 reg = <0 0x00980000 0 0x4000>;
1167 #size-cells = <0>;
1172 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1173 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1174 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1181 reg = <0 0x00980000 0 0x4000>;
1183 #size-cells = <0>;
1188 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1189 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1190 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1197 reg = <0 0x00984000 0 0x4000>;
1199 #size-cells = <0>;
1204 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1205 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1206 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1213 reg = <0 0x00984000 0 0x4000>;
1215 #size-cells = <0>;
1220 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1222 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1229 reg = <0 0x00988000 0 0x4000>;
1231 #size-cells = <0>;
1236 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1238 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1245 reg = <0 0x00988000 0 0x4000>;
1247 #size-cells = <0>;
1252 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1253 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1254 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1261 reg = <0 0x00988000 0 0x4000>;
1267 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1268 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1275 reg = <0 0x0098c000 0 0x4000>;
1277 #size-cells = <0>;
1282 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1283 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1284 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1291 reg = <0 0x0098c000 0 0x4000>;
1293 #size-cells = <0>;
1298 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1299 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1300 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1307 reg = <0 0x00990000 0 0x4000>;
1312 #size-cells = <0>;
1314 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1315 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1316 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1323 reg = <0 0x00990000 0 0x4000>;
1325 #size-cells = <0>;
1330 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1331 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1332 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1339 reg = <0 0x00994000 0 0x4000>;
1341 #size-cells = <0>;
1346 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1347 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1348 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1355 reg = <0 0x00994000 0 0x4000>;
1357 #size-cells = <0>;
1362 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1363 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1364 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 reg = <0 0x00998000 0 0x4000>;
1373 #size-cells = <0>;
1378 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1379 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1380 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1387 reg = <0 0x00998000 0 0x4000>;
1389 #size-cells = <0>;
1394 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1395 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1396 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1403 reg = <0 0x0099c000 0 0x4000>;
1405 #size-cells = <0>;
1410 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1411 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1412 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1419 reg = <0 0x0099c000 0 0x4000>;
1421 #size-cells = <0>;
1426 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1427 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1428 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1436 reg = <0 0x00ac0000 0 0x6000>;
1440 iommus = <&apps_smmu 0x83 0>;
1450 reg = <0 0x00a80000 0 0x4000>;
1452 #size-cells = <0>;
1457 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1458 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1459 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1466 reg = <0 0x00a80000 0 0x4000>;
1468 #size-cells = <0>;
1473 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1474 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1475 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1482 reg = <0 0x00a84000 0 0x4000>;
1484 #size-cells = <0>;
1489 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1490 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1491 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1498 reg = <0 0x00a84000 0 0x4000>;
1500 #size-cells = <0>;
1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1506 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1507 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1514 reg = <0 0x00a88000 0 0x4000>;
1516 #size-cells = <0>;
1521 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1522 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1523 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1530 reg = <0 0x00a88000 0 0x4000>;
1532 #size-cells = <0>;
1537 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1538 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1539 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 reg = <0 0x00a8c000 0 0x4000>;
1548 #size-cells = <0>;
1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1554 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1555 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1562 reg = <0 0x00a8c000 0 0x4000>;
1564 #size-cells = <0>;
1569 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1570 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1571 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1578 reg = <0 0x00a90000 0 0x4000>;
1580 #size-cells = <0>;
1585 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1586 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1587 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1594 reg = <0 0x00a90000 0 0x4000>;
1596 #size-cells = <0>;
1601 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1602 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1603 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1610 reg = <0 0x00a94000 0 0x4000>;
1612 #size-cells = <0>;
1617 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1618 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1619 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 reg = <0 0x00a94000 0 0x4000>;
1628 #size-cells = <0>;
1633 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1634 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1635 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1642 reg = <0 0x00a98000 0 0x4000>;
1644 #size-cells = <0>;
1649 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1650 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1651 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1658 reg = <0 0x00a98000 0 0x4000>;
1660 #size-cells = <0>;
1665 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1666 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1667 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1674 reg = <0 0x00a9c000 0 0x4000>;
1676 #size-cells = <0>;
1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1682 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1683 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1690 reg = <0 0x00a9c000 0 0x4000>;
1692 #size-cells = <0>;
1697 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1698 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1699 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1707 reg = <0 0x010d3000 0 0x1000>;
1715 reg = <0x0 0x01c00000 0x0 0x3000>,
1716 <0x0 0x30000000 0x0 0xf1d>,
1717 <0x0 0x30000f20 0x0 0xa8>,
1718 <0x0 0x30001000 0x0 0x1000>,
1719 <0x0 0x30100000 0x0 0x100000>,
1720 <0x0 0x01c03000 0x0 0x1000>;
1724 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
1725 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
1726 bus-range = <0x00 0xff>;
1740 interrupt-map-mask = <0 0 0 0x7>;
1741 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1742 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1743 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1744 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1768 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
1769 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
1786 reg = <0x0 0x01c06000 0x0 0x2000>;
1806 #clock-cells = <0>;
1809 #phy-cells = <0>;
1817 reg = <0x0 0x01c08000 0x0 0x3000>,
1818 <0x0 0x32000000 0x0 0xf1d>,
1819 <0x0 0x32000f20 0x0 0xa8>,
1820 <0x0 0x32001000 0x0 0x1000>,
1821 <0x0 0x32100000 0x0 0x100000>,
1822 <0x0 0x01c0b000 0x0 0x1000>;
1826 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
1827 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1828 bus-range = <0x00 0xff>;
1842 interrupt-map-mask = <0 0 0 0x7>;
1843 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1844 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1845 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1846 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1868 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1869 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1886 reg = <0x0 0x01c0e000 0x0 0x2000>;
1906 #clock-cells = <0>;
1909 #phy-cells = <0>;
1917 reg = <0x0 0x01c10000 0x0 0x3000>,
1918 <0x0 0x34000000 0x0 0xf1d>,
1919 <0x0 0x34000f20 0x0 0xa8>,
1920 <0x0 0x34001000 0x0 0x1000>,
1921 <0x0 0x34100000 0x0 0x100000>,
1922 <0x0 0x01c13000 0x0 0x1000>;
1926 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
1927 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1928 bus-range = <0x00 0xff>;
1942 interrupt-map-mask = <0 0 0 0x7>;
1943 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1944 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1945 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1946 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
1968 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
1969 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
1986 reg = <0x0 0x01c14000 0x0 0x2000>,
1987 <0x0 0x01c16000 0x0 0x2000>;
2007 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2009 #clock-cells = <0>;
2012 #phy-cells = <0>;
2020 reg = <0x0 0x01c18000 0x0 0x3000>,
2021 <0x0 0x38000000 0x0 0xf1d>,
2022 <0x0 0x38000f20 0x0 0xa8>,
2023 <0x0 0x38001000 0x0 0x1000>,
2024 <0x0 0x38100000 0x0 0x100000>,
2025 <0x0 0x01c1b000 0x0 0x1000>;
2029 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
2030 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
2031 bus-range = <0x00 0xff>;
2045 interrupt-map-mask = <0 0 0 0x7>;
2046 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2047 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2048 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2049 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
2071 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
2072 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
2089 reg = <0x0 0x01c1e000 0x0 0x2000>;
2109 #clock-cells = <0>;
2112 #phy-cells = <0>;
2120 reg = <0x0 0x01c20000 0x0 0x3000>,
2121 <0x0 0x3c000000 0x0 0xf1d>,
2122 <0x0 0x3c000f20 0x0 0xa8>,
2123 <0x0 0x3c001000 0x0 0x1000>,
2124 <0x0 0x3c100000 0x0 0x100000>,
2125 <0x0 0x01c23000 0x0 0x1000>;
2129 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
2130 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
2131 bus-range = <0x00 0xff>;
2145 interrupt-map-mask = <0 0 0 0x7>;
2146 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2147 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
2148 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
2149 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
2171 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
2172 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
2189 reg = <0x0 0x01c24000 0x0 0x2000>,
2190 <0x0 0x01c26000 0x0 0x2000>;
2210 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2212 #clock-cells = <0>;
2215 #phy-cells = <0>;
2223 reg = <0 0x01d84000 0 0x3000>;
2235 iommus = <&apps_smmu 0xe0 0x0>;
2255 <0 0>,
2256 <0 0>,
2258 <0 0>,
2259 <0 0>,
2260 <0 0>,
2261 <0 0>;
2267 reg = <0 0x01d87000 0 0x1000>;
2275 resets = <&ufs_mem_hc 0>;
2278 #phy-cells = <0>;
2286 reg = <0 0x01da4000 0 0x3000>;
2297 iommus = <&apps_smmu 0x4a0 0x0>;
2317 <0 0>,
2318 <0 0>,
2320 <0 0>,
2321 <0 0>,
2322 <0 0>,
2323 <0 0>;
2329 reg = <0 0x01da7000 0 0x1000>;
2337 resets = <&ufs_card_hc 0>;
2340 #phy-cells = <0>;
2347 reg = <0x0 0x01f40000 0x0 0x20000>;
2353 reg = <0x0 0x01fc0000 0x0 0x30000>;
2359 reg = <0 0x03d00000 0 0x40000>,
2360 <0 0x03d9e000 0 0x1000>,
2361 <0 0x03d61000 0 0x800>;
2366 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
2370 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2431 reg = <0 0x03d6a000 0 0x34000>,
2432 <0 0x03de0000 0 0x10000>,
2433 <0 0x0b290000 0 0x10000>;
2456 iommus = <&gpu_smmu 5 0xc00>;
2476 reg = <0 0x03d90000 0 0x9000>;
2493 reg = <0 0x03da0000 0 0x20000>;
2533 reg = <0 0x088e5000 0 0x400>;
2538 #phy-cells = <0>;
2546 reg = <0 0x088e7000 0 0x400>;
2551 #phy-cells = <0>;
2559 reg = <0 0x088e8000 0 0x400>;
2564 #phy-cells = <0>;
2572 reg = <0 0x088e9000 0 0x400>;
2577 #phy-cells = <0>;
2585 reg = <0 0x088ea000 0 0x400>;
2590 #phy-cells = <0>;
2597 reg = <0 0x088ef000 0 0x2000>;
2611 #clock-cells = <0>;
2614 #phy-cells = <0>;
2621 reg = <0 0x088f1000 0 0x2000>;
2635 #clock-cells = <0>;
2638 #phy-cells = <0>;
2645 reg = <0 0x03000000 0 0x100>;
2648 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2667 qcom,smem-states = <&smp2p_adsp_out 0>;
2688 #size-cells = <0>;
2693 #sound-dai-cells = <0>;
2698 iommus = <&apps_smmu 0x0c01 0x0>;
2723 reg = <0 0x03200000 0 0x1000>;
2735 #clock-cells = <0>;
2739 pinctrl-0 = <&rx_swr_default>;
2746 reg = <0 0x03210000 0 0x2000>;
2754 qcom,din-ports = <0>;
2757 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2758 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2759 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2760 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2761 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2762 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2763 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2764 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2765 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2769 #size-cells = <0>;
2776 reg = <0 0x03220000 0 0x1000>;
2778 pinctrl-0 = <&tx_swr_default>;
2791 #clock-cells = <0>;
2799 reg = <0 0x03240000 0 0x1000>;
2810 #clock-cells = <0>;
2815 pinctrl-0 = <&wsa_swr_default>;
2821 reg = <0 0x03250000 0 0x2000>;
2833 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2834 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2835 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2836 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2837 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2838 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2839 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2840 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2841 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2845 #size-cells = <0>;
2852 reg = <0 0x032a9000 0 0x1000>;
2859 reg = <0 0x03330000 0 0x2000>;
2871 #size-cells = <0>;
2874 qcom,dout-ports = <0>;
2875 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2876 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2877 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2878 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2879 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2880 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2881 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2882 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2883 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2890 reg = <0 0x03370000 0 0x1000>;
2899 #clock-cells = <0>;
2908 reg = <0 0x33c0000 0x0 0x20000>,
2909 <0 0x3550000 0x0 0x10000>;
2912 gpio-ranges = <&lpass_tlmm 0 0 19>;
3063 reg = <0 0x033e0000 0 0x12000>;
3070 reg = <0 0x08804000 0 0x1000>;
3081 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3082 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
3084 iommus = <&apps_smmu 0x4e0 0x0>;
3099 opp-avg-kBps = <100000 0>;
3106 opp-avg-kBps = <200000 0>;
3113 reg = <0 0x088eb000 0 0x4000>;
3134 #size-cells = <0>;
3136 port@0 {
3137 reg = <0>;
3153 reg = <0 0x08902000 0 0x400>;
3154 #phy-cells = <0>;
3166 reg = <0 0x08903000 0 0x4000>;
3187 #size-cells = <0>;
3189 port@0 {
3190 reg = <0>;
3205 reg = <0 0x08909a00 0 0x19c>,
3206 <0 0x08909200 0 0xec>,
3207 <0 0x08909600 0 0xec>,
3208 <0 0x08909000 0 0x1c8>;
3216 #phy-cells = <0>;
3223 reg = <0 0x0890ca00 0 0x19c>,
3224 <0 0x0890c200 0 0xec>,
3225 <0 0x0890c600 0 0xec>,
3226 <0 0x0890c000 0 0x1c8>;
3234 #phy-cells = <0>;
3241 reg = <0 0x09091000 0 0x1000>;
3252 opp-0 {
3296 reg = <0 0x090b6400 0 0x600>;
3306 opp-0 {
3332 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3333 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
3334 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
3335 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
3336 <0 0x09600000 0 0x58000>;
3345 reg = <0 0x0a6f8800 0 0x400>;
3380 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3381 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3390 reg = <0 0x0a600000 0 0xcd00>;
3392 iommus = <&apps_smmu 0x820 0x0>;
3405 reg = <0 0x0a8f8800 0 0x400>;
3440 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3441 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3450 reg = <0 0x0a800000 0 0xcd00>;
3452 iommus = <&apps_smmu 0x860 0x0>;
3465 reg = <0 0x0ae00000 0 0x1000>;
3475 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
3476 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
3478 iommus = <&apps_smmu 0x1000 0x402>;
3492 reg = <0 0x0ae01000 0 0x8f000>,
3493 <0 0x0aeb0000 0 0x2008>;
3509 interrupts = <0>;
3518 #size-cells = <0>;
3520 port@0 {
3521 reg = <0>;
3580 reg = <0 0xae90000 0 0x200>,
3581 <0 0xae90200 0 0x200>,
3582 <0 0xae90400 0 0x600>,
3583 <0 0xae91000 0 0x400>,
3584 <0 0xae91400 0 0x400>;
3605 #sound-dai-cells = <0>;
3614 #size-cells = <0>;
3616 port@0 {
3617 reg = <0>;
3659 reg = <0 0xae98000 0 0x200>,
3660 <0 0xae98200 0 0x200>,
3661 <0 0xae98400 0 0x600>,
3662 <0 0xae99000 0 0x400>,
3663 <0 0xae99400 0 0x400>;
3683 #sound-dai-cells = <0>;
3692 #size-cells = <0>;
3694 port@0 {
3695 reg = <0>;
3737 reg = <0 0xae9a000 0 0x200>,
3738 <0 0xae9a200 0 0x200>,
3739 <0 0xae9a400 0 0x600>,
3740 <0 0xae9b000 0 0x400>,
3741 <0 0xae9b400 0 0x400>;
3759 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
3762 #sound-dai-cells = <0>;
3768 #size-cells = <0>;
3770 port@0 {
3771 reg = <0>;
3809 reg = <0 0xaea0000 0 0x200>,
3810 <0 0xaea0200 0 0x200>,
3811 <0 0xaea0400 0 0x600>,
3812 <0 0xaea1000 0 0x400>,
3813 <0 0xaea1400 0 0x400>;
3831 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
3834 #sound-dai-cells = <0>;
3840 #size-cells = <0>;
3842 port@0 {
3843 reg = <0>;
3882 reg = <0 0x0aec2a00 0 0x19c>,
3883 <0 0x0aec2200 0 0xec>,
3884 <0 0x0aec2600 0 0xec>,
3885 <0 0x0aec2000 0 0x1c8>;
3893 #phy-cells = <0>;
3900 reg = <0 0x0aec5a00 0 0x19c>,
3901 <0 0x0aec5200 0 0xec>,
3902 <0 0x0aec5600 0 0xec>,
3903 <0 0x0aec5000 0 0x1c8>;
3911 #phy-cells = <0>;
3918 reg = <0 0x0af00000 0 0x20000>;
3927 <&mdss0_dp2_phy 0>,
3929 <&mdss0_dp3_phy 0>,
3931 <0>,
3932 <0>,
3933 <0>,
3934 <0>;
3946 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
3947 qcom,pdc-ranges = <0 480 40>,
4011 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4012 <0 0x0c222000 0 0x8>; /* SROT */
4022 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4023 <0 0x0c223000 0 0x8>; /* SROT */
4033 reg = <0 0x0c300000 0 0x400>;
4037 #clock-cells = <0>;
4042 reg = <0 0x0c3f0000 0 0x400>;
4047 reg = <0 0x0c440000 0 0x1100>,
4048 <0 0x0c600000 0 0x2000000>,
4049 <0 0x0e600000 0 0x100000>,
4050 <0 0x0e700000 0 0xa0000>,
4051 <0 0x0c40a000 0 0x26000>;
4055 qcom,ee = <0>;
4056 qcom,channel = <0>;
4058 #size-cells = <0>;
4065 reg = <0 0x0f100000 0 0x300000>;
4071 gpio-ranges = <&tlmm 0 0 230>;
4077 reg = <0 0x15000000 0 0x100000>;
4216 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4217 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4220 redistributor-stride = <0 0x20000>;
4228 reg = <0 0x17a40000 0 0x20000>;
4236 reg = <0 0x17c10000 0 0x1000>;
4238 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4243 reg = <0x0 0x17c20000 0x0 0x1000>;
4246 ranges = <0x0 0x0 0x0 0x20000000>;
4249 frame-number = <0>;
4252 reg = <0x17c21000 0x1000>,
4253 <0x17c22000 0x1000>;
4259 reg = <0x17c23000 0x1000>;
4266 reg = <0x17c25000 0x1000>;
4273 reg = <0x17c26000 0x1000>;
4280 reg = <0x17c29000 0x1000>;
4287 reg = <0x17c2b000 0x1000>;
4294 reg = <0x17c2d000 0x1000>;
4301 reg = <0x0 0x18200000 0x0 0x10000>,
4302 <0x0 0x18210000 0x0 0x10000>,
4303 <0x0 0x18220000 0x0 0x10000>;
4304 reg-names = "drv-0", "drv-1", "drv-2";
4308 qcom,tcs-offset = <0xd00>;
4379 reg = <0 0x18590000 0 0x1000>;
4389 reg = <0 0x18591000 0 0x1000>,
4390 <0 0x18592000 0 0x1000>;
4402 reg = <0 0x1b300000 0 0x100>;
4405 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
4420 qcom,smem-states = <&smp2p_nsp0_out 0>;
4423 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4442 #size-cells = <0>;
4447 iommus = <&apps_smmu 0x3181 0x0420>;
4453 iommus = <&apps_smmu 0x3182 0x0420>;
4459 iommus = <&apps_smmu 0x3183 0x0420>;
4465 iommus = <&apps_smmu 0x3184 0x0420>;
4471 iommus = <&apps_smmu 0x3185 0x0420>;
4477 iommus = <&apps_smmu 0x3186 0x0420>;
4483 iommus = <&apps_smmu 0x3187 0x0420>;
4489 iommus = <&apps_smmu 0x3188 0x0420>;
4495 iommus = <&apps_smmu 0x318b 0x0420>;
4501 iommus = <&apps_smmu 0x318b 0x0420>;
4507 iommus = <&apps_smmu 0x318c 0x0420>;
4513 iommus = <&apps_smmu 0x318d 0x0420>;
4519 iommus = <&apps_smmu 0x318e 0x0420>;
4525 iommus = <&apps_smmu 0x318f 0x0420>;
4533 reg = <0 0x21300000 0 0x100>;
4536 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
4551 qcom,smem-states = <&smp2p_nsp1_out 0>;
4554 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
4572 reg = <0 0x22000000 0 0x1000>;
4581 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
4582 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
4586 iommus = <&apps_smmu 0x1800 0x402>;
4600 reg = <0 0x22001000 0 0x8f000>,
4601 <0 0x220b0000 0 0x2008>;
4617 interrupts = <0>;
4626 #size-cells = <0>;
4628 port@0 {
4629 reg = <0>;
4688 reg = <0 0x22090000 0 0x200>,
4689 <0 0x22090200 0 0x200>,
4690 <0 0x22090400 0 0x600>,
4691 <0 0x22091000 0 0x400>,
4692 <0 0x22091400 0 0x400>;
4710 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
4713 #sound-dai-cells = <0>;
4719 #size-cells = <0>;
4721 port@0 {
4722 reg = <0>;
4760 reg = <0 0x22098000 0 0x200>,
4761 <0 0x22098200 0 0x200>,
4762 <0 0x22098400 0 0x600>,
4763 <0 0x22099000 0 0x400>,
4764 <0 0x22099400 0 0x400>;
4782 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
4785 #sound-dai-cells = <0>;
4791 #size-cells = <0>;
4793 port@0 {
4794 reg = <0>;
4832 reg = <0 0x2209a000 0 0x200>,
4833 <0 0x2209a200 0 0x200>,
4834 <0 0x2209a400 0 0x600>,
4835 <0 0x2209b000 0 0x400>,
4836 <0 0x2209b400 0 0x400>;
4854 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
4857 #sound-dai-cells = <0>;
4863 #size-cells = <0>;
4865 port@0 {
4866 reg = <0>;
4904 reg = <0 0x220a0000 0 0x200>,
4905 <0 0x220a0200 0 0x200>,
4906 <0 0x220a0400 0 0x600>,
4907 <0 0x220a1000 0 0x400>,
4908 <0 0x220a1400 0 0x400>;
4926 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
4929 #sound-dai-cells = <0>;
4935 #size-cells = <0>;
4937 port@0 {
4938 reg = <0>;
4977 reg = <0 0x220c2a00 0 0x19c>,
4978 <0 0x220c2200 0 0xec>,
4979 <0 0x220c2600 0 0xec>,
4980 <0 0x220c2000 0 0x1c8>;
4988 #phy-cells = <0>;
4995 reg = <0 0x220c5a00 0 0x19c>,
4996 <0 0x220c5200 0 0xec>,
4997 <0 0x220c5600 0 0xec>,
4998 <0 0x220c5000 0 0x1c8>;
5006 #phy-cells = <0>;
5013 reg = <0 0x22100000 0 0x20000>;
5017 <0>,
5018 <&mdss1_dp0_phy 0>,
5020 <&mdss1_dp1_phy 0>,
5022 <&mdss1_dp2_phy 0>,
5024 <&mdss1_dp3_phy 0>,
5026 <0>,
5027 <0>,
5028 <0>,
5029 <0>;
5041 reg = <0x0 0x23000000 0x0 0x10000>,
5042 <0x0 0x23016000 0x0 0x100>;
5058 iommus = <&apps_smmu 0x40 0xf>;