Lines Matching +full:opp +full:- +full:345000000
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
12 #include <dt-bindings/interconnect/qcom,sc8180x.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
16 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&intc>;
21 #address-cells = <2>;
22 #size-cells = <2>;
25 xo_board_clk: xo-board {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <38400000>;
31 sleep_clk: sleep-clk {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <32764>;
35 clock-output-names = "sleep_clk";
40 #address-cells = <2>;
41 #size-cells = <0>;
47 enable-method = "psci";
48 capacity-dmips-mhz = <602>;
49 next-level-cache = <&L2_0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
51 operating-points-v2 = <&cpu0_opp_table>;
54 power-domains = <&CPU_PD0>;
55 power-domain-names = "psci";
56 #cooling-cells = <2>;
59 L2_0: l2-cache {
61 cache-level = <2>;
62 cache-unified;
63 next-level-cache = <&L3_0>;
64 L3_0: l3-cache {
66 cache-level = <3>;
67 cache-unified;
76 enable-method = "psci";
77 capacity-dmips-mhz = <602>;
78 next-level-cache = <&L2_100>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
80 operating-points-v2 = <&cpu0_opp_table>;
83 power-domains = <&CPU_PD1>;
84 power-domain-names = "psci";
85 #cooling-cells = <2>;
88 L2_100: l2-cache {
90 cache-level = <2>;
91 cache-unified;
92 next-level-cache = <&L3_0>;
101 enable-method = "psci";
102 capacity-dmips-mhz = <602>;
103 next-level-cache = <&L2_200>;
104 qcom,freq-domain = <&cpufreq_hw 0>;
105 operating-points-v2 = <&cpu0_opp_table>;
108 power-domains = <&CPU_PD2>;
109 power-domain-names = "psci";
110 #cooling-cells = <2>;
113 L2_200: l2-cache {
115 cache-level = <2>;
116 cache-unified;
117 next-level-cache = <&L3_0>;
125 enable-method = "psci";
126 capacity-dmips-mhz = <602>;
127 next-level-cache = <&L2_300>;
128 qcom,freq-domain = <&cpufreq_hw 0>;
129 operating-points-v2 = <&cpu0_opp_table>;
132 power-domains = <&CPU_PD3>;
133 power-domain-names = "psci";
134 #cooling-cells = <2>;
137 L2_300: l2-cache {
139 cache-unified;
140 cache-level = <2>;
141 next-level-cache = <&L3_0>;
149 enable-method = "psci";
150 capacity-dmips-mhz = <1024>;
151 next-level-cache = <&L2_400>;
152 qcom,freq-domain = <&cpufreq_hw 1>;
153 operating-points-v2 = <&cpu4_opp_table>;
156 power-domains = <&CPU_PD4>;
157 power-domain-names = "psci";
158 #cooling-cells = <2>;
161 L2_400: l2-cache {
163 cache-unified;
164 cache-level = <2>;
165 next-level-cache = <&L3_0>;
173 enable-method = "psci";
174 capacity-dmips-mhz = <1024>;
175 next-level-cache = <&L2_500>;
176 qcom,freq-domain = <&cpufreq_hw 1>;
177 operating-points-v2 = <&cpu4_opp_table>;
180 power-domains = <&CPU_PD5>;
181 power-domain-names = "psci";
182 #cooling-cells = <2>;
185 L2_500: l2-cache {
187 cache-unified;
188 cache-level = <2>;
189 next-level-cache = <&L3_0>;
197 enable-method = "psci";
198 capacity-dmips-mhz = <1024>;
199 next-level-cache = <&L2_600>;
200 qcom,freq-domain = <&cpufreq_hw 1>;
201 operating-points-v2 = <&cpu4_opp_table>;
204 power-domains = <&CPU_PD6>;
205 power-domain-names = "psci";
206 #cooling-cells = <2>;
209 L2_600: l2-cache {
211 cache-unified;
212 cache-level = <2>;
213 next-level-cache = <&L3_0>;
221 enable-method = "psci";
222 capacity-dmips-mhz = <1024>;
223 next-level-cache = <&L2_700>;
224 qcom,freq-domain = <&cpufreq_hw 1>;
225 operating-points-v2 = <&cpu4_opp_table>;
228 power-domains = <&CPU_PD7>;
229 power-domain-names = "psci";
230 #cooling-cells = <2>;
233 L2_700: l2-cache {
235 cache-unified;
236 cache-level = <2>;
237 next-level-cache = <&L3_0>;
241 cpu-map {
277 idle-states {
278 entry-method = "psci";
280 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
281 compatible = "arm,idle-state";
282 arm,psci-suspend-param = <0x40000004>;
283 entry-latency-us = <355>;
284 exit-latency-us = <909>;
285 min-residency-us = <3934>;
286 local-timer-stop;
289 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
290 compatible = "arm,idle-state";
291 arm,psci-suspend-param = <0x40000004>;
292 entry-latency-us = <2411>;
293 exit-latency-us = <1461>;
294 min-residency-us = <4488>;
295 local-timer-stop;
299 domain-idle-states {
300 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
301 compatible = "domain-idle-state";
302 arm,psci-suspend-param = <0x41000044>;
303 entry-latency-us = <3300>;
304 exit-latency-us = <3300>;
305 min-residency-us = <6000>;
308 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
309 compatible = "domain-idle-state";
310 arm,psci-suspend-param = <0x4100a344>;
311 entry-latency-us = <3263>;
312 exit-latency-us = <6562>;
313 min-residency-us = <9987>;
318 cpu0_opp_table: opp-table-cpu0 {
319 compatible = "operating-points-v2";
320 opp-shared;
322 opp-300000000 {
323 opp-hz = /bits/ 64 <300000000>;
324 opp-peak-kBps = <800000 9600000>;
327 opp-422400000 {
328 opp-hz = /bits/ 64 <422400000>;
329 opp-peak-kBps = <800000 9600000>;
332 opp-537600000 {
333 opp-hz = /bits/ 64 <537600000>;
334 opp-peak-kBps = <800000 12902400>;
337 opp-652800000 {
338 opp-hz = /bits/ 64 <652800000>;
339 opp-peak-kBps = <800000 12902400>;
342 opp-768000000 {
343 opp-hz = /bits/ 64 <768000000>;
344 opp-peak-kBps = <800000 15974400>;
347 opp-883200000 {
348 opp-hz = /bits/ 64 <883200000>;
349 opp-peak-kBps = <1804000 19660800>;
352 opp-998400000 {
353 opp-hz = /bits/ 64 <998400000>;
354 opp-peak-kBps = <1804000 19660800>;
357 opp-1113600000 {
358 opp-hz = /bits/ 64 <1113600000>;
359 opp-peak-kBps = <1804000 22732800>;
362 opp-1228800000 {
363 opp-hz = /bits/ 64 <1228800000>;
364 opp-peak-kBps = <1804000 22732800>;
367 opp-1363200000 {
368 opp-hz = /bits/ 64 <1363200000>;
369 opp-peak-kBps = <2188000 25804800>;
372 opp-1478400000 {
373 opp-hz = /bits/ 64 <1478400000>;
374 opp-peak-kBps = <2188000 31948800>;
377 opp-1574400000 {
378 opp-hz = /bits/ 64 <1574400000>;
379 opp-peak-kBps = <3072000 31948800>;
382 opp-1670400000 {
383 opp-hz = /bits/ 64 <1670400000>;
384 opp-peak-kBps = <3072000 31948800>;
387 opp-1766400000 {
388 opp-hz = /bits/ 64 <1766400000>;
389 opp-peak-kBps = <3072000 31948800>;
393 cpu4_opp_table: opp-table-cpu4 {
394 compatible = "operating-points-v2";
395 opp-shared;
397 opp-825600000 {
398 opp-hz = /bits/ 64 <825600000>;
399 opp-peak-kBps = <1804000 15974400>;
402 opp-940800000 {
403 opp-hz = /bits/ 64 <940800000>;
404 opp-peak-kBps = <2188000 19660800>;
407 opp-1056000000 {
408 opp-hz = /bits/ 64 <1056000000>;
409 opp-peak-kBps = <2188000 22732800>;
412 opp-1171200000 {
413 opp-hz = /bits/ 64 <1171200000>;
414 opp-peak-kBps = <3072000 25804800>;
417 opp-1286400000 {
418 opp-hz = /bits/ 64 <1286400000>;
419 opp-peak-kBps = <3072000 31948800>;
422 opp-1420800000 {
423 opp-hz = /bits/ 64 <1420800000>;
424 opp-peak-kBps = <4068000 31948800>;
427 opp-1536000000 {
428 opp-hz = /bits/ 64 <1536000000>;
429 opp-peak-kBps = <4068000 31948800>;
432 opp-1651200000 {
433 opp-hz = /bits/ 64 <1651200000>;
434 opp-peak-kBps = <4068000 40550400>;
437 opp-1766400000 {
438 opp-hz = /bits/ 64 <1766400000>;
439 opp-peak-kBps = <4068000 40550400>;
442 opp-1881600000 {
443 opp-hz = /bits/ 64 <1881600000>;
444 opp-peak-kBps = <4068000 43008000>;
447 opp-1996800000 {
448 opp-hz = /bits/ 64 <1996800000>;
449 opp-peak-kBps = <6220000 43008000>;
452 opp-2131200000 {
453 opp-hz = /bits/ 64 <2131200000>;
454 opp-peak-kBps = <6220000 49152000>;
457 opp-2246400000 {
458 opp-hz = /bits/ 64 <2246400000>;
459 opp-peak-kBps = <7216000 49152000>;
462 opp-2361600000 {
463 opp-hz = /bits/ 64 <2361600000>;
464 opp-peak-kBps = <8368000 49152000>;
467 opp-2457600000 {
468 opp-hz = /bits/ 64 <2457600000>;
469 opp-peak-kBps = <8368000 51609600>;
472 opp-2553600000 {
473 opp-hz = /bits/ 64 <2553600000>;
474 opp-peak-kBps = <8368000 51609600>;
477 opp-2649600000 {
478 opp-hz = /bits/ 64 <2649600000>;
479 opp-peak-kBps = <8368000 51609600>;
482 opp-2745600000 {
483 opp-hz = /bits/ 64 <2745600000>;
484 opp-peak-kBps = <8368000 51609600>;
487 opp-2841600000 {
488 opp-hz = /bits/ 64 <2841600000>;
489 opp-peak-kBps = <8368000 51609600>;
492 opp-2918400000 {
493 opp-hz = /bits/ 64 <2918400000>;
494 opp-peak-kBps = <8368000 51609600>;
497 opp-2995200000 {
498 opp-hz = /bits/ 64 <2995200000>;
499 opp-peak-kBps = <8368000 51609600>;
505 compatible = "qcom,scm-sc8180x", "qcom,scm";
509 camnoc_virt: interconnect-camnoc-virt {
510 compatible = "qcom,sc8180x-camnoc-virt";
511 #interconnect-cells = <2>;
512 qcom,bcm-voters = <&apps_bcm_voter>;
515 mc_virt: interconnect-mc-virt {
516 compatible = "qcom,sc8180x-mc-virt";
517 #interconnect-cells = <2>;
518 qcom,bcm-voters = <&apps_bcm_voter>;
521 qup_virt: interconnect-qup-virt {
522 compatible = "qcom,sc8180x-qup-virt";
523 #interconnect-cells = <2>;
524 qcom,bcm-voters = <&apps_bcm_voter>;
534 compatible = "arm,armv8-pmuv3";
539 compatible = "arm,psci-1.0";
542 CPU_PD0: power-domain-cpu0 {
543 #power-domain-cells = <0>;
544 power-domains = <&CLUSTER_PD>;
545 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
548 CPU_PD1: power-domain-cpu1 {
549 #power-domain-cells = <0>;
550 power-domains = <&CLUSTER_PD>;
551 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
554 CPU_PD2: power-domain-cpu2 {
555 #power-domain-cells = <0>;
556 power-domains = <&CLUSTER_PD>;
557 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
560 CPU_PD3: power-domain-cpu3 {
561 #power-domain-cells = <0>;
562 power-domains = <&CLUSTER_PD>;
563 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
566 CPU_PD4: power-domain-cpu4 {
567 #power-domain-cells = <0>;
568 power-domains = <&CLUSTER_PD>;
569 domain-idle-states = <&BIG_CPU_SLEEP_0>;
572 CPU_PD5: power-domain-cpu5 {
573 #power-domain-cells = <0>;
574 power-domains = <&CLUSTER_PD>;
575 domain-idle-states = <&BIG_CPU_SLEEP_0>;
578 CPU_PD6: power-domain-cpu6 {
579 #power-domain-cells = <0>;
580 power-domains = <&CLUSTER_PD>;
581 domain-idle-states = <&BIG_CPU_SLEEP_0>;
584 CPU_PD7: power-domain-cpu7 {
585 #power-domain-cells = <0>;
586 power-domains = <&CLUSTER_PD>;
587 domain-idle-states = <&BIG_CPU_SLEEP_0>;
590 CLUSTER_PD: power-domain-cpu-cluster0 {
591 #power-domain-cells = <0>;
592 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;
596 reserved-memory {
597 #address-cells = <2>;
598 #size-cells = <2>;
603 no-map;
608 no-map;
613 no-map;
616 aop_cmd_db: cmd-db@85f20000 {
617 compatible = "qcom,cmd-db";
619 no-map;
624 no-map;
630 no-map;
636 no-map;
641 no-map;
646 no-map;
651 no-map;
656 no-map;
660 smp2p-cdsp {
668 qcom,local-pid = <0>;
669 qcom,remote-pid = <5>;
671 cdsp_smp2p_out: master-kernel {
672 qcom,entry-name = "master-kernel";
673 #qcom,smem-state-cells = <1>;
676 cdsp_smp2p_in: slave-kernel {
677 qcom,entry-name = "slave-kernel";
679 interrupt-controller;
680 #interrupt-cells = <2>;
684 smp2p-lpass {
692 qcom,local-pid = <0>;
693 qcom,remote-pid = <2>;
695 adsp_smp2p_out: master-kernel {
696 qcom,entry-name = "master-kernel";
697 #qcom,smem-state-cells = <1>;
700 adsp_smp2p_in: slave-kernel {
701 qcom,entry-name = "slave-kernel";
703 interrupt-controller;
704 #interrupt-cells = <2>;
708 smp2p-mpss {
716 qcom,local-pid = <0>;
717 qcom,remote-pid = <1>;
719 modem_smp2p_out: master-kernel {
720 qcom,entry-name = "master-kernel";
721 #qcom,smem-state-cells = <1>;
724 modem_smp2p_in: slave-kernel {
725 qcom,entry-name = "slave-kernel";
727 interrupt-controller;
728 #interrupt-cells = <2>;
731 modem_smp2p_ipa_out: ipa-ap-to-modem {
732 qcom,entry-name = "ipa";
733 #qcom,smem-state-cells = <1>;
736 modem_smp2p_ipa_in: ipa-modem-to-ap {
737 qcom,entry-name = "ipa";
738 interrupt-controller;
739 #interrupt-cells = <2>;
742 modem_smp2p_wlan_in: wlan-wpss-to-ap {
743 qcom,entry-name = "wlan";
744 interrupt-controller;
745 #interrupt-cells = <2>;
749 smp2p-slpi {
757 qcom,local-pid = <0>;
758 qcom,remote-pid = <3>;
760 slpi_smp2p_out: master-kernel {
761 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells = <1>;
765 slpi_smp2p_in: slave-kernel {
766 qcom,entry-name = "slave-kernel";
768 interrupt-controller;
769 #interrupt-cells = <2>;
774 compatible = "simple-bus";
775 #address-cells = <2>;
776 #size-cells = <2>;
778 dma-ranges = <0 0 0 0 0x10 0>;
780 gcc: clock-controller@100000 {
781 compatible = "qcom,gcc-sc8180x";
783 #clock-cells = <1>;
784 #reset-cells = <1>;
785 #power-domain-cells = <1>;
789 clock-names = "bi_tcxo",
792 power-domains = <&rpmhpd SC8180X_CX>;
796 compatible = "qcom,geni-se-qup";
800 clock-names = "m-ahb", "s-ahb";
801 #address-cells = <2>;
802 #size-cells = <2>;
808 compatible = "qcom,geni-i2c";
811 clock-names = "se";
816 interconnect-names = "qup-core", "qup-config", "qup-memory";
817 #address-cells = <1>;
818 #size-cells = <0>;
823 compatible = "qcom,geni-spi";
826 clock-names = "se";
830 interconnect-names = "qup-core", "qup-config";
831 #address-cells = <1>;
832 #size-cells = <0>;
837 compatible = "qcom,geni-uart";
840 clock-names = "se";
844 interconnect-names = "qup-core", "qup-config";
849 compatible = "qcom,geni-i2c";
852 clock-names = "se";
857 interconnect-names = "qup-core", "qup-config", "qup-memory";
858 #address-cells = <1>;
859 #size-cells = <0>;
864 compatible = "qcom,geni-spi";
867 clock-names = "se";
871 interconnect-names = "qup-core", "qup-config";
872 #address-cells = <1>;
873 #size-cells = <0>;
878 compatible = "qcom,geni-uart";
881 clock-names = "se";
885 interconnect-names = "qup-core", "qup-config";
890 compatible = "qcom,geni-i2c";
893 clock-names = "se";
898 interconnect-names = "qup-core", "qup-config", "qup-memory";
899 #address-cells = <1>;
900 #size-cells = <0>;
905 compatible = "qcom,geni-spi";
908 clock-names = "se";
912 interconnect-names = "qup-core", "qup-config";
913 #address-cells = <1>;
914 #size-cells = <0>;
919 compatible = "qcom,geni-uart";
922 clock-names = "se";
926 interconnect-names = "qup-core", "qup-config";
931 compatible = "qcom,geni-i2c";
934 clock-names = "se";
939 interconnect-names = "qup-core", "qup-config", "qup-memory";
940 #address-cells = <1>;
941 #size-cells = <0>;
946 compatible = "qcom,geni-spi";
949 clock-names = "se";
953 interconnect-names = "qup-core", "qup-config";
954 #address-cells = <1>;
955 #size-cells = <0>;
960 compatible = "qcom,geni-uart";
963 clock-names = "se";
967 interconnect-names = "qup-core", "qup-config";
972 compatible = "qcom,geni-i2c";
975 clock-names = "se";
980 interconnect-names = "qup-core", "qup-config", "qup-memory";
981 #address-cells = <1>;
982 #size-cells = <0>;
987 compatible = "qcom,geni-spi";
990 clock-names = "se";
994 interconnect-names = "qup-core", "qup-config";
995 #address-cells = <1>;
996 #size-cells = <0>;
1001 compatible = "qcom,geni-uart";
1004 clock-names = "se";
1008 interconnect-names = "qup-core", "qup-config";
1013 compatible = "qcom,geni-i2c";
1016 clock-names = "se";
1021 interconnect-names = "qup-core", "qup-config", "qup-memory";
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1028 compatible = "qcom,geni-spi";
1031 clock-names = "se";
1035 interconnect-names = "qup-core", "qup-config";
1036 #address-cells = <1>;
1037 #size-cells = <0>;
1042 compatible = "qcom,geni-uart";
1045 clock-names = "se";
1049 interconnect-names = "qup-core", "qup-config";
1054 compatible = "qcom,geni-i2c";
1057 clock-names = "se";
1062 interconnect-names = "qup-core", "qup-config", "qup-memory";
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1069 compatible = "qcom,geni-spi";
1072 clock-names = "se";
1076 interconnect-names = "qup-core", "qup-config";
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1083 compatible = "qcom,geni-uart";
1086 clock-names = "se";
1090 interconnect-names = "qup-core", "qup-config";
1095 compatible = "qcom,geni-i2c";
1098 clock-names = "se";
1103 interconnect-names = "qup-core", "qup-config", "qup-memory";
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1110 compatible = "qcom,geni-spi";
1113 clock-names = "se";
1117 interconnect-names = "qup-core", "qup-config";
1118 #address-cells = <1>;
1119 #size-cells = <0>;
1124 compatible = "qcom,geni-uart";
1127 clock-names = "se";
1131 interconnect-names = "qup-core", "qup-config";
1137 compatible = "qcom,geni-se-qup";
1141 clock-names = "m-ahb", "s-ahb";
1142 #address-cells = <2>;
1143 #size-cells = <2>;
1149 compatible = "qcom,geni-i2c";
1152 clock-names = "se";
1157 interconnect-names = "qup-core", "qup-config", "qup-memory";
1158 #address-cells = <1>;
1159 #size-cells = <0>;
1164 compatible = "qcom,geni-spi";
1167 clock-names = "se";
1171 interconnect-names = "qup-core", "qup-config";
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1178 compatible = "qcom,geni-uart";
1181 clock-names = "se";
1185 interconnect-names = "qup-core", "qup-config";
1190 compatible = "qcom,geni-i2c";
1193 clock-names = "se";
1198 interconnect-names = "qup-core", "qup-config", "qup-memory";
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1205 compatible = "qcom,geni-spi";
1208 clock-names = "se";
1212 interconnect-names = "qup-core", "qup-config";
1213 #address-cells = <1>;
1214 #size-cells = <0>;
1219 compatible = "qcom,geni-debug-uart";
1222 clock-names = "se";
1226 interconnect-names = "qup-core", "qup-config";
1231 compatible = "qcom,geni-i2c";
1234 clock-names = "se";
1239 interconnect-names = "qup-core", "qup-config", "qup-memory";
1240 #address-cells = <1>;
1241 #size-cells = <0>;
1246 compatible = "qcom,geni-spi";
1249 clock-names = "se";
1253 interconnect-names = "qup-core", "qup-config";
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1260 compatible = "qcom,geni-uart";
1263 clock-names = "se";
1267 interconnect-names = "qup-core", "qup-config";
1272 compatible = "qcom,geni-i2c";
1275 clock-names = "se";
1280 interconnect-names = "qup-core", "qup-config", "qup-memory";
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1287 compatible = "qcom,geni-spi";
1290 clock-names = "se";
1294 interconnect-names = "qup-core", "qup-config";
1295 #address-cells = <1>;
1296 #size-cells = <0>;
1301 compatible = "qcom,geni-uart";
1304 clock-names = "se";
1308 interconnect-names = "qup-core", "qup-config";
1313 compatible = "qcom,geni-i2c";
1316 clock-names = "se";
1321 interconnect-names = "qup-core", "qup-config", "qup-memory";
1322 #address-cells = <1>;
1323 #size-cells = <0>;
1328 compatible = "qcom,geni-spi";
1331 clock-names = "se";
1335 interconnect-names = "qup-core", "qup-config";
1336 #address-cells = <1>;
1337 #size-cells = <0>;
1342 compatible = "qcom,geni-uart";
1345 clock-names = "se";
1349 interconnect-names = "qup-core", "qup-config";
1354 compatible = "qcom,geni-i2c";
1357 clock-names = "se";
1362 interconnect-names = "qup-core", "qup-config", "qup-memory";
1363 #address-cells = <1>;
1364 #size-cells = <0>;
1369 compatible = "qcom,geni-spi";
1372 clock-names = "se";
1376 interconnect-names = "qup-core", "qup-config";
1377 #address-cells = <1>;
1378 #size-cells = <0>;
1383 compatible = "qcom,geni-uart";
1386 clock-names = "se";
1390 interconnect-names = "qup-core", "qup-config";
1396 compatible = "qcom,geni-se-qup";
1400 clock-names = "m-ahb", "s-ahb";
1401 #address-cells = <2>;
1402 #size-cells = <2>;
1408 compatible = "qcom,geni-i2c";
1411 clock-names = "se";
1416 interconnect-names = "qup-core", "qup-config", "qup-memory";
1417 #address-cells = <1>;
1418 #size-cells = <0>;
1423 compatible = "qcom,geni-spi";
1426 clock-names = "se";
1430 interconnect-names = "qup-core", "qup-config";
1431 #address-cells = <1>;
1432 #size-cells = <0>;
1437 compatible = "qcom,geni-uart";
1440 clock-names = "se";
1444 interconnect-names = "qup-core", "qup-config";
1449 compatible = "qcom,geni-i2c";
1452 clock-names = "se";
1457 interconnect-names = "qup-core", "qup-config", "qup-memory";
1458 #address-cells = <1>;
1459 #size-cells = <0>;
1464 compatible = "qcom,geni-spi";
1467 clock-names = "se";
1471 interconnect-names = "qup-core", "qup-config";
1472 #address-cells = <1>;
1473 #size-cells = <0>;
1478 compatible = "qcom,geni-uart";
1481 clock-names = "se";
1485 interconnect-names = "qup-core", "qup-config";
1490 compatible = "qcom,geni-i2c";
1493 clock-names = "se";
1498 interconnect-names = "qup-core", "qup-config", "qup-memory";
1499 #address-cells = <1>;
1500 #size-cells = <0>;
1505 compatible = "qcom,geni-spi";
1508 clock-names = "se";
1512 interconnect-names = "qup-core", "qup-config";
1513 #address-cells = <1>;
1514 #size-cells = <0>;
1519 compatible = "qcom,geni-uart";
1522 clock-names = "se";
1526 interconnect-names = "qup-core", "qup-config";
1531 compatible = "qcom,geni-i2c";
1534 clock-names = "se";
1539 interconnect-names = "qup-core", "qup-config", "qup-memory";
1540 #address-cells = <1>;
1541 #size-cells = <0>;
1546 compatible = "qcom,geni-spi";
1549 clock-names = "se";
1553 interconnect-names = "qup-core", "qup-config";
1554 #address-cells = <1>;
1555 #size-cells = <0>;
1560 compatible = "qcom,geni-uart";
1563 clock-names = "se";
1567 interconnect-names = "qup-core", "qup-config";
1572 compatible = "qcom,geni-i2c";
1575 clock-names = "se";
1580 interconnect-names = "qup-core", "qup-config", "qup-memory";
1581 #address-cells = <1>;
1582 #size-cells = <0>;
1587 compatible = "qcom,geni-spi";
1590 clock-names = "se";
1594 interconnect-names = "qup-core", "qup-config";
1595 #address-cells = <1>;
1596 #size-cells = <0>;
1601 compatible = "qcom,geni-uart";
1604 clock-names = "se";
1608 interconnect-names = "qup-core", "qup-config";
1613 compatible = "qcom,geni-i2c";
1616 clock-names = "se";
1621 interconnect-names = "qup-core", "qup-config", "qup-memory";
1622 #address-cells = <1>;
1623 #size-cells = <0>;
1628 compatible = "qcom,geni-spi";
1631 clock-names = "se";
1635 interconnect-names = "qup-core", "qup-config";
1636 #address-cells = <1>;
1637 #size-cells = <0>;
1642 compatible = "qcom,geni-uart";
1645 clock-names = "se";
1649 interconnect-names = "qup-core", "qup-config";
1655 compatible = "qcom,sc8180x-config-noc";
1657 #interconnect-cells = <2>;
1658 qcom,bcm-voters = <&apps_bcm_voter>;
1662 compatible = "qcom,sc8180x-system-noc";
1664 #interconnect-cells = <2>;
1665 qcom,bcm-voters = <&apps_bcm_voter>;
1669 compatible = "qcom,sc8180x-aggre1-noc";
1671 #interconnect-cells = <2>;
1672 qcom,bcm-voters = <&apps_bcm_voter>;
1676 compatible = "qcom,sc8180x-aggre2-noc";
1678 #interconnect-cells = <2>;
1679 qcom,bcm-voters = <&apps_bcm_voter>;
1683 compatible = "qcom,sc8180x-compute-noc";
1685 #interconnect-cells = <2>;
1686 qcom,bcm-voters = <&apps_bcm_voter>;
1690 compatible = "qcom,sc8180x-mmss-noc";
1692 #interconnect-cells = <2>;
1693 qcom,bcm-voters = <&apps_bcm_voter>;
1697 compatible = "qcom,pcie-sc8180x";
1703 reg-names = "parf",
1709 linux,pci-domain = <0>;
1710 bus-range = <0x00 0xff>;
1711 num-lanes = <2>;
1713 #address-cells = <3>;
1714 #size-cells = <2>;
1720 interrupt-names = "msi";
1721 #interrupt-cells = <1>;
1722 interrupt-map-mask = <0 0 0 0x7>;
1723 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1736 clock-names = "pipe",
1745 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1746 assigned-clock-rates = <19200000>;
1749 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1753 reset-names = "pci";
1755 power-domains = <&gcc PCIE_0_GDSC>;
1759 interconnect-names = "pcie-mem", "cpu-pcie";
1762 phy-names = "pciephy";
1763 dma-coherent;
1769 compatible = "qcom,sc8180x-qmp-pcie-phy";
1776 clock-names = "aux",
1781 #clock-cells = <0>;
1782 clock-output-names = "pcie_0_pipe_clk";
1783 #phy-cells = <0>;
1786 reset-names = "phy";
1788 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1789 assigned-clock-rates = <100000000>;
1795 compatible = "qcom,pcie-sc8180x";
1801 reg-names = "parf",
1807 linux,pci-domain = <3>;
1808 bus-range = <0x00 0xff>;
1809 num-lanes = <2>;
1811 #address-cells = <3>;
1812 #size-cells = <2>;
1818 interrupt-names = "msi";
1819 #interrupt-cells = <1>;
1820 interrupt-map-mask = <0 0 0 0x7>;
1821 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1834 clock-names = "pipe",
1843 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1844 assigned-clock-rates = <19200000>;
1847 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1851 reset-names = "pci";
1853 power-domains = <&gcc PCIE_3_GDSC>;
1857 interconnect-names = "pcie-mem", "cpu-pcie";
1860 phy-names = "pciephy";
1861 dma-coherent;
1867 compatible = "qcom,sc8180x-qmp-pcie-phy";
1874 clock-names = "aux",
1879 #clock-cells = <0>;
1880 clock-output-names = "pcie_3_pipe_clk";
1882 #phy-cells = <0>;
1885 reset-names = "phy";
1887 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1888 assigned-clock-rates = <100000000>;
1894 compatible = "qcom,pcie-sc8180x";
1900 reg-names = "parf",
1906 linux,pci-domain = <1>;
1907 bus-range = <0x00 0xff>;
1908 num-lanes = <2>;
1910 #address-cells = <3>;
1911 #size-cells = <2>;
1917 interrupt-names = "msi";
1918 #interrupt-cells = <1>;
1919 interrupt-map-mask = <0 0 0 0x7>;
1920 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1933 clock-names = "pipe",
1942 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1943 assigned-clock-rates = <19200000>;
1946 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1950 reset-names = "pci";
1952 power-domains = <&gcc PCIE_1_GDSC>;
1956 interconnect-names = "pcie-mem", "cpu-pcie";
1959 phy-names = "pciephy";
1960 dma-coherent;
1966 compatible = "qcom,sc8180x-qmp-pcie-phy";
1973 clock-names = "aux",
1978 #clock-cells = <0>;
1979 clock-output-names = "pcie_1_pipe_clk";
1981 #phy-cells = <0>;
1984 reset-names = "phy";
1986 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1987 assigned-clock-rates = <100000000>;
1993 compatible = "qcom,pcie-sc8180x";
1999 reg-names = "parf",
2005 linux,pci-domain = <2>;
2006 bus-range = <0x00 0xff>;
2007 num-lanes = <4>;
2009 #address-cells = <3>;
2010 #size-cells = <2>;
2016 interrupt-names = "msi";
2017 #interrupt-cells = <1>;
2018 interrupt-map-mask = <0 0 0 0x7>;
2019 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2032 clock-names = "pipe",
2041 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2042 assigned-clock-rates = <19200000>;
2045 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2049 reset-names = "pci";
2051 power-domains = <&gcc PCIE_2_GDSC>;
2055 interconnect-names = "pcie-mem", "cpu-pcie";
2058 phy-names = "pciephy";
2059 dma-coherent;
2065 compatible = "qcom,sc8180x-qmp-pcie-phy";
2072 clock-names = "aux",
2077 #clock-cells = <0>;
2078 clock-output-names = "pcie_2_pipe_clk";
2080 #phy-cells = <0>;
2083 reset-names = "phy";
2085 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2086 assigned-clock-rates = <100000000>;
2092 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
2093 "jedec,ufs-2.0";
2097 phy-names = "ufsphy";
2098 lanes-per-direction = <2>;
2099 #reset-cells = <1>;
2101 reset-names = "rst";
2113 clock-names = "core_clk",
2121 freq-table-hz = <37500000 300000000>,
2133 ufs_mem_phy: phy-wrapper@1d87000 {
2134 compatible = "qcom,sc8180x-qmp-ufs-phy";
2139 clock-names = "ref",
2143 reset-names = "ufsphy";
2145 power-domains = <&gcc UFS_PHY_GDSC>;
2147 #phy-cells = <0>;
2153 compatible = "qcom,sc8180x-ipa-virt";
2155 #interconnect-cells = <2>;
2156 qcom,bcm-voters = <&apps_bcm_voter>;
2160 compatible = "qcom,tcsr-mutex";
2162 #hwlock-cells = <1>;
2166 compatible = "qcom,adreno-680.1", "qcom,adreno";
2167 #stream-id-cells = <16>;
2170 reg-names = "kgsl_3d0_reg_memory";
2176 operating-points-v2 = <&gpu_opp_table>;
2179 interconnect-names = "gfx-mem";
2184 gpu_opp_table: opp-table {
2185 compatible = "operating-points-v2";
2187 opp-514000000 {
2188 opp-hz = /bits/ 64 <514000000>;
2189 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2192 opp-500000000 {
2193 opp-hz = /bits/ 64 <500000000>;
2194 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2197 opp-461000000 {
2198 opp-hz = /bits/ 64 <461000000>;
2199 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2202 opp-405000000 {
2203 opp-hz = /bits/ 64 <405000000>;
2204 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2207 opp-315000000 {
2208 opp-hz = /bits/ 64 <315000000>;
2209 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2212 opp-256000000 {
2213 opp-hz = /bits/ 64 <256000000>;
2214 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2217 opp-177000000 {
2218 opp-hz = /bits/ 64 <177000000>;
2219 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2225 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2230 reg-names = "gmu",
2236 interrupt-names = "hfi", "gmu";
2243 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2245 power-domains = <&gpucc GPU_CX_GDSC>,
2247 power-domain-names = "cx", "gx";
2251 operating-points-v2 = <&gmu_opp_table>;
2253 gmu_opp_table: opp-table {
2254 compatible = "operating-points-v2";
2256 opp-200000000 {
2257 opp-hz = /bits/ 64 <200000000>;
2258 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2261 opp-500000000 {
2262 opp-hz = /bits/ 64 <500000000>;
2263 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2268 gpucc: clock-controller@2c90000 {
2269 compatible = "qcom,sc8180x-gpucc";
2274 clock-names = "bi_tcxo",
2277 #clock-cells = <1>;
2278 #reset-cells = <1>;
2279 #power-domain-cells = <1>;
2283 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
2284 "qcom,smmu-500", "arm,mmu-500";
2286 #iommu-cells = <2>;
2287 #global-interrupts = <1>;
2300 clock-names = "ahb", "bus", "iface";
2302 power-domains = <&gpucc GPU_CX_GDSC>;
2306 compatible = "qcom,sc8180x-tlmm";
2310 reg-names = "west", "east", "south";
2312 gpio-controller;
2313 #gpio-cells = <2>;
2314 interrupt-controller;
2315 #interrupt-cells = <2>;
2316 gpio-ranges = <&tlmm 0 0 191>;
2317 wakeup-parent = <&pdc>;
2321 compatible = "qcom,sc8180x-mpss-pas";
2324 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2330 interrupt-names = "wdog", "fatal", "ready", "handover",
2331 "stop-ack", "shutdown-ack";
2334 clock-names = "xo";
2336 power-domains = <&rpmhpd SC8180X_CX>,
2338 power-domain-names = "cx", "mss";
2342 qcom,smem-states = <&modem_smp2p_out 0>;
2343 qcom,smem-state-names = "stop";
2345 glink-edge {
2348 qcom,remote-pid = <1>;
2354 compatible = "qcom,sc8180x-cdsp-pas";
2357 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2362 interrupt-names = "wdog", "fatal", "ready",
2363 "handover", "stop-ack";
2366 clock-names = "xo";
2368 power-domains = <&rpmhpd SC8180X_CX>;
2369 power-domain-names = "cx";
2373 qcom,smem-states = <&cdsp_smp2p_out 0>;
2374 qcom,smem-state-names = "stop";
2378 glink-edge {
2381 qcom,remote-pid = <5>;
2387 compatible = "qcom,sc8180x-usb-hs-phy",
2388 "qcom,usb-snps-hs-7nm-phy";
2391 clock-names = "ref";
2394 #phy-cells = <0>;
2400 compatible = "qcom,sc8180x-usb-hs-phy",
2401 "qcom,usb-snps-hs-7nm-phy";
2404 clock-names = "ref";
2407 #phy-cells = <0>;
2413 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2417 reg-names = "reg-base", "dp_com";
2422 clock-names = "aux",
2428 reset-names = "phy", "common";
2430 #clock-cells = <1>;
2431 #address-cells = <2>;
2432 #size-cells = <2>;
2438 #address-cells = <1>;
2439 #size-cells = <0>;
2454 usb_prim_ssphy: usb3-phy@88e9200 {
2461 #phy-cells = <0>;
2463 clock-names = "pipe0";
2464 clock-output-names = "usb3_prim_phy_pipe_clk_src";
2467 usb_prim_dpphy: dp-phy@88ea200 {
2473 #clock-cells = <1>;
2474 #phy-cells = <0>;
2479 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2483 reg-names = "reg-base", "dp_com";
2488 clock-names = "aux",
2494 reset-names = "phy", "common";
2496 #clock-cells = <1>;
2497 #address-cells = <2>;
2498 #size-cells = <2>;
2504 #address-cells = <1>;
2505 #size-cells = <0>;
2520 usb_sec_ssphy: usb3-phy@88e9200 {
2527 #phy-cells = <0>;
2529 clock-names = "pipe0";
2530 clock-output-names = "usb3_sec_phy_pipe_clk_src";
2533 usb_sec_dpphy: dp-phy@88ef200 {
2539 #clock-cells = <1>;
2540 #phy-cells = <0>;
2541 clock-output-names = "qmp_dptx1_phy_pll_link_clk",
2546 system-cache-controller@9200000 {
2547 compatible = "qcom,sc8180x-llcc";
2553 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2560 compatible = "qcom,sc8180x-gem-noc";
2562 #interconnect-cells = <2>;
2563 qcom,bcm-voters = <&apps_bcm_voter>;
2567 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2569 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2573 interrupt-names = "hs_phy_irq",
2584 clock-names = "cfg_noc",
2591 power-domains = <&gcc USB30_PRIM_GDSC>;
2595 interconnect-names = "usb-ddr", "apps-usb";
2597 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2599 assigned-clock-rates = <19200000>, <200000000>;
2601 #address-cells = <2>;
2602 #size-cells = <2>;
2604 dma-ranges;
2616 phy-names = "usb2-phy", "usb3-phy";
2626 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2635 clock-names = "cfg_noc",
2642 power-domains = <&gcc USB30_SEC_GDSC>;
2643 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2647 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2650 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2652 assigned-clock-rates = <19200000>, <200000000>;
2656 interconnect-names = "usb-ddr", "apps-usb";
2658 #address-cells = <2>;
2659 #size-cells = <2>;
2661 dma-ranges;
2673 phy-names = "usb2-phy", "usb3-phy";
2683 compatible = "qcom,sc8180x-mdss";
2685 reg-names = "mdss";
2687 power-domains = <&dispcc MDSS_GDSC>;
2693 clock-names = "iface",
2701 interrupt-controller;
2702 #interrupt-cells = <1>;
2706 interconnect-names = "mdp0-mem", "mdp1-mem";
2710 #address-cells = <2>;
2711 #size-cells = <2>;
2717 compatible = "qcom,sc8180x-dpu";
2720 reg-names = "mdp", "vbif";
2726 clock-names = "iface",
2731 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2732 assigned-clock-rates = <19200000>;
2734 operating-points-v2 = <&mdp_opp_table>;
2735 power-domains = <&rpmhpd SC8180X_MMCX>;
2737 interrupt-parent = <&mdss>;
2741 #address-cells = <1>;
2742 #size-cells = <0>;
2747 remote-endpoint = <&dp0_in>;
2754 remote-endpoint = <&mdss_dsi0_in>;
2761 remote-endpoint = <&mdss_dsi1_in>;
2768 remote-endpoint = <&dp1_in>;
2775 remote-endpoint = <&edp_in>;
2780 mdp_opp_table: opp-table {
2781 compatible = "operating-points-v2";
2783 opp-200000000 {
2784 opp-hz = /bits/ 64 <200000000>;
2785 required-opps = <&rpmhpd_opp_low_svs>;
2788 opp-300000000 {
2789 opp-hz = /bits/ 64 <300000000>;
2790 required-opps = <&rpmhpd_opp_svs>;
2793 opp-345000000 {
2794 opp-hz = /bits/ 64 <345000000>;
2795 required-opps = <&rpmhpd_opp_svs_l1>;
2798 opp-460000000 {
2799 opp-hz = /bits/ 64 <460000000>;
2800 required-opps = <&rpmhpd_opp_nom>;
2806 compatible = "qcom,mdss-dsi-ctrl";
2808 reg-names = "dsi_ctrl";
2810 interrupt-parent = <&mdss>;
2819 clock-names = "byte",
2826 operating-points-v2 = <&dsi_opp_table>;
2827 power-domains = <&rpmhpd SC8180X_MMCX>;
2830 phy-names = "dsi";
2835 #address-cells = <1>;
2836 #size-cells = <0>;
2841 remote-endpoint = <&dpu_intf1_out>;
2852 dsi_opp_table: opp-table {
2853 compatible = "operating-points-v2";
2855 opp-187500000 {
2856 opp-hz = /bits/ 64 <187500000>;
2857 required-opps = <&rpmhpd_opp_low_svs>;
2860 opp-300000000 {
2861 opp-hz = /bits/ 64 <300000000>;
2862 required-opps = <&rpmhpd_opp_svs>;
2865 opp-358000000 {
2866 opp-hz = /bits/ 64 <358000000>;
2867 required-opps = <&rpmhpd_opp_svs_l1>;
2872 mdss_dsi0_phy: dsi-phy@ae94400 {
2873 compatible = "qcom,dsi-phy-7nm";
2877 reg-names = "dsi_phy",
2881 #clock-cells = <1>;
2882 #phy-cells = <0>;
2886 clock-names = "iface", "ref";
2892 compatible = "qcom,mdss-dsi-ctrl";
2894 reg-names = "dsi_ctrl";
2896 interrupt-parent = <&mdss>;
2905 clock-names = "byte",
2912 operating-points-v2 = <&dsi_opp_table>;
2913 power-domains = <&rpmhpd SC8180X_MMCX>;
2916 phy-names = "dsi";
2921 #address-cells = <1>;
2922 #size-cells = <0>;
2927 remote-endpoint = <&dpu_intf2_out>;
2939 mdss_dsi1_phy: dsi-phy@ae96400 {
2940 compatible = "qcom,dsi-phy-7nm";
2944 reg-names = "dsi_phy",
2948 #clock-cells = <1>;
2949 #phy-cells = <0>;
2953 clock-names = "iface", "ref";
2958 mdss_dp0: displayport-controller@ae90000 {
2959 compatible = "qcom,sc8180x-dp";
2964 interrupt-parent = <&mdss>;
2971 clock-names = "core_iface",
2977 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2979 assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>;
2982 phy-names = "dp";
2984 #sound-dai-cells = <0>;
2986 operating-points-v2 = <&dp0_opp_table>;
2987 power-domains = <&rpmhpd SC8180X_MMCX>;
2992 #address-cells = <1>;
2993 #size-cells = <0>;
2998 remote-endpoint = <&dpu_intf0_out>;
3009 dp0_opp_table: opp-table {
3010 compatible = "operating-points-v2";
3012 opp-160000000 {
3013 opp-hz = /bits/ 64 <160000000>;
3014 required-opps = <&rpmhpd_opp_low_svs>;
3017 opp-270000000 {
3018 opp-hz = /bits/ 64 <270000000>;
3019 required-opps = <&rpmhpd_opp_svs>;
3022 opp-540000000 {
3023 opp-hz = /bits/ 64 <540000000>;
3024 required-opps = <&rpmhpd_opp_svs_l1>;
3027 opp-810000000 {
3028 opp-hz = /bits/ 64 <810000000>;
3029 required-opps = <&rpmhpd_opp_nom>;
3034 mdss_dp1: displayport-controller@ae98000 {
3035 compatible = "qcom,sc8180x-dp";
3040 interrupt-parent = <&mdss>;
3047 clock-names = "core_iface",
3053 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
3055 assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>;
3058 phy-names = "dp";
3060 #sound-dai-cells = <0>;
3062 operating-points-v2 = <&dp0_opp_table>;
3063 power-domains = <&rpmhpd SC8180X_MMCX>;
3068 #address-cells = <1>;
3069 #size-cells = <0>;
3074 remote-endpoint = <&dpu_intf4_out>;
3085 dp1_opp_table: opp-table {
3086 compatible = "operating-points-v2";
3088 opp-160000000 {
3089 opp-hz = /bits/ 64 <160000000>;
3090 required-opps = <&rpmhpd_opp_low_svs>;
3093 opp-270000000 {
3094 opp-hz = /bits/ 64 <270000000>;
3095 required-opps = <&rpmhpd_opp_svs>;
3098 opp-540000000 {
3099 opp-hz = /bits/ 64 <540000000>;
3100 required-opps = <&rpmhpd_opp_svs_l1>;
3103 opp-810000000 {
3104 opp-hz = /bits/ 64 <810000000>;
3105 required-opps = <&rpmhpd_opp_nom>;
3110 mdss_edp: displayport-controller@ae9a000 {
3111 compatible = "qcom,sc8180x-edp";
3116 interrupt-parent = <&mdss>;
3123 clock-names = "core_iface",
3129 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
3131 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3134 phy-names = "dp";
3136 #sound-dai-cells = <0>;
3138 operating-points-v2 = <&edp_opp_table>;
3139 power-domains = <&rpmhpd SC8180X_MMCX>;
3144 #address-cells = <1>;
3145 #size-cells = <0>;
3150 remote-endpoint = <&dpu_intf5_out>;
3155 edp_opp_table: opp-table {
3156 compatible = "operating-points-v2";
3158 opp-160000000 {
3159 opp-hz = /bits/ 64 <160000000>;
3160 required-opps = <&rpmhpd_opp_low_svs>;
3163 opp-270000000 {
3164 opp-hz = /bits/ 64 <270000000>;
3165 required-opps = <&rpmhpd_opp_svs>;
3168 opp-540000000 {
3169 opp-hz = /bits/ 64 <540000000>;
3170 required-opps = <&rpmhpd_opp_svs_l1>;
3173 opp-810000000 {
3174 opp-hz = /bits/ 64 <810000000>;
3175 required-opps = <&rpmhpd_opp_nom>;
3182 compatible = "qcom,sc8180x-edp-phy";
3190 clock-names = "aux", "cfg_ahb";
3192 power-domains = <&rpmhpd SC8180X_MX>;
3194 #clock-cells = <1>;
3195 #phy-cells = <0>;
3198 dispcc: clock-controller@af00000 {
3199 compatible = "qcom,sc8180x-dispcc";
3209 clock-names = "bi_tcxo",
3217 power-domains = <&rpmhpd SC8180X_MMCX>;
3218 required-opps = <&rpmhpd_opp_low_svs>;
3219 #clock-cells = <1>;
3220 #reset-cells = <1>;
3221 #power-domain-cells = <1>;
3224 pdc: interrupt-controller@b220000 {
3225 compatible = "qcom,sc8180x-pdc", "qcom,pdc";
3227 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3228 #interrupt-cells = <2>;
3229 interrupt-parent = <&intc>;
3230 interrupt-controller;
3233 tsens0: thermal-sensor@c263000 {
3234 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3240 interrupt-names = "uplow", "critical";
3241 #thermal-sensor-cells = <1>;
3244 tsens1: thermal-sensor@c265000 {
3245 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3251 interrupt-names = "uplow", "critical";
3252 #thermal-sensor-cells = <1>;
3255 aoss_qmp: power-controller@c300000 {
3256 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
3261 #clock-cells = <0>;
3262 #power-domain-cells = <1>;
3266 compatible = "qcom,spmi-pmic-arb";
3272 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3273 interrupt-names = "periph_irq";
3277 #address-cells = <2>;
3278 #size-cells = <0>;
3279 interrupt-controller;
3280 #interrupt-cells = <4>;
3281 cell-index = <0>;
3285 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
3287 #iommu-cells = <2>;
3288 #global-interrupts = <1>;
3400 compatible = "qcom,sc8180x-adsp-pas";
3403 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3408 interrupt-names = "wdog", "fatal", "ready",
3409 "handover", "stop-ack";
3412 clock-names = "xo";
3414 power-domains = <&rpmhpd SC8180X_CX>;
3415 power-domain-names = "cx";
3419 qcom,smem-states = <&adsp_smp2p_out 0>;
3420 qcom,smem-state-names = "stop";
3424 remoteproc_adsp_glink: glink-edge {
3427 qcom,remote-pid = <2>;
3432 intc: interrupt-controller@17a00000 {
3433 compatible = "arm,gic-v3";
3434 interrupt-controller;
3435 #interrupt-cells = <3>;
3442 compatible = "qcom,sc8180x-apss-shared";
3444 #mbox-cells = <1>;
3448 compatible = "arm,armv7-timer-mem";
3451 #address-cells = <1>;
3452 #size-cells = <1>;
3458 frame-number = <0>;
3465 frame-number = <1>;
3472 frame-number = <2>;
3479 frame-number = <3>;
3486 frame-number = <4>;
3493 frame-number = <5>;
3500 frame-number = <6>;
3507 compatible = "qcom,rpmh-rsc";
3511 reg-names = "drv-0", "drv-1", "drv-2";
3515 qcom,tcs-offset = <0xd00>;
3516 qcom,drv-id = <2>;
3517 qcom,tcs-config = <ACTIVE_TCS 2>,
3522 power-domains = <&CLUSTER_PD>;
3524 apps_bcm_voter: bcm-voter {
3525 compatible = "qcom,bcm-voter";
3528 rpmhcc: clock-controller {
3529 compatible = "qcom,sc8180x-rpmh-clk";
3530 #clock-cells = <1>;
3531 clock-names = "xo";
3535 rpmhpd: power-controller {
3536 compatible = "qcom,sc8180x-rpmhpd";
3537 #power-domain-cells = <1>;
3538 operating-points-v2 = <&rpmhpd_opp_table>;
3540 rpmhpd_opp_table: opp-table {
3541 compatible = "operating-points-v2";
3544 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3548 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3552 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3556 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3560 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3564 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3568 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3572 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3576 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3580 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3587 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
3591 clock-names = "xo", "alternate";
3593 #interconnect-cells = <1>;
3597 compatible = "qcom,sc8180x-lmh";
3601 qcom,lmh-temp-arm-millicelsius = <65000>;
3602 qcom,lmh-temp-low-millicelsius = <94500>;
3603 qcom,lmh-temp-high-millicelsius = <95000>;
3604 interrupt-controller;
3605 #interrupt-cells = <1>;
3609 compatible = "qcom,sc8180x-lmh";
3613 qcom,lmh-temp-arm-millicelsius = <65000>;
3614 qcom,lmh-temp-low-millicelsius = <94500>;
3615 qcom,lmh-temp-high-millicelsius = <95000>;
3616 interrupt-controller;
3617 #interrupt-cells = <1>;
3621 compatible = "qcom,sc8180x-cpufreq-hw", "qcom,cpufreq-hw";
3623 reg-names = "freq-domain0", "freq-domain1";
3626 clock-names = "xo", "alternate";
3628 #freq-domain-cells = <1>;
3629 #clock-cells = <1>;
3633 compatible = "qcom,wcn3990-wifi";
3635 reg-names = "membase";
3636 clock-names = "cxo_ref_clk_pin";
3651 qcom,msa-fixed-perm;
3656 thermal-zones {
3657 cpu0-thermal {
3658 polling-delay-passive = <250>;
3659 polling-delay = <1000>;
3661 thermal-sensors = <&tsens0 1>;
3664 cpu-crit {
3672 cpu1-thermal {
3673 polling-delay-passive = <250>;
3674 polling-delay = <1000>;
3676 thermal-sensors = <&tsens0 2>;
3679 cpu-crit {
3687 cpu2-thermal {
3688 polling-delay-passive = <250>;
3689 polling-delay = <1000>;
3691 thermal-sensors = <&tsens0 3>;
3694 cpu-crit {
3702 cpu3-thermal {
3703 polling-delay-passive = <250>;
3704 polling-delay = <1000>;
3706 thermal-sensors = <&tsens0 4>;
3709 cpu-crit {
3717 cpu4-top-thermal {
3718 polling-delay-passive = <250>;
3719 polling-delay = <1000>;
3721 thermal-sensors = <&tsens0 7>;
3724 cpu-crit {
3732 cpu5-top-thermal {
3733 polling-delay-passive = <250>;
3734 polling-delay = <1000>;
3736 thermal-sensors = <&tsens0 8>;
3739 cpu-crit {
3747 cpu6-top-thermal {
3748 polling-delay-passive = <250>;
3749 polling-delay = <1000>;
3751 thermal-sensors = <&tsens0 9>;
3754 cpu-crit {
3762 cpu7-top-thermal {
3763 polling-delay-passive = <250>;
3764 polling-delay = <1000>;
3766 thermal-sensors = <&tsens0 10>;
3769 cpu-crit {
3777 cpu4-bottom-thermal {
3778 polling-delay-passive = <250>;
3779 polling-delay = <1000>;
3781 thermal-sensors = <&tsens0 11>;
3784 cpu-crit {
3792 cpu5-bottom-thermal {
3793 polling-delay-passive = <250>;
3794 polling-delay = <1000>;
3796 thermal-sensors = <&tsens0 12>;
3799 cpu-crit {
3807 cpu6-bottom-thermal {
3808 polling-delay-passive = <250>;
3809 polling-delay = <1000>;
3811 thermal-sensors = <&tsens0 13>;
3814 cpu-crit {
3822 cpu7-bottom-thermal {
3823 polling-delay-passive = <250>;
3824 polling-delay = <1000>;
3826 thermal-sensors = <&tsens0 14>;
3829 cpu-crit {
3837 aoss0-thermal {
3838 polling-delay-passive = <250>;
3839 polling-delay = <1000>;
3841 thermal-sensors = <&tsens0 0>;
3844 trip-point0 {
3852 cluster0-thermal {
3853 polling-delay-passive = <250>;
3854 polling-delay = <1000>;
3856 thermal-sensors = <&tsens0 5>;
3859 cluster-crit {
3867 cluster1-thermal {
3868 polling-delay-passive = <250>;
3869 polling-delay = <1000>;
3871 thermal-sensors = <&tsens0 6>;
3874 cluster-crit {
3882 gpu-top-thermal {
3883 polling-delay-passive = <250>;
3884 polling-delay = <1000>;
3886 thermal-sensors = <&tsens0 15>;
3889 trip-point0 {
3897 aoss1-thermal {
3898 polling-delay-passive = <250>;
3899 polling-delay = <1000>;
3901 thermal-sensors = <&tsens1 0>;
3904 trip-point0 {
3912 wlan-thermal {
3913 polling-delay-passive = <250>;
3914 polling-delay = <1000>;
3916 thermal-sensors = <&tsens1 1>;
3919 trip-point0 {
3927 video-thermal {
3928 polling-delay-passive = <250>;
3929 polling-delay = <1000>;
3931 thermal-sensors = <&tsens1 2>;
3934 trip-point0 {
3942 mem-thermal {
3943 polling-delay-passive = <250>;
3944 polling-delay = <1000>;
3946 thermal-sensors = <&tsens1 3>;
3949 trip-point0 {
3957 q6-hvx-thermal {
3958 polling-delay-passive = <250>;
3959 polling-delay = <1000>;
3961 thermal-sensors = <&tsens1 4>;
3964 trip-point0 {
3972 camera-thermal {
3973 polling-delay-passive = <250>;
3974 polling-delay = <1000>;
3976 thermal-sensors = <&tsens1 5>;
3979 trip-point0 {
3987 compute-thermal {
3988 polling-delay-passive = <250>;
3989 polling-delay = <1000>;
3991 thermal-sensors = <&tsens1 6>;
3994 trip-point0 {
4002 mdm-dsp-thermal {
4003 polling-delay-passive = <250>;
4004 polling-delay = <1000>;
4006 thermal-sensors = <&tsens1 7>;
4009 trip-point0 {
4017 npu-thermal {
4018 polling-delay-passive = <250>;
4019 polling-delay = <1000>;
4021 thermal-sensors = <&tsens1 8>;
4024 trip-point0 {
4032 gpu-bottom-thermal {
4033 polling-delay-passive = <250>;
4034 polling-delay = <1000>;
4036 thermal-sensors = <&tsens1 11>;
4039 trip-point0 {
4049 compatible = "arm,armv8-timer";