Lines Matching +full:0 +full:x01740000
27 #clock-cells = <0>;
33 #clock-cells = <0>;
41 #size-cells = <0>;
43 CPU0: cpu@0 {
46 reg = <0x0 0x0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
57 clocks = <&cpufreq_hw 0>;
75 reg = <0x0 0x100>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
86 clocks = <&cpufreq_hw 0>;
100 reg = <0x0 0x200>;
104 qcom,freq-domain = <&cpufreq_hw 0>;
111 clocks = <&cpufreq_hw 0>;
124 reg = <0x0 0x300>;
128 qcom,freq-domain = <&cpufreq_hw 0>;
135 clocks = <&cpufreq_hw 0>;
148 reg = <0x0 0x400>;
172 reg = <0x0 0x500>;
196 reg = <0x0 0x600>;
220 reg = <0x0 0x700>;
280 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
282 arm,psci-suspend-param = <0x40000004>;
289 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
291 arm,psci-suspend-param = <0x40000004>;
300 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
302 arm,psci-suspend-param = <0x41000044>;
310 arm,psci-suspend-param = <0x4100a344>;
530 reg = <0x0 0x80000000 0x0 0x0>;
543 #power-domain-cells = <0>;
549 #power-domain-cells = <0>;
555 #power-domain-cells = <0>;
561 #power-domain-cells = <0>;
567 #power-domain-cells = <0>;
573 #power-domain-cells = <0>;
579 #power-domain-cells = <0>;
585 #power-domain-cells = <0>;
591 #power-domain-cells = <0>;
602 reg = <0x0 0x85700000 0x0 0x600000>;
607 reg = <0x0 0x85d00000 0x0 0x140000>;
612 reg = <0x0 0x85f00000 0x0 0x20000>;
618 reg = <0x0 0x85f20000 0x0 0x20000>;
623 reg = <0x0 0x85f40000 0x0 0x10000>;
629 reg = <0x0 0x86000000 0x0 0x200000>;
635 reg = <0x0 0x86200000 0x0 0x3900000>;
640 reg = <0x0 0x89b00000 0x0 0x1c00000>;
645 reg = <0x0 0x9d400000 0x0 0x1000000>;
650 reg = <0x0 0x9e400000 0x0 0x1400000>;
655 reg = <0x0 0x9f800000 0x0 0x800000>;
668 qcom,local-pid = <0>;
692 qcom,local-pid = <0>;
716 qcom,local-pid = <0>;
757 qcom,local-pid = <0>;
773 soc: soc@0 {
777 ranges = <0 0 0 0 0x10 0>;
778 dma-ranges = <0 0 0 0 0x10 0>;
782 reg = <0x0 0x00100000 0x0 0x1f0000>;
797 reg = <0 0x008c0000 0 0x6000>;
804 iommus = <&apps_smmu 0x4c3 0>;
809 reg = <0 0x00880000 0 0x4000>;
813 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
814 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
815 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
818 #size-cells = <0>;
824 reg = <0 0x00880000 0 0x4000>;
828 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
829 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
832 #size-cells = <0>;
838 reg = <0 0x00880000 0 0x4000>;
842 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
843 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
850 reg = <0 0x00884000 0 0x4000>;
854 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
855 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
856 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
859 #size-cells = <0>;
865 reg = <0 0x00884000 0 0x4000>;
869 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
870 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
873 #size-cells = <0>;
879 reg = <0 0x00884000 0 0x4000>;
883 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
884 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
891 reg = <0 0x00888000 0 0x4000>;
895 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
896 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
897 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
900 #size-cells = <0>;
906 reg = <0 0x00888000 0 0x4000>;
910 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
911 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
914 #size-cells = <0>;
920 reg = <0 0x00888000 0 0x4000>;
924 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
925 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
932 reg = <0 0x0088c000 0 0x4000>;
936 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
937 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
938 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
941 #size-cells = <0>;
947 reg = <0 0x0088c000 0 0x4000>;
951 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
952 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
955 #size-cells = <0>;
961 reg = <0 0x0088c000 0 0x4000>;
965 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
966 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
973 reg = <0 0x00890000 0 0x4000>;
977 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
978 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
979 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
982 #size-cells = <0>;
988 reg = <0 0x00890000 0 0x4000>;
992 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
993 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
996 #size-cells = <0>;
1002 reg = <0 0x00890000 0 0x4000>;
1006 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1007 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1014 reg = <0 0x00894000 0 0x4000>;
1018 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1019 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1020 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1023 #size-cells = <0>;
1029 reg = <0 0x00894000 0 0x4000>;
1033 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1034 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1037 #size-cells = <0>;
1043 reg = <0 0x00894000 0 0x4000>;
1047 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1048 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1055 reg = <0 0x00898000 0 0x4000>;
1059 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1060 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1061 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1064 #size-cells = <0>;
1070 reg = <0 0x00898000 0 0x4000>;
1074 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1075 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1078 #size-cells = <0>;
1084 reg = <0 0x00898000 0 0x4000>;
1088 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1089 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1096 reg = <0 0x0089c000 0 0x4000>;
1100 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1101 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1102 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1105 #size-cells = <0>;
1111 reg = <0 0x0089c000 0 0x4000>;
1115 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1116 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1119 #size-cells = <0>;
1125 reg = <0 0x0089c000 0 0x4000>;
1129 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1130 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1138 reg = <0x0 0x00ac0000 0x0 0x6000>;
1145 iommus = <&apps_smmu 0x603 0>;
1150 reg = <0 0x00a80000 0 0x4000>;
1154 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1155 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1156 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1159 #size-cells = <0>;
1165 reg = <0 0x00a80000 0 0x4000>;
1169 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1170 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1173 #size-cells = <0>;
1179 reg = <0 0x00a80000 0 0x4000>;
1183 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1184 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1191 reg = <0 0x00a84000 0 0x4000>;
1195 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1196 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1197 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1200 #size-cells = <0>;
1206 reg = <0 0x00a84000 0 0x4000>;
1210 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1211 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1214 #size-cells = <0>;
1220 reg = <0 0x00a84000 0 0x4000>;
1224 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1225 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1232 reg = <0 0x00a88000 0 0x4000>;
1236 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1237 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1238 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1241 #size-cells = <0>;
1247 reg = <0 0x00a88000 0 0x4000>;
1251 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1252 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1255 #size-cells = <0>;
1261 reg = <0 0x00a88000 0 0x4000>;
1265 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1266 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1273 reg = <0 0x00a8c000 0 0x4000>;
1277 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1278 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1279 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1282 #size-cells = <0>;
1288 reg = <0 0x00a8c000 0 0x4000>;
1292 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1293 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1296 #size-cells = <0>;
1302 reg = <0 0x00a8c000 0 0x4000>;
1306 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1307 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1314 reg = <0 0x00a90000 0 0x4000>;
1318 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1319 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1320 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1323 #size-cells = <0>;
1329 reg = <0 0x00a90000 0 0x4000>;
1333 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1334 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1337 #size-cells = <0>;
1343 reg = <0 0x00a90000 0 0x4000>;
1347 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1348 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1355 reg = <0 0x00a94000 0 0x4000>;
1359 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1360 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1361 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1364 #size-cells = <0>;
1370 reg = <0 0x00a94000 0 0x4000>;
1374 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1375 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1378 #size-cells = <0>;
1384 reg = <0 0x00a94000 0 0x4000>;
1388 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1389 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1397 reg = <0x0 0x00cc0000 0x0 0x6000>;
1404 iommus = <&apps_smmu 0x7a3 0>;
1409 reg = <0 0x00c80000 0 0x4000>;
1413 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1414 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1415 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1418 #size-cells = <0>;
1424 reg = <0 0x00c80000 0 0x4000>;
1428 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1429 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1432 #size-cells = <0>;
1438 reg = <0 0x00c80000 0 0x4000>;
1442 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1443 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1450 reg = <0 0x00c84000 0 0x4000>;
1454 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1455 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1456 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1459 #size-cells = <0>;
1465 reg = <0 0x00c84000 0 0x4000>;
1469 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1470 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1473 #size-cells = <0>;
1479 reg = <0 0x00c84000 0 0x4000>;
1483 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1484 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1491 reg = <0 0x00c88000 0 0x4000>;
1495 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1496 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1497 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1500 #size-cells = <0>;
1506 reg = <0 0x00c88000 0 0x4000>;
1510 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1511 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1514 #size-cells = <0>;
1520 reg = <0 0x00c88000 0 0x4000>;
1524 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1525 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1532 reg = <0 0x00c8c000 0 0x4000>;
1536 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1537 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1538 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1541 #size-cells = <0>;
1547 reg = <0 0x00c8c000 0 0x4000>;
1551 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1552 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1555 #size-cells = <0>;
1561 reg = <0 0x00c8c000 0 0x4000>;
1565 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1566 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1573 reg = <0 0x00c90000 0 0x4000>;
1577 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1578 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1579 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1582 #size-cells = <0>;
1588 reg = <0 0x00c90000 0 0x4000>;
1592 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1593 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1596 #size-cells = <0>;
1602 reg = <0 0x00c90000 0 0x4000>;
1606 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1607 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1614 reg = <0 0x00c94000 0 0x4000>;
1618 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1619 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1620 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1623 #size-cells = <0>;
1629 reg = <0 0x00c94000 0 0x4000>;
1633 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1634 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1637 #size-cells = <0>;
1643 reg = <0 0x00c94000 0 0x4000>;
1647 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1648 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1656 reg = <0 0x01500000 0 0x7400>;
1663 reg = <0 0x01620000 0 0x19400>;
1670 reg = <0 0x016e0000 0 0xd080>;
1677 reg = <0 0x01700000 0 0x20000>;
1684 reg = <0 0x01720000 0 0x7000>;
1691 reg = <0 0x01740000 0 0x1c100>;
1698 reg = <0 0x01c00000 0 0x3000>,
1699 <0 0x60000000 0 0xf1d>,
1700 <0 0x60000f20 0 0xa8>,
1701 <0 0x60001000 0 0x1000>,
1702 <0 0x60100000 0 0x100000>;
1709 linux,pci-domain = <0>;
1710 bus-range = <0x00 0xff>;
1716 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
1717 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1722 interrupt-map-mask = <0 0 0 0x7>;
1723 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1724 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1725 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1726 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1748 iommus = <&apps_smmu 0x1d80 0x7f>;
1749 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1750 <0x100 &apps_smmu 0x1d81 0x1>;
1757 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
1758 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1770 reg = <0 0x01c06000 0 0x1000>;
1781 #clock-cells = <0>;
1783 #phy-cells = <0>;
1796 reg = <0 0x01c08000 0 0x3000>,
1797 <0 0x40000000 0 0xf1d>,
1798 <0 0x40000f20 0 0xa8>,
1799 <0 0x40001000 0 0x1000>,
1800 <0 0x40100000 0 0x100000>;
1808 bus-range = <0x00 0xff>;
1814 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1815 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1820 interrupt-map-mask = <0 0 0 0x7>;
1821 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1822 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1823 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1824 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1846 iommus = <&apps_smmu 0x1e00 0x7f>;
1847 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1848 <0x100 &apps_smmu 0x1e01 0x1>;
1855 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
1856 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>;
1868 reg = <0 0x01c0c000 0 0x1000>;
1879 #clock-cells = <0>;
1882 #phy-cells = <0>;
1895 reg = <0 0x01c10000 0 0x3000>,
1896 <0 0x68000000 0 0xf1d>,
1897 <0 0x68000f20 0 0xa8>,
1898 <0 0x68001000 0 0x1000>,
1899 <0 0x68100000 0 0x100000>;
1907 bus-range = <0x00 0xff>;
1913 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>,
1914 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>;
1919 interrupt-map-mask = <0 0 0 0x7>;
1920 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1921 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1922 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1923 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1945 iommus = <&apps_smmu 0x1c80 0x7f>;
1946 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1947 <0x100 &apps_smmu 0x1c81 0x1>;
1954 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
1955 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>;
1967 reg = <0 0x01c16000 0 0x1000>;
1978 #clock-cells = <0>;
1981 #phy-cells = <0>;
1994 reg = <0 0x01c18000 0 0x3000>,
1995 <0 0x70000000 0 0xf1d>,
1996 <0 0x70000f20 0 0xa8>,
1997 <0 0x70001000 0 0x1000>,
1998 <0 0x70100000 0 0x100000>;
2006 bus-range = <0x00 0xff>;
2012 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>,
2013 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
2018 interrupt-map-mask = <0 0 0 0x7>;
2019 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2020 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2021 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2022 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2044 iommus = <&apps_smmu 0x1d00 0x7f>;
2045 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2046 <0x100 &apps_smmu 0x1d01 0x1>;
2053 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2054 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>;
2066 reg = <0 0x01c1c000 0 0x1000>;
2077 #clock-cells = <0>;
2080 #phy-cells = <0>;
2094 reg = <0 0x01d84000 0 0x2500>;
2103 iommus = <&apps_smmu 0x300 0>;
2122 <0 0>,
2123 <0 0>,
2125 <0 0>,
2126 <0 0>,
2127 <0 0>,
2128 <0 0>;
2135 reg = <0 0x01d87000 0 0x1000>;
2142 resets = <&ufs_mem_hc 0>;
2147 #phy-cells = <0>;
2154 reg = <0 0x01e00000 0 0x1000>;
2161 reg = <0x0 0x01f40000 0x0 0x40000>;
2169 reg = <0 0x02c00000 0 0x40000>;
2174 iommus = <&adreno_smmu 0 0xc01>;
2178 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>;
2227 reg = <0 0x02c6a000 0 0x30000>,
2228 <0 0x0b290000 0 0x10000>,
2229 <0 0x0b490000 0 0x10000>;
2249 iommus = <&adreno_smmu 5 0xc00>;
2270 reg = <0 0x02c90000 0 0x9000>;
2285 reg = <0 0x02ca0000 0 0x10000>;
2307 reg = <0 0x03100000 0 0x300000>,
2308 <0 0x03500000 0 0x700000>,
2309 <0 0x03d00000 0 0x300000>;
2316 gpio-ranges = <&tlmm 0 0 191>;
2322 reg = <0x0 0x04080000 0x0 0x4040>;
2325 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2342 qcom,smem-states = <&modem_smp2p_out 0>;
2355 reg = <0x0 0x08300000 0x0 0x4040>;
2358 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2373 qcom,smem-states = <&cdsp_smp2p_out 0>;
2389 reg = <0 0x088e2000 0 0x400>;
2394 #phy-cells = <0>;
2402 reg = <0 0x088e3000 0 0x400>;
2407 #phy-cells = <0>;
2414 reg = <0 0x088e9000 0 0x18c>,
2415 <0 0x088e8000 0 0x38>,
2416 <0 0x088ea000 0 0x40>;
2439 #size-cells = <0>;
2441 port@0 {
2442 reg = <0>;
2455 reg = <0 0x088e9200 0 0x200>,
2456 <0 0x088e9400 0 0x200>,
2457 <0 0x088e9c00 0 0x218>,
2458 <0 0x088e9600 0 0x200>,
2459 <0 0x088e9800 0 0x200>,
2460 <0 0x088e9a00 0 0x100>;
2461 #phy-cells = <0>;
2468 reg = <0 0x088ea200 0 0x200>,
2469 <0 0x088ea400 0 0x200>,
2470 <0 0x088eaa00 0 0x200>,
2471 <0 0x088ea600 0 0x200>,
2472 <0 0x088ea800 0 0x200>;
2474 #phy-cells = <0>;
2480 reg = <0 0x088ee000 0 0x18c>,
2481 <0 0x088ed000 0 0x10>,
2482 <0 0x088ef000 0 0x40>;
2505 #size-cells = <0>;
2507 port@0 {
2508 reg = <0>;
2521 reg = <0 0x088ee200 0 0x200>,
2522 <0 0x088ee400 0 0x200>,
2523 <0 0x088eec00 0 0x218>,
2524 <0 0x088ee600 0 0x200>,
2525 <0 0x088ee800 0 0x200>,
2526 <0 0x088eea00 0 0x100>;
2527 #phy-cells = <0>;
2534 reg = <0 0x088ef200 0 0x200>,
2535 <0 0x088ef400 0 0x200>,
2536 <0 0x088efa00 0 0x200>,
2537 <0 0x088ef600 0 0x200>,
2538 <0 0x088ef800 0 0x200>;
2540 #phy-cells = <0>;
2548 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2549 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2550 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
2551 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
2552 <0 0x09600000 0 0x58000>;
2561 reg = <0 0x09680000 0 0x58200>;
2568 reg = <0 0x0a6f8800 0 0x400>;
2593 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
2594 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
2610 reg = <0 0x0a600000 0 0xcd00>;
2612 iommus = <&apps_smmu 0x140 0>;
2627 reg = <0 0x0a8f8800 0 0x400>;
2654 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
2655 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
2667 reg = <0 0x0a800000 0 0xcd00>;
2669 iommus = <&apps_smmu 0x160 0>;
2684 reg = <0 0x0ae00000 0 0x1000>;
2704 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
2705 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
2708 iommus = <&apps_smmu 0x800 0x420>;
2718 reg = <0 0x0ae01000 0 0x8f000>,
2719 <0 0x0aeb0000 0 0x2008>;
2738 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2742 #size-cells = <0>;
2744 port@0 {
2745 reg = <0>;
2807 reg = <0 0x0ae94000 0 0x400>;
2836 #size-cells = <0>;
2838 port@0 {
2839 reg = <0>;
2874 reg = <0 0x0ae94400 0 0x200>,
2875 <0 0x0ae94600 0 0x280>,
2876 <0 0x0ae94900 0 0x260>;
2882 #phy-cells = <0>;
2893 reg = <0 0x0ae96000 0 0x400>;
2922 #size-cells = <0>;
2924 port@0 {
2925 reg = <0>;
2941 reg = <0 0x0ae96400 0 0x200>,
2942 <0 0x0ae96600 0 0x280>,
2943 <0 0x0ae96900 0 0x260>;
2949 #phy-cells = <0>;
2960 reg = <0 0xae90000 0 0x200>,
2961 <0 0xae90200 0 0x200>,
2962 <0 0xae90400 0 0x600>,
2963 <0 0xae90a00 0 0x400>;
2979 assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>;
2984 #sound-dai-cells = <0>;
2993 #size-cells = <0>;
2995 port@0 {
2996 reg = <0>;
3036 reg = <0 0xae98000 0 0x200>,
3037 <0 0xae98200 0 0x200>,
3038 <0 0xae98400 0 0x600>,
3039 <0 0xae98a00 0 0x400>;
3055 assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>;
3060 #sound-dai-cells = <0>;
3069 #size-cells = <0>;
3071 port@0 {
3072 reg = <0>;
3112 reg = <0 0xae9a000 0 0x200>,
3113 <0 0xae9a200 0 0x200>,
3114 <0 0xae9a400 0 0x600>,
3115 <0 0xae9aa00 0 0x400>;
3131 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3136 #sound-dai-cells = <0>;
3145 #size-cells = <0>;
3147 port@0 {
3148 reg = <0>;
3183 reg = <0 0x0aec2a00 0 0x1c0>,
3184 <0 0x0aec2200 0 0xa0>,
3185 <0 0x0aec2600 0 0xa0>,
3186 <0 0x0aec2000 0 0x19c>;
3195 #phy-cells = <0>;
3200 reg = <0 0x0af00000 0 0x20000>;
3203 <&usb_prim_dpphy 0>,
3205 <&usb_sec_dpphy 0>,
3207 <&edp_phy 0>,
3226 reg = <0 0x0b220000 0 0x30000>;
3227 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3235 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3236 <0 0x0c222000 0 0x1ff>; /* SROT */
3246 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3247 <0 0x0c223000 0 0x1ff>; /* SROT */
3257 reg = <0x0 0x0c300000 0x0 0x400>;
3259 mboxes = <&apss_shared 0>;
3261 #clock-cells = <0>;
3267 reg = <0x0 0x0c440000 0x0 0x0001100>,
3268 <0x0 0x0c600000 0x0 0x2000000>,
3269 <0x0 0x0e600000 0x0 0x0100000>,
3270 <0x0 0x0e700000 0x0 0x00a0000>,
3271 <0x0 0x0c40a000 0x0 0x0026000>;
3275 qcom,ee = <0>;
3276 qcom,channel = <0>;
3278 #size-cells = <0>;
3281 cell-index = <0>;
3286 reg = <0 0x15000000 0 0x100000>;
3401 reg = <0x0 0x17300000 0x0 0x4040>;
3404 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3419 qcom,smem-states = <&adsp_smp2p_out 0>;
3436 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3437 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3443 reg = <0x0 0x17c00000 0x0 0x1000>;
3449 reg = <0x0 0x17c20000 0x0 0x1000>;
3453 ranges = <0 0 0 0x20000000>;
3456 reg = <0x17c21000 0x1000>,
3457 <0x17c22000 0x1000>;
3458 frame-number = <0>;
3464 reg = <0x17c23000 0x1000>;
3471 reg = <0x17c25000 0x1000>;
3478 reg = <0x17c26000 0x1000>;
3485 reg = <0x17c29000 0x1000>;
3492 reg = <0x17c2b000 0x1000>;
3499 reg = <0x17c2d000 0x1000>;
3508 reg = <0x0 0x18200000 0x0 0x10000>,
3509 <0x0 0x18210000 0x0 0x10000>,
3510 <0x0 0x18220000 0x0 0x10000>;
3511 reg-names = "drv-0", "drv-1", "drv-2";
3515 qcom,tcs-offset = <0xd00>;
3520 <CONTROL_TCS 0>;
3588 reg = <0 0x18321000 0 0x1400>;
3598 reg = <0 0x18350800 0 0x400>;
3610 reg = <0 0x18358800 0 0x400>;
3622 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3634 reg = <0 0x18800000 0 0x800000>;
3650 iommus = <&apps_smmu 0x0640 0x1>;
3841 thermal-sensors = <&tsens0 0>;
3901 thermal-sensors = <&tsens1 0>;
4053 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;