Lines Matching +full:sdm845 +full:- +full:dispcc
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sc7180.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/phy/phy-qcom-qmp.h>
19 #include <dt-bindings/phy/phy-qcom-qusb2.h>
20 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
22 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
24 #include <dt-bindings/thermal/thermal.h>
27 interrupt-parent = <&intc>;
29 #address-cells = <2>;
30 #size-cells = <2>;
60 xo_board: xo-board {
61 compatible = "fixed-clock";
62 clock-frequency = <38400000>;
63 #clock-cells = <0>;
66 sleep_clk: sleep-clk {
67 compatible = "fixed-clock";
68 clock-frequency = <32764>;
69 #clock-cells = <0>;
74 #address-cells = <2>;
75 #size-cells = <0>;
82 enable-method = "psci";
83 power-domains = <&CPU_PD0>;
84 power-domain-names = "psci";
85 capacity-dmips-mhz = <415>;
86 dynamic-power-coefficient = <137>;
87 operating-points-v2 = <&cpu0_opp_table>;
90 next-level-cache = <&L2_0>;
91 #cooling-cells = <2>;
92 qcom,freq-domain = <&cpufreq_hw 0>;
93 L2_0: l2-cache {
95 cache-level = <2>;
96 cache-unified;
97 next-level-cache = <&L3_0>;
98 L3_0: l3-cache {
100 cache-level = <3>;
101 cache-unified;
111 enable-method = "psci";
112 power-domains = <&CPU_PD1>;
113 power-domain-names = "psci";
114 capacity-dmips-mhz = <415>;
115 dynamic-power-coefficient = <137>;
116 next-level-cache = <&L2_100>;
117 operating-points-v2 = <&cpu0_opp_table>;
120 #cooling-cells = <2>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
122 L2_100: l2-cache {
124 cache-level = <2>;
125 cache-unified;
126 next-level-cache = <&L3_0>;
135 enable-method = "psci";
136 power-domains = <&CPU_PD2>;
137 power-domain-names = "psci";
138 capacity-dmips-mhz = <415>;
139 dynamic-power-coefficient = <137>;
140 next-level-cache = <&L2_200>;
141 operating-points-v2 = <&cpu0_opp_table>;
144 #cooling-cells = <2>;
145 qcom,freq-domain = <&cpufreq_hw 0>;
146 L2_200: l2-cache {
148 cache-level = <2>;
149 cache-unified;
150 next-level-cache = <&L3_0>;
159 enable-method = "psci";
160 power-domains = <&CPU_PD3>;
161 power-domain-names = "psci";
162 capacity-dmips-mhz = <415>;
163 dynamic-power-coefficient = <137>;
164 next-level-cache = <&L2_300>;
165 operating-points-v2 = <&cpu0_opp_table>;
168 #cooling-cells = <2>;
169 qcom,freq-domain = <&cpufreq_hw 0>;
170 L2_300: l2-cache {
172 cache-level = <2>;
173 cache-unified;
174 next-level-cache = <&L3_0>;
183 enable-method = "psci";
184 power-domains = <&CPU_PD4>;
185 power-domain-names = "psci";
186 capacity-dmips-mhz = <415>;
187 dynamic-power-coefficient = <137>;
188 next-level-cache = <&L2_400>;
189 operating-points-v2 = <&cpu0_opp_table>;
192 #cooling-cells = <2>;
193 qcom,freq-domain = <&cpufreq_hw 0>;
194 L2_400: l2-cache {
196 cache-level = <2>;
197 cache-unified;
198 next-level-cache = <&L3_0>;
207 enable-method = "psci";
208 power-domains = <&CPU_PD5>;
209 power-domain-names = "psci";
210 capacity-dmips-mhz = <415>;
211 dynamic-power-coefficient = <137>;
212 next-level-cache = <&L2_500>;
213 operating-points-v2 = <&cpu0_opp_table>;
216 #cooling-cells = <2>;
217 qcom,freq-domain = <&cpufreq_hw 0>;
218 L2_500: l2-cache {
220 cache-level = <2>;
221 cache-unified;
222 next-level-cache = <&L3_0>;
231 enable-method = "psci";
232 power-domains = <&CPU_PD6>;
233 power-domain-names = "psci";
234 capacity-dmips-mhz = <1024>;
235 dynamic-power-coefficient = <480>;
236 next-level-cache = <&L2_600>;
237 operating-points-v2 = <&cpu6_opp_table>;
240 #cooling-cells = <2>;
241 qcom,freq-domain = <&cpufreq_hw 1>;
242 L2_600: l2-cache {
244 cache-level = <2>;
245 cache-unified;
246 next-level-cache = <&L3_0>;
255 enable-method = "psci";
256 power-domains = <&CPU_PD7>;
257 power-domain-names = "psci";
258 capacity-dmips-mhz = <1024>;
259 dynamic-power-coefficient = <480>;
260 next-level-cache = <&L2_700>;
261 operating-points-v2 = <&cpu6_opp_table>;
264 #cooling-cells = <2>;
265 qcom,freq-domain = <&cpufreq_hw 1>;
266 L2_700: l2-cache {
268 cache-level = <2>;
269 cache-unified;
270 next-level-cache = <&L3_0>;
274 cpu-map {
310 idle_states: idle-states {
311 entry-method = "psci";
313 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
314 compatible = "arm,idle-state";
315 idle-state-name = "little-power-down";
316 arm,psci-suspend-param = <0x40000003>;
317 entry-latency-us = <549>;
318 exit-latency-us = <901>;
319 min-residency-us = <1774>;
320 local-timer-stop;
323 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
324 compatible = "arm,idle-state";
325 idle-state-name = "little-rail-power-down";
326 arm,psci-suspend-param = <0x40000004>;
327 entry-latency-us = <702>;
328 exit-latency-us = <915>;
329 min-residency-us = <4001>;
330 local-timer-stop;
333 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
334 compatible = "arm,idle-state";
335 idle-state-name = "big-power-down";
336 arm,psci-suspend-param = <0x40000003>;
337 entry-latency-us = <523>;
338 exit-latency-us = <1244>;
339 min-residency-us = <2207>;
340 local-timer-stop;
343 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
344 compatible = "arm,idle-state";
345 idle-state-name = "big-rail-power-down";
346 arm,psci-suspend-param = <0x40000004>;
347 entry-latency-us = <526>;
348 exit-latency-us = <1854>;
349 min-residency-us = <5555>;
350 local-timer-stop;
354 domain_idle_states: domain-idle-states {
355 CLUSTER_SLEEP_PC: cluster-sleep-0 {
356 compatible = "domain-idle-state";
357 idle-state-name = "cluster-l3-power-collapse";
358 arm,psci-suspend-param = <0x41000044>;
359 entry-latency-us = <2752>;
360 exit-latency-us = <3048>;
361 min-residency-us = <6118>;
364 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
365 compatible = "domain-idle-state";
366 idle-state-name = "cluster-cx-retention";
367 arm,psci-suspend-param = <0x41001244>;
368 entry-latency-us = <3638>;
369 exit-latency-us = <4562>;
370 min-residency-us = <8467>;
373 CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
374 compatible = "domain-idle-state";
375 idle-state-name = "cluster-power-down";
376 arm,psci-suspend-param = <0x4100b244>;
377 entry-latency-us = <3263>;
378 exit-latency-us = <6562>;
379 min-residency-us = <9826>;
386 compatible = "qcom,scm-sc7180", "qcom,scm";
396 cpu0_opp_table: opp-table-cpu0 {
397 compatible = "operating-points-v2";
398 opp-shared;
400 cpu0_opp1: opp-300000000 {
401 opp-hz = /bits/ 64 <300000000>;
402 opp-peak-kBps = <1200000 4800000>;
405 cpu0_opp2: opp-576000000 {
406 opp-hz = /bits/ 64 <576000000>;
407 opp-peak-kBps = <1200000 4800000>;
410 cpu0_opp3: opp-768000000 {
411 opp-hz = /bits/ 64 <768000000>;
412 opp-peak-kBps = <1200000 4800000>;
415 cpu0_opp4: opp-1017600000 {
416 opp-hz = /bits/ 64 <1017600000>;
417 opp-peak-kBps = <1804000 8908800>;
420 cpu0_opp5: opp-1248000000 {
421 opp-hz = /bits/ 64 <1248000000>;
422 opp-peak-kBps = <2188000 12902400>;
425 cpu0_opp6: opp-1324800000 {
426 opp-hz = /bits/ 64 <1324800000>;
427 opp-peak-kBps = <2188000 12902400>;
430 cpu0_opp7: opp-1516800000 {
431 opp-hz = /bits/ 64 <1516800000>;
432 opp-peak-kBps = <3072000 15052800>;
435 cpu0_opp8: opp-1612800000 {
436 opp-hz = /bits/ 64 <1612800000>;
437 opp-peak-kBps = <3072000 15052800>;
440 cpu0_opp9: opp-1708800000 {
441 opp-hz = /bits/ 64 <1708800000>;
442 opp-peak-kBps = <3072000 15052800>;
445 cpu0_opp10: opp-1804800000 {
446 opp-hz = /bits/ 64 <1804800000>;
447 opp-peak-kBps = <4068000 22425600>;
451 cpu6_opp_table: opp-table-cpu6 {
452 compatible = "operating-points-v2";
453 opp-shared;
455 cpu6_opp1: opp-300000000 {
456 opp-hz = /bits/ 64 <300000000>;
457 opp-peak-kBps = <2188000 8908800>;
460 cpu6_opp2: opp-652800000 {
461 opp-hz = /bits/ 64 <652800000>;
462 opp-peak-kBps = <2188000 8908800>;
465 cpu6_opp3: opp-825600000 {
466 opp-hz = /bits/ 64 <825600000>;
467 opp-peak-kBps = <2188000 8908800>;
470 cpu6_opp4: opp-979200000 {
471 opp-hz = /bits/ 64 <979200000>;
472 opp-peak-kBps = <2188000 8908800>;
475 cpu6_opp5: opp-1113600000 {
476 opp-hz = /bits/ 64 <1113600000>;
477 opp-peak-kBps = <2188000 8908800>;
480 cpu6_opp6: opp-1267200000 {
481 opp-hz = /bits/ 64 <1267200000>;
482 opp-peak-kBps = <4068000 12902400>;
485 cpu6_opp7: opp-1555200000 {
486 opp-hz = /bits/ 64 <1555200000>;
487 opp-peak-kBps = <4068000 15052800>;
490 cpu6_opp8: opp-1708800000 {
491 opp-hz = /bits/ 64 <1708800000>;
492 opp-peak-kBps = <6220000 19353600>;
495 cpu6_opp9: opp-1843200000 {
496 opp-hz = /bits/ 64 <1843200000>;
497 opp-peak-kBps = <6220000 19353600>;
500 cpu6_opp10: opp-1900800000 {
501 opp-hz = /bits/ 64 <1900800000>;
502 opp-peak-kBps = <6220000 22425600>;
505 cpu6_opp11: opp-1996800000 {
506 opp-hz = /bits/ 64 <1996800000>;
507 opp-peak-kBps = <6220000 22425600>;
510 cpu6_opp12: opp-2112000000 {
511 opp-hz = /bits/ 64 <2112000000>;
512 opp-peak-kBps = <6220000 22425600>;
515 cpu6_opp13: opp-2208000000 {
516 opp-hz = /bits/ 64 <2208000000>;
517 opp-peak-kBps = <7216000 22425600>;
520 cpu6_opp14: opp-2323200000 {
521 opp-hz = /bits/ 64 <2323200000>;
522 opp-peak-kBps = <7216000 22425600>;
525 cpu6_opp15: opp-2400000000 {
526 opp-hz = /bits/ 64 <2400000000>;
527 opp-peak-kBps = <8532000 23347200>;
530 cpu6_opp16: opp-2553600000 {
531 opp-hz = /bits/ 64 <2553600000>;
532 opp-peak-kBps = <8532000 23347200>;
536 qspi_opp_table: opp-table-qspi {
537 compatible = "operating-points-v2";
539 opp-75000000 {
540 opp-hz = /bits/ 64 <75000000>;
541 required-opps = <&rpmhpd_opp_low_svs>;
544 opp-150000000 {
545 opp-hz = /bits/ 64 <150000000>;
546 required-opps = <&rpmhpd_opp_svs>;
549 opp-300000000 {
550 opp-hz = /bits/ 64 <300000000>;
551 required-opps = <&rpmhpd_opp_nom>;
555 qup_opp_table: opp-table-qup {
556 compatible = "operating-points-v2";
558 opp-75000000 {
559 opp-hz = /bits/ 64 <75000000>;
560 required-opps = <&rpmhpd_opp_low_svs>;
563 opp-100000000 {
564 opp-hz = /bits/ 64 <100000000>;
565 required-opps = <&rpmhpd_opp_svs>;
568 opp-128000000 {
569 opp-hz = /bits/ 64 <128000000>;
570 required-opps = <&rpmhpd_opp_nom>;
575 compatible = "arm,armv8-pmuv3";
580 compatible = "arm,psci-1.0";
584 #power-domain-cells = <0>;
585 power-domains = <&CLUSTER_PD>;
586 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
590 #power-domain-cells = <0>;
591 power-domains = <&CLUSTER_PD>;
592 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
596 #power-domain-cells = <0>;
597 power-domains = <&CLUSTER_PD>;
598 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
602 #power-domain-cells = <0>;
603 power-domains = <&CLUSTER_PD>;
604 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
608 #power-domain-cells = <0>;
609 power-domains = <&CLUSTER_PD>;
610 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
614 #power-domain-cells = <0>;
615 power-domains = <&CLUSTER_PD>;
616 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
620 #power-domain-cells = <0>;
621 power-domains = <&CLUSTER_PD>;
622 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
626 #power-domain-cells = <0>;
627 power-domains = <&CLUSTER_PD>;
628 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
631 CLUSTER_PD: cpu-cluster0 {
632 #power-domain-cells = <0>;
633 domain-idle-states = <&CLUSTER_SLEEP_PC
639 reserved_memory: reserved-memory {
640 #address-cells = <2>;
641 #size-cells = <2>;
646 no-map;
651 no-map;
656 no-map;
661 compatible = "qcom,cmd-db";
662 no-map;
667 no-map;
672 no-map;
677 no-map;
682 no-map;
686 compatible = "qcom,rmtfs-mem";
688 no-map;
690 qcom,client-id = <1>;
697 memory-region = <&smem_mem>;
701 smp2p-cdsp {
709 qcom,local-pid = <0>;
710 qcom,remote-pid = <5>;
712 cdsp_smp2p_out: master-kernel {
713 qcom,entry-name = "master-kernel";
714 #qcom,smem-state-cells = <1>;
717 cdsp_smp2p_in: slave-kernel {
718 qcom,entry-name = "slave-kernel";
720 interrupt-controller;
721 #interrupt-cells = <2>;
725 smp2p-lpass {
733 qcom,local-pid = <0>;
734 qcom,remote-pid = <2>;
736 adsp_smp2p_out: master-kernel {
737 qcom,entry-name = "master-kernel";
738 #qcom,smem-state-cells = <1>;
741 adsp_smp2p_in: slave-kernel {
742 qcom,entry-name = "slave-kernel";
744 interrupt-controller;
745 #interrupt-cells = <2>;
749 smp2p-mpss {
754 qcom,local-pid = <0>;
755 qcom,remote-pid = <1>;
757 modem_smp2p_out: master-kernel {
758 qcom,entry-name = "master-kernel";
759 #qcom,smem-state-cells = <1>;
762 modem_smp2p_in: slave-kernel {
763 qcom,entry-name = "slave-kernel";
764 interrupt-controller;
765 #interrupt-cells = <2>;
768 ipa_smp2p_out: ipa-ap-to-modem {
769 qcom,entry-name = "ipa";
770 #qcom,smem-state-cells = <1>;
773 ipa_smp2p_in: ipa-modem-to-ap {
774 qcom,entry-name = "ipa";
775 interrupt-controller;
776 #interrupt-cells = <2>;
781 #address-cells = <2>;
782 #size-cells = <2>;
784 dma-ranges = <0 0 0 0 0x10 0>;
785 compatible = "simple-bus";
787 gcc: clock-controller@100000 {
788 compatible = "qcom,gcc-sc7180";
793 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
794 #clock-cells = <1>;
795 #reset-cells = <1>;
796 #power-domain-cells = <1>;
797 power-domains = <&rpmhpd SC7180_CX>;
801 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
808 clock-names = "core";
809 #address-cells = <1>;
810 #size-cells = <1>;
812 qusb2p_hstx_trim: hstx-trim-primary@25b {
824 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
827 reg-names = "hc", "cqhci";
832 interrupt-names = "hc_irq", "pwr_irq";
837 clock-names = "iface", "core", "xo";
840 interconnect-names = "sdhc-ddr","cpu-sdhc";
841 power-domains = <&rpmhpd SC7180_CX>;
842 operating-points-v2 = <&sdhc1_opp_table>;
844 bus-width = <8>;
845 non-removable;
846 supports-cqe;
848 mmc-ddr-1_8v;
849 mmc-hs200-1_8v;
850 mmc-hs400-1_8v;
851 mmc-hs400-enhanced-strobe;
855 sdhc1_opp_table: opp-table {
856 compatible = "operating-points-v2";
858 opp-100000000 {
859 opp-hz = /bits/ 64 <100000000>;
860 required-opps = <&rpmhpd_opp_low_svs>;
861 opp-peak-kBps = <1800000 600000>;
862 opp-avg-kBps = <100000 0>;
865 opp-384000000 {
866 opp-hz = /bits/ 64 <384000000>;
867 required-opps = <&rpmhpd_opp_nom>;
868 opp-peak-kBps = <5400000 1600000>;
869 opp-avg-kBps = <390000 0>;
875 compatible = "qcom,geni-se-qup";
877 clock-names = "m-ahb", "s-ahb";
880 #address-cells = <2>;
881 #size-cells = <2>;
887 compatible = "qcom,geni-i2c";
889 clock-names = "se";
891 pinctrl-names = "default";
892 pinctrl-0 = <&qup_i2c0_default>;
894 #address-cells = <1>;
895 #size-cells = <0>;
899 interconnect-names = "qup-core", "qup-config",
900 "qup-memory";
901 power-domains = <&rpmhpd SC7180_CX>;
902 required-opps = <&rpmhpd_opp_low_svs>;
907 compatible = "qcom,geni-spi";
909 clock-names = "se";
911 pinctrl-names = "default";
912 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
914 #address-cells = <1>;
915 #size-cells = <0>;
916 power-domains = <&rpmhpd SC7180_CX>;
917 operating-points-v2 = <&qup_opp_table>;
920 interconnect-names = "qup-core", "qup-config";
925 compatible = "qcom,geni-uart";
927 clock-names = "se";
929 pinctrl-names = "default";
930 pinctrl-0 = <&qup_uart0_default>;
932 power-domains = <&rpmhpd SC7180_CX>;
933 operating-points-v2 = <&qup_opp_table>;
936 interconnect-names = "qup-core", "qup-config";
941 compatible = "qcom,geni-i2c";
943 clock-names = "se";
945 pinctrl-names = "default";
946 pinctrl-0 = <&qup_i2c1_default>;
948 #address-cells = <1>;
949 #size-cells = <0>;
953 interconnect-names = "qup-core", "qup-config",
954 "qup-memory";
955 power-domains = <&rpmhpd SC7180_CX>;
956 required-opps = <&rpmhpd_opp_low_svs>;
961 compatible = "qcom,geni-spi";
963 clock-names = "se";
965 pinctrl-names = "default";
966 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
968 #address-cells = <1>;
969 #size-cells = <0>;
970 power-domains = <&rpmhpd SC7180_CX>;
971 operating-points-v2 = <&qup_opp_table>;
974 interconnect-names = "qup-core", "qup-config";
979 compatible = "qcom,geni-uart";
981 clock-names = "se";
983 pinctrl-names = "default";
984 pinctrl-0 = <&qup_uart1_default>;
986 power-domains = <&rpmhpd SC7180_CX>;
987 operating-points-v2 = <&qup_opp_table>;
990 interconnect-names = "qup-core", "qup-config";
995 compatible = "qcom,geni-i2c";
997 clock-names = "se";
999 pinctrl-names = "default";
1000 pinctrl-0 = <&qup_i2c2_default>;
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1007 interconnect-names = "qup-core", "qup-config",
1008 "qup-memory";
1009 power-domains = <&rpmhpd SC7180_CX>;
1010 required-opps = <&rpmhpd_opp_low_svs>;
1015 compatible = "qcom,geni-uart";
1017 clock-names = "se";
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&qup_uart2_default>;
1022 power-domains = <&rpmhpd SC7180_CX>;
1023 operating-points-v2 = <&qup_opp_table>;
1026 interconnect-names = "qup-core", "qup-config";
1031 compatible = "qcom,geni-i2c";
1033 clock-names = "se";
1035 pinctrl-names = "default";
1036 pinctrl-0 = <&qup_i2c3_default>;
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1043 interconnect-names = "qup-core", "qup-config",
1044 "qup-memory";
1045 power-domains = <&rpmhpd SC7180_CX>;
1046 required-opps = <&rpmhpd_opp_low_svs>;
1051 compatible = "qcom,geni-spi";
1053 clock-names = "se";
1055 pinctrl-names = "default";
1056 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1060 power-domains = <&rpmhpd SC7180_CX>;
1061 operating-points-v2 = <&qup_opp_table>;
1064 interconnect-names = "qup-core", "qup-config";
1069 compatible = "qcom,geni-uart";
1071 clock-names = "se";
1073 pinctrl-names = "default";
1074 pinctrl-0 = <&qup_uart3_default>;
1076 power-domains = <&rpmhpd SC7180_CX>;
1077 operating-points-v2 = <&qup_opp_table>;
1080 interconnect-names = "qup-core", "qup-config";
1085 compatible = "qcom,geni-i2c";
1087 clock-names = "se";
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&qup_i2c4_default>;
1092 #address-cells = <1>;
1093 #size-cells = <0>;
1097 interconnect-names = "qup-core", "qup-config",
1098 "qup-memory";
1099 power-domains = <&rpmhpd SC7180_CX>;
1100 required-opps = <&rpmhpd_opp_low_svs>;
1105 compatible = "qcom,geni-uart";
1107 clock-names = "se";
1109 pinctrl-names = "default";
1110 pinctrl-0 = <&qup_uart4_default>;
1112 power-domains = <&rpmhpd SC7180_CX>;
1113 operating-points-v2 = <&qup_opp_table>;
1116 interconnect-names = "qup-core", "qup-config";
1121 compatible = "qcom,geni-i2c";
1123 clock-names = "se";
1125 pinctrl-names = "default";
1126 pinctrl-0 = <&qup_i2c5_default>;
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1133 interconnect-names = "qup-core", "qup-config",
1134 "qup-memory";
1135 power-domains = <&rpmhpd SC7180_CX>;
1136 required-opps = <&rpmhpd_opp_low_svs>;
1141 compatible = "qcom,geni-spi";
1143 clock-names = "se";
1145 pinctrl-names = "default";
1146 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1148 #address-cells = <1>;
1149 #size-cells = <0>;
1150 power-domains = <&rpmhpd SC7180_CX>;
1151 operating-points-v2 = <&qup_opp_table>;
1154 interconnect-names = "qup-core", "qup-config";
1159 compatible = "qcom,geni-uart";
1161 clock-names = "se";
1163 pinctrl-names = "default";
1164 pinctrl-0 = <&qup_uart5_default>;
1166 power-domains = <&rpmhpd SC7180_CX>;
1167 operating-points-v2 = <&qup_opp_table>;
1170 interconnect-names = "qup-core", "qup-config";
1176 compatible = "qcom,geni-se-qup";
1178 clock-names = "m-ahb", "s-ahb";
1181 #address-cells = <2>;
1182 #size-cells = <2>;
1188 compatible = "qcom,geni-i2c";
1190 clock-names = "se";
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&qup_i2c6_default>;
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1200 interconnect-names = "qup-core", "qup-config",
1201 "qup-memory";
1202 power-domains = <&rpmhpd SC7180_CX>;
1203 required-opps = <&rpmhpd_opp_low_svs>;
1208 compatible = "qcom,geni-spi";
1210 clock-names = "se";
1212 pinctrl-names = "default";
1213 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1217 power-domains = <&rpmhpd SC7180_CX>;
1218 operating-points-v2 = <&qup_opp_table>;
1221 interconnect-names = "qup-core", "qup-config";
1226 compatible = "qcom,geni-uart";
1228 clock-names = "se";
1230 pinctrl-names = "default";
1231 pinctrl-0 = <&qup_uart6_default>;
1233 power-domains = <&rpmhpd SC7180_CX>;
1234 operating-points-v2 = <&qup_opp_table>;
1237 interconnect-names = "qup-core", "qup-config";
1242 compatible = "qcom,geni-i2c";
1244 clock-names = "se";
1246 pinctrl-names = "default";
1247 pinctrl-0 = <&qup_i2c7_default>;
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1254 interconnect-names = "qup-core", "qup-config",
1255 "qup-memory";
1256 power-domains = <&rpmhpd SC7180_CX>;
1257 required-opps = <&rpmhpd_opp_low_svs>;
1262 compatible = "qcom,geni-uart";
1264 clock-names = "se";
1266 pinctrl-names = "default";
1267 pinctrl-0 = <&qup_uart7_default>;
1269 power-domains = <&rpmhpd SC7180_CX>;
1270 operating-points-v2 = <&qup_opp_table>;
1273 interconnect-names = "qup-core", "qup-config";
1278 compatible = "qcom,geni-i2c";
1280 clock-names = "se";
1282 pinctrl-names = "default";
1283 pinctrl-0 = <&qup_i2c8_default>;
1285 #address-cells = <1>;
1286 #size-cells = <0>;
1290 interconnect-names = "qup-core", "qup-config",
1291 "qup-memory";
1292 power-domains = <&rpmhpd SC7180_CX>;
1293 required-opps = <&rpmhpd_opp_low_svs>;
1298 compatible = "qcom,geni-spi";
1300 clock-names = "se";
1302 pinctrl-names = "default";
1303 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1305 #address-cells = <1>;
1306 #size-cells = <0>;
1307 power-domains = <&rpmhpd SC7180_CX>;
1308 operating-points-v2 = <&qup_opp_table>;
1311 interconnect-names = "qup-core", "qup-config";
1316 compatible = "qcom,geni-debug-uart";
1318 clock-names = "se";
1320 pinctrl-names = "default";
1321 pinctrl-0 = <&qup_uart8_default>;
1323 power-domains = <&rpmhpd SC7180_CX>;
1324 operating-points-v2 = <&qup_opp_table>;
1327 interconnect-names = "qup-core", "qup-config";
1332 compatible = "qcom,geni-i2c";
1334 clock-names = "se";
1336 pinctrl-names = "default";
1337 pinctrl-0 = <&qup_i2c9_default>;
1339 #address-cells = <1>;
1340 #size-cells = <0>;
1344 interconnect-names = "qup-core", "qup-config",
1345 "qup-memory";
1346 power-domains = <&rpmhpd SC7180_CX>;
1347 required-opps = <&rpmhpd_opp_low_svs>;
1352 compatible = "qcom,geni-uart";
1354 clock-names = "se";
1356 pinctrl-names = "default";
1357 pinctrl-0 = <&qup_uart9_default>;
1359 power-domains = <&rpmhpd SC7180_CX>;
1360 operating-points-v2 = <&qup_opp_table>;
1363 interconnect-names = "qup-core", "qup-config";
1368 compatible = "qcom,geni-i2c";
1370 clock-names = "se";
1372 pinctrl-names = "default";
1373 pinctrl-0 = <&qup_i2c10_default>;
1375 #address-cells = <1>;
1376 #size-cells = <0>;
1380 interconnect-names = "qup-core", "qup-config",
1381 "qup-memory";
1382 power-domains = <&rpmhpd SC7180_CX>;
1383 required-opps = <&rpmhpd_opp_low_svs>;
1388 compatible = "qcom,geni-spi";
1390 clock-names = "se";
1392 pinctrl-names = "default";
1393 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1395 #address-cells = <1>;
1396 #size-cells = <0>;
1397 power-domains = <&rpmhpd SC7180_CX>;
1398 operating-points-v2 = <&qup_opp_table>;
1401 interconnect-names = "qup-core", "qup-config";
1406 compatible = "qcom,geni-uart";
1408 clock-names = "se";
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&qup_uart10_default>;
1413 power-domains = <&rpmhpd SC7180_CX>;
1414 operating-points-v2 = <&qup_opp_table>;
1417 interconnect-names = "qup-core", "qup-config";
1422 compatible = "qcom,geni-i2c";
1424 clock-names = "se";
1426 pinctrl-names = "default";
1427 pinctrl-0 = <&qup_i2c11_default>;
1429 #address-cells = <1>;
1430 #size-cells = <0>;
1434 interconnect-names = "qup-core", "qup-config",
1435 "qup-memory";
1436 power-domains = <&rpmhpd SC7180_CX>;
1437 required-opps = <&rpmhpd_opp_low_svs>;
1442 compatible = "qcom,geni-spi";
1444 clock-names = "se";
1446 pinctrl-names = "default";
1447 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1451 power-domains = <&rpmhpd SC7180_CX>;
1452 operating-points-v2 = <&qup_opp_table>;
1455 interconnect-names = "qup-core", "qup-config";
1460 compatible = "qcom,geni-uart";
1462 clock-names = "se";
1464 pinctrl-names = "default";
1465 pinctrl-0 = <&qup_uart11_default>;
1467 power-domains = <&rpmhpd SC7180_CX>;
1468 operating-points-v2 = <&qup_opp_table>;
1471 interconnect-names = "qup-core", "qup-config";
1477 compatible = "qcom,sc7180-config-noc";
1479 #interconnect-cells = <2>;
1480 qcom,bcm-voters = <&apps_bcm_voter>;
1484 compatible = "qcom,sc7180-system-noc";
1486 #interconnect-cells = <2>;
1487 qcom,bcm-voters = <&apps_bcm_voter>;
1491 compatible = "qcom,sc7180-mc-virt";
1493 #interconnect-cells = <2>;
1494 qcom,bcm-voters = <&apps_bcm_voter>;
1498 compatible = "qcom,sc7180-qup-virt";
1500 #interconnect-cells = <2>;
1501 qcom,bcm-voters = <&apps_bcm_voter>;
1505 compatible = "qcom,sc7180-aggre1-noc";
1507 #interconnect-cells = <2>;
1508 qcom,bcm-voters = <&apps_bcm_voter>;
1512 compatible = "qcom,sc7180-aggre2-noc";
1514 #interconnect-cells = <2>;
1515 qcom,bcm-voters = <&apps_bcm_voter>;
1519 compatible = "qcom,sc7180-compute-noc";
1521 #interconnect-cells = <2>;
1522 qcom,bcm-voters = <&apps_bcm_voter>;
1526 compatible = "qcom,sc7180-mmss-noc";
1528 #interconnect-cells = <2>;
1529 qcom,bcm-voters = <&apps_bcm_voter>;
1533 compatible = "qcom,sc7180-ipa";
1540 reg-names = "ipa-reg",
1541 "ipa-shared",
1544 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1548 interrupt-names = "ipa",
1550 "ipa-clock-query",
1551 "ipa-setup-ready";
1554 clock-names = "core";
1559 interconnect-names = "memory",
1565 qcom,smem-states = <&ipa_smp2p_out 0>,
1567 qcom,smem-state-names = "ipa-clock-enabled-valid",
1568 "ipa-clock-enabled";
1574 compatible = "qcom,tcsr-mutex";
1576 #hwlock-cells = <1>;
1580 compatible = "qcom,sc7180-tcsr", "syscon";
1585 compatible = "qcom,sc7180-tcsr", "syscon";
1590 compatible = "qcom,sc7180-pinctrl";
1594 reg-names = "west", "north", "south";
1596 gpio-controller;
1597 #gpio-cells = <2>;
1598 interrupt-controller;
1599 #interrupt-cells = <2>;
1600 gpio-ranges = <&tlmm 0 0 120>;
1601 wakeup-parent = <&pdc>;
1603 dp_hot_plug_det: dp-hot-plug-det-state {
1608 qspi_clk: qspi-clk-state {
1613 qspi_cs0: qspi-cs0-state {
1618 qspi_cs1: qspi-cs1-state {
1623 qspi_data0: qspi-data0-state {
1628 qspi_data1: qspi-data1-state {
1633 qspi_data23: qspi-data23-state {
1638 qup_i2c0_default: qup-i2c0-default-state {
1643 qup_i2c1_default: qup-i2c1-default-state {
1648 qup_i2c2_default: qup-i2c2-default-state {
1653 qup_i2c3_default: qup-i2c3-default-state {
1658 qup_i2c4_default: qup-i2c4-default-state {
1663 qup_i2c5_default: qup-i2c5-default-state {
1668 qup_i2c6_default: qup-i2c6-default-state {
1673 qup_i2c7_default: qup-i2c7-default-state {
1678 qup_i2c8_default: qup-i2c8-default-state {
1683 qup_i2c9_default: qup-i2c9-default-state {
1688 qup_i2c10_default: qup-i2c10-default-state {
1693 qup_i2c11_default: qup-i2c11-default-state {
1698 qup_spi0_spi: qup-spi0-spi-state {
1703 qup_spi0_cs: qup-spi0-cs-state {
1708 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
1713 qup_spi1_spi: qup-spi1-spi-state {
1718 qup_spi1_cs: qup-spi1-cs-state {
1723 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
1728 qup_spi3_spi: qup-spi3-spi-state {
1733 qup_spi3_cs: qup-spi3-cs-state {
1738 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
1743 qup_spi5_spi: qup-spi5-spi-state {
1748 qup_spi5_cs: qup-spi5-cs-state {
1753 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
1758 qup_spi6_spi: qup-spi6-spi-state {
1763 qup_spi6_cs: qup-spi6-cs-state {
1768 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1773 qup_spi8_spi: qup-spi8-spi-state {
1778 qup_spi8_cs: qup-spi8-cs-state {
1783 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
1788 qup_spi10_spi: qup-spi10-spi-state {
1793 qup_spi10_cs: qup-spi10-cs-state {
1798 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
1803 qup_spi11_spi: qup-spi11-spi-state {
1808 qup_spi11_cs: qup-spi11-cs-state {
1813 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
1818 qup_uart0_default: qup-uart0-default-state {
1819 qup_uart0_cts: cts-pins {
1824 qup_uart0_rts: rts-pins {
1829 qup_uart0_tx: tx-pins {
1834 qup_uart0_rx: rx-pins {
1840 qup_uart1_default: qup-uart1-default-state {
1841 qup_uart1_cts: cts-pins {
1846 qup_uart1_rts: rts-pins {
1851 qup_uart1_tx: tx-pins {
1856 qup_uart1_rx: rx-pins {
1862 qup_uart2_default: qup-uart2-default-state {
1863 qup_uart2_tx: tx-pins {
1868 qup_uart2_rx: rx-pins {
1874 qup_uart3_default: qup-uart3-default-state {
1875 qup_uart3_cts: cts-pins {
1880 qup_uart3_rts: rts-pins {
1885 qup_uart3_tx: tx-pins {
1890 qup_uart3_rx: rx-pins {
1896 qup_uart4_default: qup-uart4-default-state {
1897 qup_uart4_tx: tx-pins {
1902 qup_uart4_rx: rx-pins {
1908 qup_uart5_default: qup-uart5-default-state {
1909 qup_uart5_cts: cts-pins {
1914 qup_uart5_rts: rts-pins {
1919 qup_uart5_tx: tx-pins {
1924 qup_uart5_rx: rx-pins {
1930 qup_uart6_default: qup-uart6-default-state {
1931 qup_uart6_cts: cts-pins {
1936 qup_uart6_rts: rts-pins {
1941 qup_uart6_tx: tx-pins {
1946 qup_uart6_rx: rx-pins {
1952 qup_uart7_default: qup-uart7-default-state {
1953 qup_uart7_tx: tx-pins {
1958 qup_uart7_rx: rx-pins {
1964 qup_uart8_default: qup-uart8-default-state {
1965 qup_uart8_tx: tx-pins {
1970 qup_uart8_rx: rx-pins {
1976 qup_uart9_default: qup-uart9-default-state {
1977 qup_uart9_tx: tx-pins {
1982 qup_uart9_rx: rx-pins {
1988 qup_uart10_default: qup-uart10-default-state {
1989 qup_uart10_cts: cts-pins {
1994 qup_uart10_rts: rts-pins {
1999 qup_uart10_tx: tx-pins {
2004 qup_uart10_rx: rx-pins {
2010 qup_uart11_default: qup-uart11-default-state {
2011 qup_uart11_cts: cts-pins {
2016 qup_uart11_rts: rts-pins {
2021 qup_uart11_tx: tx-pins {
2026 qup_uart11_rx: rx-pins {
2032 sec_mi2s_active: sec-mi2s-active-state {
2037 pri_mi2s_active: pri-mi2s-active-state {
2042 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
2049 compatible = "qcom,sc7180-mpss-pas";
2052 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2058 interrupt-names = "wdog", "fatal", "ready", "handover",
2059 "stop-ack", "shutdown-ack";
2062 clock-names = "xo";
2064 power-domains = <&rpmhpd SC7180_CX>,
2067 power-domain-names = "cx", "mx", "mss";
2069 memory-region = <&mpss_mem>;
2073 qcom,smem-states = <&modem_smp2p_out 0>;
2074 qcom,smem-state-names = "stop";
2078 glink-edge {
2081 qcom,remote-pid = <1>;
2087 compatible = "qcom,adreno-618.0", "qcom,adreno";
2090 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2093 operating-points-v2 = <&gpu_opp_table>;
2096 #cooling-cells = <2>;
2098 nvmem-cells = <&gpu_speed_bin>;
2099 nvmem-cell-names = "speed_bin";
2102 interconnect-names = "gfx-mem";
2104 gpu_opp_table: opp-table {
2105 compatible = "operating-points-v2";
2107 opp-825000000 {
2108 opp-hz = /bits/ 64 <825000000>;
2109 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2110 opp-peak-kBps = <8532000>;
2111 opp-supported-hw = <0x04>;
2114 opp-800000000 {
2115 opp-hz = /bits/ 64 <800000000>;
2116 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2117 opp-peak-kBps = <8532000>;
2118 opp-supported-hw = <0x07>;
2121 opp-650000000 {
2122 opp-hz = /bits/ 64 <650000000>;
2123 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2124 opp-peak-kBps = <7216000>;
2125 opp-supported-hw = <0x07>;
2128 opp-565000000 {
2129 opp-hz = /bits/ 64 <565000000>;
2130 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2131 opp-peak-kBps = <5412000>;
2132 opp-supported-hw = <0x07>;
2135 opp-430000000 {
2136 opp-hz = /bits/ 64 <430000000>;
2137 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2138 opp-peak-kBps = <5412000>;
2139 opp-supported-hw = <0x07>;
2142 opp-355000000 {
2143 opp-hz = /bits/ 64 <355000000>;
2144 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2145 opp-peak-kBps = <3072000>;
2146 opp-supported-hw = <0x07>;
2149 opp-267000000 {
2150 opp-hz = /bits/ 64 <267000000>;
2151 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2152 opp-peak-kBps = <3072000>;
2153 opp-supported-hw = <0x07>;
2156 opp-180000000 {
2157 opp-hz = /bits/ 64 <180000000>;
2158 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2159 opp-peak-kBps = <1804000>;
2160 opp-supported-hw = <0x07>;
2166 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2168 #iommu-cells = <1>;
2169 #global-interrupts = <2>;
2183 clock-names = "bus", "iface";
2185 power-domains = <&gpucc CX_GDSC>;
2189 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2192 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2195 interrupt-names = "hfi", "gmu";
2200 clock-names = "gmu", "cxo", "axi", "memnoc";
2201 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2202 power-domain-names = "cx", "gx";
2204 operating-points-v2 = <&gmu_opp_table>;
2206 gmu_opp_table: opp-table {
2207 compatible = "operating-points-v2";
2209 opp-200000000 {
2210 opp-hz = /bits/ 64 <200000000>;
2211 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2216 gpucc: clock-controller@5090000 {
2217 compatible = "qcom,sc7180-gpucc";
2222 clock-names = "bi_tcxo",
2225 #clock-cells = <1>;
2226 #reset-cells = <1>;
2227 #power-domain-cells = <1>;
2231 compatible = "qcom,sc7180-dcc", "qcom,dcc";
2237 compatible = "arm,coresight-stm", "arm,primecell";
2240 reg-names = "stm-base", "stm-stimulus-base";
2243 clock-names = "apb_pclk";
2245 out-ports {
2248 remote-endpoint = <&funnel0_in7>;
2255 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2259 clock-names = "apb_pclk";
2261 out-ports {
2264 remote-endpoint = <&merge_funnel_in0>;
2269 in-ports {
2270 #address-cells = <1>;
2271 #size-cells = <0>;
2276 remote-endpoint = <&stm_out>;
2283 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2287 clock-names = "apb_pclk";
2289 out-ports {
2292 remote-endpoint = <&merge_funnel_in1>;
2297 in-ports {
2298 #address-cells = <1>;
2299 #size-cells = <0>;
2304 remote-endpoint = <&apss_merge_funnel_out>;
2311 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2315 clock-names = "apb_pclk";
2317 out-ports {
2320 remote-endpoint = <&swao_funnel_in>;
2325 in-ports {
2326 #address-cells = <1>;
2327 #size-cells = <0>;
2332 remote-endpoint = <&funnel0_out>;
2339 remote-endpoint = <&funnel1_out>;
2346 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2350 clock-names = "apb_pclk";
2352 out-ports {
2355 remote-endpoint = <&etr_in>;
2360 in-ports {
2363 remote-endpoint = <&swao_replicator_out>;
2370 compatible = "arm,coresight-tmc", "arm,primecell";
2375 clock-names = "apb_pclk";
2376 arm,scatter-gather;
2378 in-ports {
2381 remote-endpoint = <&replicator_out>;
2388 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2392 clock-names = "apb_pclk";
2394 out-ports {
2397 remote-endpoint = <&etf_in>;
2402 in-ports {
2403 #address-cells = <1>;
2404 #size-cells = <0>;
2409 remote-endpoint = <&merge_funnel_out>;
2416 compatible = "arm,coresight-tmc", "arm,primecell";
2420 clock-names = "apb_pclk";
2422 out-ports {
2425 remote-endpoint = <&swao_replicator_in>;
2430 in-ports {
2433 remote-endpoint = <&swao_funnel_out>;
2440 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2444 clock-names = "apb_pclk";
2445 qcom,replicator-loses-context;
2447 out-ports {
2450 remote-endpoint = <&replicator_in>;
2455 in-ports {
2458 remote-endpoint = <&etf_out>;
2465 compatible = "arm,coresight-etm4x", "arm,primecell";
2471 clock-names = "apb_pclk";
2472 arm,coresight-loses-context-with-cpu;
2473 qcom,skip-power-up;
2475 out-ports {
2478 remote-endpoint = <&apss_funnel_in0>;
2485 compatible = "arm,coresight-etm4x", "arm,primecell";
2491 clock-names = "apb_pclk";
2492 arm,coresight-loses-context-with-cpu;
2493 qcom,skip-power-up;
2495 out-ports {
2498 remote-endpoint = <&apss_funnel_in1>;
2505 compatible = "arm,coresight-etm4x", "arm,primecell";
2511 clock-names = "apb_pclk";
2512 arm,coresight-loses-context-with-cpu;
2513 qcom,skip-power-up;
2515 out-ports {
2518 remote-endpoint = <&apss_funnel_in2>;
2525 compatible = "arm,coresight-etm4x", "arm,primecell";
2531 clock-names = "apb_pclk";
2532 arm,coresight-loses-context-with-cpu;
2533 qcom,skip-power-up;
2535 out-ports {
2538 remote-endpoint = <&apss_funnel_in3>;
2545 compatible = "arm,coresight-etm4x", "arm,primecell";
2551 clock-names = "apb_pclk";
2552 arm,coresight-loses-context-with-cpu;
2553 qcom,skip-power-up;
2555 out-ports {
2558 remote-endpoint = <&apss_funnel_in4>;
2565 compatible = "arm,coresight-etm4x", "arm,primecell";
2571 clock-names = "apb_pclk";
2572 arm,coresight-loses-context-with-cpu;
2573 qcom,skip-power-up;
2575 out-ports {
2578 remote-endpoint = <&apss_funnel_in5>;
2585 compatible = "arm,coresight-etm4x", "arm,primecell";
2591 clock-names = "apb_pclk";
2592 arm,coresight-loses-context-with-cpu;
2593 qcom,skip-power-up;
2595 out-ports {
2598 remote-endpoint = <&apss_funnel_in6>;
2605 compatible = "arm,coresight-etm4x", "arm,primecell";
2611 clock-names = "apb_pclk";
2612 arm,coresight-loses-context-with-cpu;
2613 qcom,skip-power-up;
2615 out-ports {
2618 remote-endpoint = <&apss_funnel_in7>;
2625 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2629 clock-names = "apb_pclk";
2631 out-ports {
2634 remote-endpoint = <&apss_merge_funnel_in>;
2639 in-ports {
2640 #address-cells = <1>;
2641 #size-cells = <0>;
2646 remote-endpoint = <&etm0_out>;
2653 remote-endpoint = <&etm1_out>;
2660 remote-endpoint = <&etm2_out>;
2667 remote-endpoint = <&etm3_out>;
2674 remote-endpoint = <&etm4_out>;
2681 remote-endpoint = <&etm5_out>;
2688 remote-endpoint = <&etm6_out>;
2695 remote-endpoint = <&etm7_out>;
2702 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2706 clock-names = "apb_pclk";
2708 out-ports {
2711 remote-endpoint = <&funnel1_in4>;
2716 in-ports {
2719 remote-endpoint = <&apss_funnel_out>;
2726 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2732 interrupt-names = "hc_irq", "pwr_irq";
2737 clock-names = "iface", "core", "xo";
2741 interconnect-names = "sdhc-ddr","cpu-sdhc";
2742 power-domains = <&rpmhpd SC7180_CX>;
2743 operating-points-v2 = <&sdhc2_opp_table>;
2745 bus-width = <4>;
2749 sdhc2_opp_table: opp-table {
2750 compatible = "operating-points-v2";
2752 opp-100000000 {
2753 opp-hz = /bits/ 64 <100000000>;
2754 required-opps = <&rpmhpd_opp_low_svs>;
2755 opp-peak-kBps = <1800000 600000>;
2756 opp-avg-kBps = <100000 0>;
2759 opp-202000000 {
2760 opp-hz = /bits/ 64 <202000000>;
2761 required-opps = <&rpmhpd_opp_nom>;
2762 opp-peak-kBps = <5400000 1600000>;
2763 opp-avg-kBps = <200000 0>;
2769 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2772 #address-cells = <1>;
2773 #size-cells = <0>;
2777 clock-names = "iface", "core";
2780 interconnect-names = "qspi-config";
2781 power-domains = <&rpmhpd SC7180_CX>;
2782 operating-points-v2 = <&qspi_opp_table>;
2787 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2790 #phy-cells = <0>;
2793 clock-names = "cfg_ahb", "ref";
2796 nvmem-cells = <&qusb2p_hstx_trim>;
2800 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2809 clock-names = "aux",
2817 reset-names = "phy", "common";
2819 #clock-cells = <1>;
2820 #phy-cells = <1>;
2824 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon";
2830 operating-points-v2 = <&cpu_bwmon_opp_table>;
2832 cpu_bwmon_opp_table: opp-table {
2833 compatible = "operating-points-v2";
2835 opp-0 {
2836 opp-peak-kBps = <2288000>;
2839 opp-1 {
2840 opp-peak-kBps = <4577000>;
2843 opp-2 {
2844 opp-peak-kBps = <7110000>;
2847 opp-3 {
2848 opp-peak-kBps = <9155000>;
2851 opp-4 {
2852 opp-peak-kBps = <12298000>;
2855 opp-5 {
2856 opp-peak-kBps = <14236000>;
2862 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2868 operating-points-v2 = <&llcc_bwmon_opp_table>;
2870 llcc_bwmon_opp_table: opp-table {
2871 compatible = "operating-points-v2";
2873 opp-0 {
2874 opp-peak-kBps = <1144000>;
2877 opp-1 {
2878 opp-peak-kBps = <1720000>;
2881 opp-2 {
2882 opp-peak-kBps = <2086000>;
2885 opp-3 {
2886 opp-peak-kBps = <2929000>;
2889 opp-4 {
2890 opp-peak-kBps = <3879000>;
2893 opp-5 {
2894 opp-peak-kBps = <5931000>;
2897 opp-6 {
2898 opp-peak-kBps = <6881000>;
2901 opp-7 {
2902 opp-peak-kBps = <8137000>;
2908 compatible = "qcom,sc7180-dc-noc";
2910 #interconnect-cells = <2>;
2911 qcom,bcm-voters = <&apps_bcm_voter>;
2914 system-cache-controller@9200000 {
2915 compatible = "qcom,sc7180-llcc";
2917 reg-names = "llcc0_base", "llcc_broadcast_base";
2922 compatible = "qcom,sc7180-gem-noc";
2924 #interconnect-cells = <2>;
2925 qcom,bcm-voters = <&apps_bcm_voter>;
2929 compatible = "qcom,sc7180-npu-noc";
2931 #interconnect-cells = <2>;
2932 qcom,bcm-voters = <&apps_bcm_voter>;
2936 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2939 #address-cells = <2>;
2940 #size-cells = <2>;
2942 dma-ranges;
2949 clock-names = "cfg_noc",
2955 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2957 assigned-clock-rates = <19200000>, <150000000>;
2959 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2963 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2966 power-domains = <&gcc USB30_PRIM_GDSC>;
2967 required-opps = <&rpmhpd_opp_nom>;
2973 interconnect-names = "usb-ddr", "apps-usb";
2975 wakeup-source;
2984 snps,parkmode-disable-ss-quirk;
2986 phy-names = "usb2-phy", "usb3-phy";
2987 maximum-speed = "super-speed";
2991 venus: video-codec@aa00000 {
2992 compatible = "qcom,sc7180-venus";
2995 power-domains = <&videocc VENUS_GDSC>,
2998 power-domain-names = "venus", "vcodec0", "cx";
2999 operating-points-v2 = <&venus_opp_table>;
3005 clock-names = "core", "iface", "bus",
3008 memory-region = <&venus_mem>;
3011 interconnect-names = "video-mem", "cpu-cfg";
3013 video-decoder {
3014 compatible = "venus-decoder";
3017 video-encoder {
3018 compatible = "venus-encoder";
3021 venus_opp_table: opp-table {
3022 compatible = "operating-points-v2";
3024 opp-150000000 {
3025 opp-hz = /bits/ 64 <150000000>;
3026 required-opps = <&rpmhpd_opp_low_svs>;
3029 opp-270000000 {
3030 opp-hz = /bits/ 64 <270000000>;
3031 required-opps = <&rpmhpd_opp_svs>;
3034 opp-340000000 {
3035 opp-hz = /bits/ 64 <340000000>;
3036 required-opps = <&rpmhpd_opp_svs_l1>;
3039 opp-434000000 {
3040 opp-hz = /bits/ 64 <434000000>;
3041 required-opps = <&rpmhpd_opp_nom>;
3044 opp-500000097 {
3045 opp-hz = /bits/ 64 <500000097>;
3046 required-opps = <&rpmhpd_opp_turbo>;
3051 videocc: clock-controller@ab00000 {
3052 compatible = "qcom,sc7180-videocc";
3055 clock-names = "bi_tcxo";
3056 #clock-cells = <1>;
3057 #reset-cells = <1>;
3058 #power-domain-cells = <1>;
3062 compatible = "qcom,sc7180-camnoc-virt";
3064 #interconnect-cells = <2>;
3065 qcom,bcm-voters = <&apps_bcm_voter>;
3068 camcc: clock-controller@ad00000 {
3069 compatible = "qcom,sc7180-camcc";
3074 clock-names = "bi_tcxo", "iface", "xo";
3075 #clock-cells = <1>;
3076 #reset-cells = <1>;
3077 #power-domain-cells = <1>;
3080 mdss: display-subsystem@ae00000 {
3081 compatible = "qcom,sc7180-mdss";
3083 reg-names = "mdss";
3085 power-domains = <&dispcc MDSS_GDSC>;
3088 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3089 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3090 clock-names = "iface", "ahb", "core";
3093 interrupt-controller;
3094 #interrupt-cells = <1>;
3097 interconnect-names = "mdp0-mem";
3101 #address-cells = <2>;
3102 #size-cells = <2>;
3107 mdp: display-controller@ae01000 {
3108 compatible = "qcom,sc7180-dpu";
3111 reg-names = "mdp", "vbif";
3114 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3115 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3116 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3117 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3118 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3119 clock-names = "bus", "iface", "rot", "lut", "core",
3121 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3122 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3123 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3124 assigned-clock-rates = <19200000>,
3127 operating-points-v2 = <&mdp_opp_table>;
3128 power-domains = <&rpmhpd SC7180_CX>;
3130 interrupt-parent = <&mdss>;
3134 #address-cells = <1>;
3135 #size-cells = <0>;
3140 remote-endpoint = <&mdss_dsi0_in>;
3147 remote-endpoint = <&dp_in>;
3152 mdp_opp_table: opp-table {
3153 compatible = "operating-points-v2";
3155 opp-200000000 {
3156 opp-hz = /bits/ 64 <200000000>;
3157 required-opps = <&rpmhpd_opp_low_svs>;
3160 opp-300000000 {
3161 opp-hz = /bits/ 64 <300000000>;
3162 required-opps = <&rpmhpd_opp_svs>;
3165 opp-345000000 {
3166 opp-hz = /bits/ 64 <345000000>;
3167 required-opps = <&rpmhpd_opp_svs_l1>;
3170 opp-460000000 {
3171 opp-hz = /bits/ 64 <460000000>;
3172 required-opps = <&rpmhpd_opp_nom>;
3178 compatible = "qcom,sc7180-dsi-ctrl",
3179 "qcom,mdss-dsi-ctrl";
3181 reg-names = "dsi_ctrl";
3183 interrupt-parent = <&mdss>;
3186 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3187 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3188 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3189 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3190 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3192 clock-names = "byte",
3199 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3200 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3202 operating-points-v2 = <&dsi_opp_table>;
3203 power-domains = <&rpmhpd SC7180_CX>;
3207 #address-cells = <1>;
3208 #size-cells = <0>;
3213 #address-cells = <1>;
3214 #size-cells = <0>;
3219 remote-endpoint = <&dpu_intf1_out>;
3230 dsi_opp_table: opp-table {
3231 compatible = "operating-points-v2";
3233 opp-187500000 {
3234 opp-hz = /bits/ 64 <187500000>;
3235 required-opps = <&rpmhpd_opp_low_svs>;
3238 opp-300000000 {
3239 opp-hz = /bits/ 64 <300000000>;
3240 required-opps = <&rpmhpd_opp_svs>;
3243 opp-358000000 {
3244 opp-hz = /bits/ 64 <358000000>;
3245 required-opps = <&rpmhpd_opp_svs_l1>;
3251 compatible = "qcom,dsi-phy-10nm";
3255 reg-names = "dsi_phy",
3259 #clock-cells = <1>;
3260 #phy-cells = <0>;
3262 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3264 clock-names = "iface", "ref";
3269 mdss_dp: displayport-controller@ae90000 {
3270 compatible = "qcom,sc7180-dp";
3279 interrupt-parent = <&mdss>;
3282 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3283 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3284 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3285 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3286 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3287 clock-names = "core_iface", "core_aux", "ctrl_link",
3289 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3290 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3291 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3294 phy-names = "dp";
3296 operating-points-v2 = <&dp_opp_table>;
3297 power-domains = <&rpmhpd SC7180_CX>;
3299 #sound-dai-cells = <0>;
3302 #address-cells = <1>;
3303 #size-cells = <0>;
3307 remote-endpoint = <&dpu_intf0_out>;
3317 dp_opp_table: opp-table {
3318 compatible = "operating-points-v2";
3320 opp-160000000 {
3321 opp-hz = /bits/ 64 <160000000>;
3322 required-opps = <&rpmhpd_opp_low_svs>;
3325 opp-270000000 {
3326 opp-hz = /bits/ 64 <270000000>;
3327 required-opps = <&rpmhpd_opp_svs>;
3330 opp-540000000 {
3331 opp-hz = /bits/ 64 <540000000>;
3332 required-opps = <&rpmhpd_opp_svs_l1>;
3335 opp-810000000 {
3336 opp-hz = /bits/ 64 <810000000>;
3337 required-opps = <&rpmhpd_opp_nom>;
3343 dispcc: clock-controller@af00000 { label
3344 compatible = "qcom,sc7180-dispcc";
3352 clock-names = "bi_tcxo",
3358 #clock-cells = <1>;
3359 #reset-cells = <1>;
3360 #power-domain-cells = <1>;
3363 pdc: interrupt-controller@b220000 {
3364 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3366 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3367 #interrupt-cells = <2>;
3368 interrupt-parent = <&intc>;
3369 interrupt-controller;
3372 pdc_reset: reset-controller@b2e0000 {
3373 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3375 #reset-cells = <1>;
3378 tsens0: thermal-sensor@c263000 {
3379 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3385 interrupt-names = "uplow","critical";
3386 #thermal-sensor-cells = <1>;
3389 tsens1: thermal-sensor@c265000 {
3390 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3396 interrupt-names = "uplow","critical";
3397 #thermal-sensor-cells = <1>;
3400 aoss_reset: reset-controller@c2a0000 {
3401 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3403 #reset-cells = <1>;
3406 aoss_qmp: power-management@c300000 {
3407 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3412 #clock-cells = <0>;
3416 compatible = "qcom,rpmh-stats";
3421 compatible = "qcom,spmi-pmic-arb";
3427 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3428 interrupt-names = "periph_irq";
3429 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3432 #address-cells = <2>;
3433 #size-cells = <0>;
3434 interrupt-controller;
3435 #interrupt-cells = <4>;
3439 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3442 #address-cells = <1>;
3443 #size-cells = <1>;
3447 pil-reloc@94c {
3448 compatible = "qcom,pil-reloc-info";
3454 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3456 #iommu-cells = <2>;
3457 #global-interrupts = <1>;
3541 intc: interrupt-controller@17a00000 {
3542 compatible = "arm,gic-v3";
3543 #address-cells = <2>;
3544 #size-cells = <2>;
3546 #interrupt-cells = <3>;
3547 interrupt-controller;
3552 msi-controller@17a40000 {
3553 compatible = "arm,gic-v3-its";
3554 msi-controller;
3555 #msi-cells = <1>;
3562 compatible = "qcom,sc7180-apss-shared",
3563 "qcom,sdm845-apss-shared";
3565 #mbox-cells = <1>;
3569 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3576 #address-cells = <1>;
3577 #size-cells = <1>;
3579 compatible = "arm,armv7-timer-mem";
3583 frame-number = <0>;
3591 frame-number = <1>;
3598 frame-number = <2>;
3605 frame-number = <3>;
3612 frame-number = <4>;
3619 frame-number = <5>;
3626 frame-number = <6>;
3634 compatible = "qcom,rpmh-rsc";
3638 reg-names = "drv-0", "drv-1", "drv-2";
3642 qcom,tcs-offset = <0xd00>;
3643 qcom,drv-id = <2>;
3644 qcom,tcs-config = <ACTIVE_TCS 2>,
3648 power-domains = <&CLUSTER_PD>;
3650 rpmhcc: clock-controller {
3651 compatible = "qcom,sc7180-rpmh-clk";
3653 clock-names = "xo";
3654 #clock-cells = <1>;
3657 rpmhpd: power-controller {
3658 compatible = "qcom,sc7180-rpmhpd";
3659 #power-domain-cells = <1>;
3660 operating-points-v2 = <&rpmhpd_opp_table>;
3662 rpmhpd_opp_table: opp-table {
3663 compatible = "operating-points-v2";
3666 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3670 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3674 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3678 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3682 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3686 opp-level = <224>;
3690 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3694 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3698 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3702 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3706 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3711 apps_bcm_voter: bcm-voter {
3712 compatible = "qcom,bcm-voter";
3717 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
3721 clock-names = "xo", "alternate";
3723 #interconnect-cells = <1>;
3727 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
3729 reg-names = "freq-domain0", "freq-domain1";
3732 clock-names = "xo", "alternate";
3734 #freq-domain-cells = <1>;
3735 #clock-cells = <1>;
3739 compatible = "qcom,wcn3990-wifi";
3741 reg-names = "membase";
3756 memory-region = <&wlan_mem>;
3757 qcom,msa-fixed-perm;
3761 lpasscc: clock-controller@62d00000 {
3762 compatible = "qcom,sc7180-lpasscorecc";
3765 reg-names = "lpass_core_cc", "lpass_audio_cc";
3768 clock-names = "iface", "bi_tcxo";
3769 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3770 #clock-cells = <1>;
3771 #power-domain-cells = <1>;
3777 compatible = "qcom,sc7180-lpass-cpu";
3780 reg-names = "lpass-hdmiif", "lpass-lpaif";
3786 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3787 required-opps = <&rpmhpd_opp_nom>;
3798 clock-names = "pcnoc-sway-clk", "audio-core",
3799 "mclk0", "pcnoc-mport-clk",
3800 "mi2s-bit-clk0", "mi2s-bit-clk1";
3803 #sound-dai-cells = <1>;
3804 #address-cells = <1>;
3805 #size-cells = <0>;
3809 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
3812 lpass_hm: clock-controller@63000000 {
3813 compatible = "qcom,sc7180-lpasshm";
3817 clock-names = "iface", "bi_tcxo";
3818 power-domains = <&rpmhpd SC7180_CX>;
3820 #clock-cells = <1>;
3821 #power-domain-cells = <1>;
3827 thermal-zones {
3828 cpu0_thermal: cpu0-thermal {
3829 polling-delay-passive = <250>;
3830 polling-delay = <0>;
3832 thermal-sensors = <&tsens0 1>;
3833 sustainable-power = <1052>;
3836 cpu0_alert0: trip-point0 {
3842 cpu0_alert1: trip-point1 {
3848 cpu0_crit: cpu-crit {
3855 cooling-maps {
3858 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3867 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3877 cpu1_thermal: cpu1-thermal {
3878 polling-delay-passive = <250>;
3879 polling-delay = <0>;
3881 thermal-sensors = <&tsens0 2>;
3882 sustainable-power = <1052>;
3885 cpu1_alert0: trip-point0 {
3891 cpu1_alert1: trip-point1 {
3897 cpu1_crit: cpu-crit {
3904 cooling-maps {
3907 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3916 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3926 cpu2_thermal: cpu2-thermal {
3927 polling-delay-passive = <250>;
3928 polling-delay = <0>;
3930 thermal-sensors = <&tsens0 3>;
3931 sustainable-power = <1052>;
3934 cpu2_alert0: trip-point0 {
3940 cpu2_alert1: trip-point1 {
3946 cpu2_crit: cpu-crit {
3953 cooling-maps {
3956 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3965 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3975 cpu3_thermal: cpu3-thermal {
3976 polling-delay-passive = <250>;
3977 polling-delay = <0>;
3979 thermal-sensors = <&tsens0 4>;
3980 sustainable-power = <1052>;
3983 cpu3_alert0: trip-point0 {
3989 cpu3_alert1: trip-point1 {
3995 cpu3_crit: cpu-crit {
4002 cooling-maps {
4005 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4014 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4024 cpu4_thermal: cpu4-thermal {
4025 polling-delay-passive = <250>;
4026 polling-delay = <0>;
4028 thermal-sensors = <&tsens0 5>;
4029 sustainable-power = <1052>;
4032 cpu4_alert0: trip-point0 {
4038 cpu4_alert1: trip-point1 {
4044 cpu4_crit: cpu-crit {
4051 cooling-maps {
4054 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4063 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4073 cpu5_thermal: cpu5-thermal {
4074 polling-delay-passive = <250>;
4075 polling-delay = <0>;
4077 thermal-sensors = <&tsens0 6>;
4078 sustainable-power = <1052>;
4081 cpu5_alert0: trip-point0 {
4087 cpu5_alert1: trip-point1 {
4093 cpu5_crit: cpu-crit {
4100 cooling-maps {
4103 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4112 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4122 cpu6_thermal: cpu6-thermal {
4123 polling-delay-passive = <250>;
4124 polling-delay = <0>;
4126 thermal-sensors = <&tsens0 9>;
4127 sustainable-power = <1425>;
4130 cpu6_alert0: trip-point0 {
4136 cpu6_alert1: trip-point1 {
4142 cpu6_crit: cpu-crit {
4149 cooling-maps {
4152 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4157 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4163 cpu7_thermal: cpu7-thermal {
4164 polling-delay-passive = <250>;
4165 polling-delay = <0>;
4167 thermal-sensors = <&tsens0 10>;
4168 sustainable-power = <1425>;
4171 cpu7_alert0: trip-point0 {
4177 cpu7_alert1: trip-point1 {
4183 cpu7_crit: cpu-crit {
4190 cooling-maps {
4193 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4198 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4204 cpu8_thermal: cpu8-thermal {
4205 polling-delay-passive = <250>;
4206 polling-delay = <0>;
4208 thermal-sensors = <&tsens0 11>;
4209 sustainable-power = <1425>;
4212 cpu8_alert0: trip-point0 {
4218 cpu8_alert1: trip-point1 {
4224 cpu8_crit: cpu-crit {
4231 cooling-maps {
4234 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4239 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4245 cpu9_thermal: cpu9-thermal {
4246 polling-delay-passive = <250>;
4247 polling-delay = <0>;
4249 thermal-sensors = <&tsens0 12>;
4250 sustainable-power = <1425>;
4253 cpu9_alert0: trip-point0 {
4259 cpu9_alert1: trip-point1 {
4265 cpu9_crit: cpu-crit {
4272 cooling-maps {
4275 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4280 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4286 aoss0-thermal {
4287 polling-delay-passive = <250>;
4288 polling-delay = <0>;
4290 thermal-sensors = <&tsens0 0>;
4293 aoss0_alert0: trip-point0 {
4299 aoss0_crit: aoss0-crit {
4307 cpuss0-thermal {
4308 polling-delay-passive = <250>;
4309 polling-delay = <0>;
4311 thermal-sensors = <&tsens0 7>;
4314 cpuss0_alert0: trip-point0 {
4319 cpuss0_crit: cluster0-crit {
4327 cpuss1-thermal {
4328 polling-delay-passive = <250>;
4329 polling-delay = <0>;
4331 thermal-sensors = <&tsens0 8>;
4334 cpuss1_alert0: trip-point0 {
4339 cpuss1_crit: cluster0-crit {
4347 gpuss0-thermal {
4348 polling-delay-passive = <250>;
4349 polling-delay = <0>;
4351 thermal-sensors = <&tsens0 13>;
4354 gpuss0_alert0: trip-point0 {
4360 gpuss0_crit: gpuss0-crit {
4367 cooling-maps {
4370 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4375 gpuss1-thermal {
4376 polling-delay-passive = <250>;
4377 polling-delay = <0>;
4379 thermal-sensors = <&tsens0 14>;
4382 gpuss1_alert0: trip-point0 {
4388 gpuss1_crit: gpuss1-crit {
4395 cooling-maps {
4398 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4403 aoss1-thermal {
4404 polling-delay-passive = <250>;
4405 polling-delay = <0>;
4407 thermal-sensors = <&tsens1 0>;
4410 aoss1_alert0: trip-point0 {
4416 aoss1_crit: aoss1-crit {
4424 cwlan-thermal {
4425 polling-delay-passive = <250>;
4426 polling-delay = <0>;
4428 thermal-sensors = <&tsens1 1>;
4431 cwlan_alert0: trip-point0 {
4437 cwlan_crit: cwlan-crit {
4445 audio-thermal {
4446 polling-delay-passive = <250>;
4447 polling-delay = <0>;
4449 thermal-sensors = <&tsens1 2>;
4452 audio_alert0: trip-point0 {
4458 audio_crit: audio-crit {
4466 ddr-thermal {
4467 polling-delay-passive = <250>;
4468 polling-delay = <0>;
4470 thermal-sensors = <&tsens1 3>;
4473 ddr_alert0: trip-point0 {
4479 ddr_crit: ddr-crit {
4487 q6-hvx-thermal {
4488 polling-delay-passive = <250>;
4489 polling-delay = <0>;
4491 thermal-sensors = <&tsens1 4>;
4494 q6_hvx_alert0: trip-point0 {
4500 q6_hvx_crit: q6-hvx-crit {
4508 camera-thermal {
4509 polling-delay-passive = <250>;
4510 polling-delay = <0>;
4512 thermal-sensors = <&tsens1 5>;
4515 camera_alert0: trip-point0 {
4521 camera_crit: camera-crit {
4529 mdm-core-thermal {
4530 polling-delay-passive = <250>;
4531 polling-delay = <0>;
4533 thermal-sensors = <&tsens1 6>;
4536 mdm_alert0: trip-point0 {
4542 mdm_crit: mdm-crit {
4550 mdm-dsp-thermal {
4551 polling-delay-passive = <250>;
4552 polling-delay = <0>;
4554 thermal-sensors = <&tsens1 7>;
4557 mdm_dsp_alert0: trip-point0 {
4563 mdm_dsp_crit: mdm-dsp-crit {
4571 npu-thermal {
4572 polling-delay-passive = <250>;
4573 polling-delay = <0>;
4575 thermal-sensors = <&tsens1 8>;
4578 npu_alert0: trip-point0 {
4584 npu_crit: npu-crit {
4592 video-thermal {
4593 polling-delay-passive = <250>;
4594 polling-delay = <0>;
4596 thermal-sensors = <&tsens1 9>;
4599 video_alert0: trip-point0 {
4605 video_crit: video-crit {
4615 compatible = "arm,armv8-timer";