Lines Matching +full:0 +full:x03500000
63 #clock-cells = <0>;
69 #clock-cells = <0>;
75 #size-cells = <0>;
77 CPU0: cpu@0 {
80 reg = <0x0 0x0>;
81 clocks = <&cpufreq_hw 0>;
92 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x100>;
110 clocks = <&cpufreq_hw 0>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
133 reg = <0x0 0x200>;
134 clocks = <&cpufreq_hw 0>;
145 qcom,freq-domain = <&cpufreq_hw 0>;
157 reg = <0x0 0x300>;
158 clocks = <&cpufreq_hw 0>;
169 qcom,freq-domain = <&cpufreq_hw 0>;
181 reg = <0x0 0x400>;
182 clocks = <&cpufreq_hw 0>;
193 qcom,freq-domain = <&cpufreq_hw 0>;
205 reg = <0x0 0x500>;
206 clocks = <&cpufreq_hw 0>;
217 qcom,freq-domain = <&cpufreq_hw 0>;
229 reg = <0x0 0x600>;
253 reg = <0x0 0x700>;
313 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
316 arm,psci-suspend-param = <0x40000003>;
323 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
326 arm,psci-suspend-param = <0x40000004>;
333 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
336 arm,psci-suspend-param = <0x40000003>;
346 arm,psci-suspend-param = <0x40000004>;
355 CLUSTER_SLEEP_PC: cluster-sleep-0 {
358 arm,psci-suspend-param = <0x41000044>;
367 arm,psci-suspend-param = <0x41001244>;
376 arm,psci-suspend-param = <0x4100b244>;
393 reg = <0 0x80000000 0 0>;
584 #power-domain-cells = <0>;
590 #power-domain-cells = <0>;
596 #power-domain-cells = <0>;
602 #power-domain-cells = <0>;
608 #power-domain-cells = <0>;
614 #power-domain-cells = <0>;
620 #power-domain-cells = <0>;
626 #power-domain-cells = <0>;
632 #power-domain-cells = <0>;
645 reg = <0x0 0x80000000 0x0 0x600000>;
650 reg = <0x0 0x80600000 0x0 0x200000>;
655 reg = <0x0 0x80800000 0x0 0x20000>;
660 reg = <0x0 0x80820000 0x0 0x20000>;
666 reg = <0x0 0x808ff000 0x0 0x1000>;
671 reg = <0x0 0x80900000 0x0 0x200000>;
676 reg = <0x0 0x80b00000 0x0 0x3900000>;
681 reg = <0 0x8b700000 0 0x10000>;
687 reg = <0x0 0x94600000 0x0 0x200000>;
709 qcom,local-pid = <0>;
733 qcom,local-pid = <0>;
754 qcom,local-pid = <0>;
780 soc: soc@0 {
783 ranges = <0 0 0 0 0x10 0>;
784 dma-ranges = <0 0 0 0 0x10 0>;
789 reg = <0 0x00100000 0 0x1f0000>;
802 reg = <0 0x00784000 0 0x7a0>,
803 <0 0x00780000 0 0x7a0>,
804 <0 0x00782000 0 0x100>,
805 <0 0x00786000 0 0x1fff>;
813 reg = <0x25b 0x1>;
818 reg = <0x1d2 0x2>;
825 reg = <0 0x007c4000 0 0x1000>,
826 <0 0x007c5000 0 0x1000>;
829 iommus = <&apps_smmu 0x60 0x0>;
838 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
839 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
862 opp-avg-kBps = <100000 0>;
869 opp-avg-kBps = <390000 0>;
876 reg = <0 0x008c0000 0 0x6000>;
883 iommus = <&apps_smmu 0x43 0x0>;
888 reg = <0 0x00880000 0 0x4000>;
892 pinctrl-0 = <&qup_i2c0_default>;
895 #size-cells = <0>;
896 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
897 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
898 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
908 reg = <0 0x00880000 0 0x4000>;
912 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
915 #size-cells = <0>;
918 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
919 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
926 reg = <0 0x00880000 0 0x4000>;
930 pinctrl-0 = <&qup_uart0_default>;
934 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
935 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
942 reg = <0 0x00884000 0 0x4000>;
946 pinctrl-0 = <&qup_i2c1_default>;
949 #size-cells = <0>;
950 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
952 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
962 reg = <0 0x00884000 0 0x4000>;
966 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
969 #size-cells = <0>;
972 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
980 reg = <0 0x00884000 0 0x4000>;
984 pinctrl-0 = <&qup_uart1_default>;
988 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
989 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
996 reg = <0 0x00888000 0 0x4000>;
1000 pinctrl-0 = <&qup_i2c2_default>;
1003 #size-cells = <0>;
1004 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1005 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1006 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1016 reg = <0 0x00888000 0 0x4000>;
1020 pinctrl-0 = <&qup_uart2_default>;
1024 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1025 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1032 reg = <0 0x0088c000 0 0x4000>;
1036 pinctrl-0 = <&qup_i2c3_default>;
1039 #size-cells = <0>;
1040 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1041 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1042 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1052 reg = <0 0x0088c000 0 0x4000>;
1056 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1059 #size-cells = <0>;
1062 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1063 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1070 reg = <0 0x0088c000 0 0x4000>;
1074 pinctrl-0 = <&qup_uart3_default>;
1078 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1079 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1086 reg = <0 0x00890000 0 0x4000>;
1090 pinctrl-0 = <&qup_i2c4_default>;
1093 #size-cells = <0>;
1094 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1095 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1096 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1106 reg = <0 0x00890000 0 0x4000>;
1110 pinctrl-0 = <&qup_uart4_default>;
1114 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1115 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1122 reg = <0 0x00894000 0 0x4000>;
1126 pinctrl-0 = <&qup_i2c5_default>;
1129 #size-cells = <0>;
1130 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1131 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1132 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1142 reg = <0 0x00894000 0 0x4000>;
1146 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1149 #size-cells = <0>;
1152 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1153 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1160 reg = <0 0x00894000 0 0x4000>;
1164 pinctrl-0 = <&qup_uart5_default>;
1168 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1169 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1177 reg = <0 0x00ac0000 0 0x6000>;
1184 iommus = <&apps_smmu 0x4c3 0x0>;
1189 reg = <0 0x00a80000 0 0x4000>;
1193 pinctrl-0 = <&qup_i2c6_default>;
1196 #size-cells = <0>;
1197 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1198 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1199 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1209 reg = <0 0x00a80000 0 0x4000>;
1213 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1216 #size-cells = <0>;
1219 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1220 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1227 reg = <0 0x00a80000 0 0x4000>;
1231 pinctrl-0 = <&qup_uart6_default>;
1235 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1236 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1243 reg = <0 0x00a84000 0 0x4000>;
1247 pinctrl-0 = <&qup_i2c7_default>;
1250 #size-cells = <0>;
1251 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1252 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1253 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1263 reg = <0 0x00a84000 0 0x4000>;
1267 pinctrl-0 = <&qup_uart7_default>;
1271 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1272 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1279 reg = <0 0x00a88000 0 0x4000>;
1283 pinctrl-0 = <&qup_i2c8_default>;
1286 #size-cells = <0>;
1287 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1288 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1289 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1299 reg = <0 0x00a88000 0 0x4000>;
1303 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1306 #size-cells = <0>;
1309 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1310 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1317 reg = <0 0x00a88000 0 0x4000>;
1321 pinctrl-0 = <&qup_uart8_default>;
1325 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1326 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1333 reg = <0 0x00a8c000 0 0x4000>;
1337 pinctrl-0 = <&qup_i2c9_default>;
1340 #size-cells = <0>;
1341 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1342 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1343 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1353 reg = <0 0x00a8c000 0 0x4000>;
1357 pinctrl-0 = <&qup_uart9_default>;
1361 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1362 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1369 reg = <0 0x00a90000 0 0x4000>;
1373 pinctrl-0 = <&qup_i2c10_default>;
1376 #size-cells = <0>;
1377 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1378 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1379 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1389 reg = <0 0x00a90000 0 0x4000>;
1393 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1396 #size-cells = <0>;
1399 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1400 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1407 reg = <0 0x00a90000 0 0x4000>;
1411 pinctrl-0 = <&qup_uart10_default>;
1415 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1416 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1423 reg = <0 0x00a94000 0 0x4000>;
1427 pinctrl-0 = <&qup_i2c11_default>;
1430 #size-cells = <0>;
1431 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1432 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1433 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1443 reg = <0 0x00a94000 0 0x4000>;
1447 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1450 #size-cells = <0>;
1453 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1454 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1461 reg = <0 0x00a94000 0 0x4000>;
1465 pinctrl-0 = <&qup_uart11_default>;
1469 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1470 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1478 reg = <0 0x01500000 0 0x28000>;
1485 reg = <0 0x01620000 0 0x17080>;
1492 reg = <0 0x01638000 0 0x1000>;
1499 reg = <0 0x01650000 0 0x1000>;
1506 reg = <0 0x016e0000 0 0x15080>;
1513 reg = <0 0x01705000 0 0x9000>;
1520 reg = <0 0x0170e000 0 0x6000>;
1527 reg = <0 0x01740000 0 0x1c100>;
1535 iommus = <&apps_smmu 0x440 0x0>,
1536 <&apps_smmu 0x442 0x0>;
1537 reg = <0 0x01e40000 0 0x7000>,
1538 <0 0x01e47000 0 0x2000>,
1539 <0 0x01e04000 0 0x2c000>;
1546 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1556 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1557 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1558 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1565 qcom,smem-states = <&ipa_smp2p_out 0>,
1575 reg = <0 0x01f40000 0 0x20000>;
1581 reg = <0 0x01f60000 0 0x20000>;
1586 reg = <0 0x01fc0000 0 0x40000>;
1591 reg = <0 0x03500000 0 0x300000>,
1592 <0 0x03900000 0 0x300000>,
1593 <0 0x03d00000 0 0x300000>;
1600 gpio-ranges = <&tlmm 0 0 120>;
2050 reg = <0 0x04080000 0 0x4040>;
2053 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2073 qcom,smem-states = <&modem_smp2p_out 0>;
2088 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2089 <0 0x05061000 0 0x800>;
2092 iommus = <&adreno_smmu 0>;
2101 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2111 opp-supported-hw = <0x04>;
2118 opp-supported-hw = <0x07>;
2125 opp-supported-hw = <0x07>;
2132 opp-supported-hw = <0x07>;
2139 opp-supported-hw = <0x07>;
2146 opp-supported-hw = <0x07>;
2153 opp-supported-hw = <0x07>;
2160 opp-supported-hw = <0x07>;
2167 reg = <0 0x05040000 0 0x10000>;
2190 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2191 <0 0x0b490000 0 0x10000>;
2218 reg = <0 0x05090000 0 0x9000>;
2232 reg = <0x0 0x010a2000 0x0 0x1000>,
2233 <0x0 0x010ae000 0x0 0x2000>;
2238 reg = <0 0x06002000 0 0x1000>,
2239 <0 0x16280000 0 0x180000>;
2256 reg = <0 0x06041000 0 0x1000>;
2271 #size-cells = <0>;
2284 reg = <0 0x06042000 0 0x1000>;
2299 #size-cells = <0>;
2312 reg = <0 0x06045000 0 0x1000>;
2327 #size-cells = <0>;
2329 port@0 {
2330 reg = <0>;
2347 reg = <0 0x06046000 0 0x1000>;
2371 reg = <0 0x06048000 0 0x1000>;
2372 iommus = <&apps_smmu 0x04a0 0x20>;
2389 reg = <0 0x06b04000 0 0x1000>;
2404 #size-cells = <0>;
2417 reg = <0 0x06b05000 0 0x1000>;
2441 reg = <0 0x06b06000 0 0x1000>;
2466 reg = <0 0x07040000 0 0x1000>;
2486 reg = <0 0x07140000 0 0x1000>;
2506 reg = <0 0x07240000 0 0x1000>;
2526 reg = <0 0x07340000 0 0x1000>;
2546 reg = <0 0x07440000 0 0x1000>;
2566 reg = <0 0x07540000 0 0x1000>;
2586 reg = <0 0x07640000 0 0x1000>;
2606 reg = <0 0x07740000 0 0x1000>;
2626 reg = <0 0x07800000 0 0x1000>;
2641 #size-cells = <0>;
2643 port@0 {
2644 reg = <0>;
2703 reg = <0 0x07810000 0 0x1000>;
2727 reg = <0 0x08804000 0 0x1000>;
2729 iommus = <&apps_smmu 0x80 0>;
2739 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2740 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2756 opp-avg-kBps = <100000 0>;
2763 opp-avg-kBps = <200000 0>;
2770 reg = <0 0x088dc000 0 0x600>;
2771 iommus = <&apps_smmu 0x20 0x0>;
2773 #size-cells = <0>;
2778 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2779 &config_noc SLAVE_QSPI_0 0>;
2788 reg = <0 0x088e3000 0 0x400>;
2790 #phy-cells = <0>;
2801 reg = <0 0x088e8000 0 0x3000>;
2825 reg = <0 0x090b6300 0 0x600>;
2835 opp-0 {
2863 reg = <0 0x090cd000 0 0x1000>;
2873 opp-0 {
2909 reg = <0 0x09160000 0 0x03200>;
2916 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2923 reg = <0 0x09680000 0 0x3e200>;
2930 reg = <0 0x09990000 0 0x1600>;
2937 reg = <0 0x0a6f8800 0 0x400>;
2971 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2972 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2979 reg = <0 0x0a600000 0 0xe000>;
2981 iommus = <&apps_smmu 0x540 0>;
2993 reg = <0 0x0aa00000 0 0xff000>;
3007 iommus = <&apps_smmu 0x0c00 0x60>;
3009 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3010 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3053 reg = <0 0x0ab00000 0 0x10000>;
3063 reg = <0 0x0ac00000 0 0x1000>;
3070 reg = <0 0x0ad00000 0 0x10000>;
3082 reg = <0 0x0ae00000 0 0x1000>;
3096 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3099 iommus = <&apps_smmu 0x800 0x2>;
3109 reg = <0 0x0ae01000 0 0x8f000>,
3110 <0 0x0aeb0000 0 0x2008>;
3131 interrupts = <0>;
3135 #size-cells = <0>;
3137 port@0 {
3138 reg = <0>;
3180 reg = <0 0x0ae94000 0 0x400>;
3200 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3208 #size-cells = <0>;
3214 #size-cells = <0>;
3216 port@0 {
3217 reg = <0>;
3252 reg = <0 0x0ae94400 0 0x200>,
3253 <0 0x0ae94600 0 0x280>,
3254 <0 0x0ae94a00 0 0x1e0>;
3260 #phy-cells = <0>;
3273 reg = <0 0x0ae90000 0 0x200>,
3274 <0 0x0ae90200 0 0x200>,
3275 <0 0x0ae90400 0 0xc00>,
3276 <0 0x0ae91000 0 0x400>,
3277 <0 0x0ae91400 0 0x400>;
3299 #sound-dai-cells = <0>;
3303 #size-cells = <0>;
3304 port@0 {
3305 reg = <0>;
3345 reg = <0 0x0af00000 0 0x200000>;
3348 <&mdss_dsi0_phy 0>,
3365 reg = <0 0x0b220000 0 0x30000>;
3366 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3374 reg = <0 0x0b2e0000 0 0x20000>;
3380 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3381 <0 0x0c222000 0 0x1ff>; /* SROT */
3391 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3392 <0 0x0c223000 0 0x1ff>; /* SROT */
3402 reg = <0 0x0c2a0000 0 0x31000>;
3408 reg = <0 0x0c300000 0 0x400>;
3410 mboxes = <&apss_shared 0>;
3412 #clock-cells = <0>;
3417 reg = <0 0x0c3f0000 0 0x400>;
3422 reg = <0 0x0c440000 0 0x1100>,
3423 <0 0x0c600000 0 0x2000000>,
3424 <0 0x0e600000 0 0x100000>,
3425 <0 0x0e700000 0 0xa0000>,
3426 <0 0x0c40a000 0 0x26000>;
3430 qcom,ee = <0>;
3431 qcom,channel = <0>;
3433 #size-cells = <0>;
3440 reg = <0 0x146aa000 0 0x2000>;
3445 ranges = <0 0 0x146aa000 0x2000>;
3449 reg = <0x94c 0xc8>;
3455 reg = <0 0x15000000 0 0x100000>;
3548 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3549 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3556 reg = <0 0x17a40000 0 0x20000>;
3564 reg = <0 0x17c00000 0 0x10000>;
3570 reg = <0 0x17c10000 0 0x1000>;
3572 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3578 ranges = <0 0 0 0x20000000>;
3580 reg = <0 0x17c20000 0 0x1000>;
3583 frame-number = <0>;
3586 reg = <0x17c21000 0x1000>,
3587 <0x17c22000 0x1000>;
3593 reg = <0x17c23000 0x1000>;
3600 reg = <0x17c25000 0x1000>;
3607 reg = <0x17c27000 0x1000>;
3614 reg = <0x17c29000 0x1000>;
3621 reg = <0x17c2b000 0x1000>;
3628 reg = <0x17c2d000 0x1000>;
3635 reg = <0 0x18200000 0 0x10000>,
3636 <0 0x18210000 0 0x10000>,
3637 <0 0x18220000 0 0x10000>;
3638 reg-names = "drv-0", "drv-1", "drv-2";
3642 qcom,tcs-offset = <0xd00>;
3718 reg = <0 0x18321000 0 0x1400>;
3728 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3740 reg = <0 0x18800000 0 0x800000>;
3742 iommus = <&apps_smmu 0xc0 0x1>;
3763 reg = <0 0x62d00000 0 0x50000>,
3764 <0 0x62780000 0 0x30000>;
3779 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3782 iommus = <&apps_smmu 0x1020 0>,
3783 <&apps_smmu 0x1021 0>,
3784 <&apps_smmu 0x1032 0>;
3805 #size-cells = <0>;
3814 reg = <0 0x63000000 0 0x28>;
3830 polling-delay = <0>;
3879 polling-delay = <0>;
3928 polling-delay = <0>;
3977 polling-delay = <0>;
4026 polling-delay = <0>;
4075 polling-delay = <0>;
4124 polling-delay = <0>;
4165 polling-delay = <0>;
4206 polling-delay = <0>;
4247 polling-delay = <0>;
4288 polling-delay = <0>;
4290 thermal-sensors = <&tsens0 0>;
4309 polling-delay = <0>;
4329 polling-delay = <0>;
4349 polling-delay = <0>;
4377 polling-delay = <0>;
4405 polling-delay = <0>;
4407 thermal-sensors = <&tsens1 0>;
4426 polling-delay = <0>;
4447 polling-delay = <0>;
4468 polling-delay = <0>;
4489 polling-delay = <0>;
4510 polling-delay = <0>;
4531 polling-delay = <0>;
4552 polling-delay = <0>;
4573 polling-delay = <0>;
4594 polling-delay = <0>;
4619 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;