Lines Matching +full:qdu1000 +full:- +full:clk +full:- +full:virt
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 interrupt-parent = <&intc>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-a55";
31 enable-method = "psci";
32 power-domains = <&CPU_PD0>;
33 power-domain-names = "psci";
34 qcom,freq-domains = <&cpufreq_hw 0>;
35 next-level-cache = <&L2_0>;
36 L2_0: l2-cache {
38 cache-level = <2>;
39 cache-unified;
40 next-level-cache = <&L3_0>;
41 L3_0: l3-cache {
43 cache-level = <3>;
44 cache-unified;
51 compatible = "arm,cortex-a55";
54 enable-method = "psci";
55 power-domains = <&CPU_PD1>;
56 power-domain-names = "psci";
57 qcom,freq-domains = <&cpufreq_hw 0>;
58 next-level-cache = <&L2_100>;
59 L2_100: l2-cache {
61 cache-level = <2>;
62 cache-unified;
63 next-level-cache = <&L3_0>;
69 compatible = "arm,cortex-a55";
72 enable-method = "psci";
73 power-domains = <&CPU_PD2>;
74 power-domain-names = "psci";
75 qcom,freq-domains = <&cpufreq_hw 0>;
76 next-level-cache = <&L2_200>;
77 L2_200: l2-cache {
79 cache-level = <2>;
80 cache-unified;
81 next-level-cache = <&L3_0>;
87 compatible = "arm,cortex-a55";
90 enable-method = "psci";
91 power-domains = <&CPU_PD3>;
92 power-domain-names = "psci";
93 qcom,freq-domains = <&cpufreq_hw 0>;
94 next-level-cache = <&L2_300>;
95 L2_300: l2-cache {
97 cache-level = <2>;
98 cache-unified;
99 next-level-cache = <&L3_0>;
103 cpu-map {
124 idle-states {
125 entry-method = "psci";
127 CPU_OFF: cpu-sleep-0 {
128 compatible = "arm,idle-state";
129 entry-latency-us = <274>;
130 exit-latency-us = <480>;
131 min-residency-us = <3934>;
132 arm,psci-suspend-param = <0x40000004>;
133 local-timer-stop;
137 domain-idle-states {
138 CLUSTER_SLEEP_0: cluster-sleep-0 {
139 compatible = "domain-idle-state";
140 entry-latency-us = <584>;
141 exit-latency-us = <2332>;
142 min-residency-us = <6118>;
143 arm,psci-suspend-param = <0x41000044>;
146 CLUSTER_SLEEP_1: cluster-sleep-1 {
147 compatible = "domain-idle-state";
148 entry-latency-us = <2893>;
149 exit-latency-us = <4023>;
150 min-residency-us = <9987>;
151 arm,psci-suspend-param = <0x41003344>;
157 compatible = "qcom,scm-qdu1000", "qcom,scm";
161 mc_virt: interconnect-0 {
162 compatible = "qcom,qdu1000-mc-virt";
163 qcom,bcm-voters = <&apps_bcm_voter>;
164 #interconnect-cells = <2>;
167 clk_virt: interconnect-1 {
168 compatible = "qcom,qdu1000-clk-virt";
169 qcom,bcm-voters = <&apps_bcm_voter>;
170 #interconnect-cells = <2>;
180 compatible = "arm,armv8-pmuv3";
185 compatible = "arm,psci-1.0";
188 CPU_PD0: power-domain-cpu0 {
189 #power-domain-cells = <0>;
190 power-domains = <&CLUSTER_PD>;
191 domain-idle-states = <&CPU_OFF>;
194 CPU_PD1: power-domain-cpu1 {
195 #power-domain-cells = <0>;
196 power-domains = <&CLUSTER_PD>;
197 domain-idle-states = <&CPU_OFF>;
200 CPU_PD2: power-domain-cpu2 {
201 #power-domain-cells = <0>;
202 power-domains = <&CLUSTER_PD>;
203 domain-idle-states = <&CPU_OFF>;
206 CPU_PD3: power-domain-cpu3 {
207 #power-domain-cells = <0>;
208 power-domains = <&CLUSTER_PD>;
209 domain-idle-states = <&CPU_OFF>;
212 CLUSTER_PD: power-domain-cluster {
213 #power-domain-cells = <0>;
214 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>;
218 reserved_memory: reserved-memory {
219 #address-cells = <2>;
220 #size-cells = <2>;
225 no-map;
228 xbl_dt_log_mem: xbl-dt-log@80600000 {
230 no-map;
233 xbl_ramdump_mem: xbl-ramdump@80640000 {
235 no-map;
238 aop_image_mem: aop-image@80800000 {
240 no-map;
243 aop_cmd_db_mem: aop-cmd-db@80860000 {
244 compatible = "qcom,cmd-db";
246 no-map;
249 aop_config_mem: aop-config@80880000 {
251 no-map;
254 tme_crash_dump_mem: tme-crash-dump@808a0000 {
256 no-map;
259 tme_log_mem: tme-log@808e0000 {
261 no-map;
264 uefi_log_mem: uefi-log@808e4000 {
266 no-map;
272 no-map;
276 cpucp_fw_mem: cpucp-fw@80b00000 {
278 no-map;
283 no-map;
286 tz_stat_mem: tz-stat@81d00000 {
288 no-map;
293 no-map;
298 no-map;
303 no-map;
308 no-map;
313 no-map;
318 no-map;
323 ipa_fw_mem: ipa-fw@8be00000 {
325 no-map;
328 ipa_gsi_mem: ipa-gsi@8be10000 {
330 no-map;
335 no-map;
338 q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 {
340 no-map;
345 no-map;
348 oem_tenx_mem: oem-tenx@b9600000 {
350 no-map;
353 tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 {
355 no-map;
358 ipa_buffer_mem: ipa-buffer@c3200000 {
360 no-map;
365 compatible = "simple-bus";
366 #address-cells = <2>;
367 #size-cells = <2>;
369 dma-ranges = <0 0 0 0 0x10 0>;
371 gcc: clock-controller@80000 {
372 compatible = "qcom,qdu1000-gcc";
379 #clock-cells = <1>;
380 #reset-cells = <1>;
381 #power-domain-cells = <1>;
384 gpi_dma0: dma-controller@900000 {
385 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
399 dma-channels = <12>;
400 dma-channel-mask = <0x3f>;
402 #dma-cells = <3>;
406 compatible = "qcom,geni-se-qup";
410 clock-names = "m-ahb", "s-ahb";
414 interconnect-names = "qup-core";
416 #address-cells = <2>;
417 #size-cells = <2>;
422 compatible = "qcom,geni-uart";
425 clock-names = "se";
426 pinctrl-0 = <&qup_uart0_default>;
427 pinctrl-names = "default";
433 compatible = "qcom,geni-i2c";
436 clock-names = "se";
438 pinctrl-0 = <&qup_i2c1_data_clk>;
439 pinctrl-names = "default";
440 #address-cells = <1>;
441 #size-cells = <0>;
446 compatible = "qcom,geni-spi";
448 #address-cells = <1>;
449 #size-cells = <0>;
452 clock-names = "se";
453 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
454 pinctrl-names = "default";
459 compatible = "qcom,geni-i2c";
462 clock-names = "se";
464 pinctrl-0 = <&qup_i2c2_data_clk>;
465 pinctrl-names = "default";
466 #address-cells = <1>;
467 #size-cells = <0>;
472 compatible = "qcom,geni-spi";
474 #address-cells = <1>;
475 #size-cells = <0>;
478 clock-names = "se";
479 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
480 pinctrl-names = "default";
485 compatible = "qcom,geni-i2c";
488 clock-names = "se";
490 pinctrl-0 = <&qup_i2c3_data_clk>;
491 pinctrl-names = "default";
492 #address-cells = <1>;
493 #size-cells = <0>;
498 compatible = "qcom,geni-spi";
500 #address-cells = <1>;
501 #size-cells = <0>;
504 clock-names = "se";
505 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
506 pinctrl-names = "default";
511 compatible = "qcom,geni-i2c";
514 clock-names = "se";
516 pinctrl-0 = <&qup_i2c4_data_clk>;
517 pinctrl-names = "default";
518 #address-cells = <1>;
519 #size-cells = <0>;
524 compatible = "qcom,geni-spi";
526 #address-cells = <1>;
527 #size-cells = <0>;
530 clock-names = "se";
531 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
532 pinctrl-names = "default";
537 compatible = "qcom,geni-i2c";
540 clock-names = "se";
542 pinctrl-0 = <&qup_i2c5_data_clk>;
543 pinctrl-names = "default";
544 #address-cells = <1>;
545 #size-cells = <0>;
550 compatible = "qcom,geni-spi";
552 #address-cells = <1>;
553 #size-cells = <0>;
556 clock-names = "se";
557 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
558 pinctrl-names = "default";
563 compatible = "qcom,geni-i2c";
566 clock-names = "se";
568 pinctrl-0 = <&qup_i2c6_data_clk>;
569 pinctrl-names = "default";
570 #address-cells = <1>;
571 #size-cells = <0>;
576 compatible = "qcom,geni-spi";
578 #address-cells = <1>;
579 #size-cells = <0>;
582 clock-names = "se";
583 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
584 pinctrl-names = "default";
589 compatible = "qcom,geni-debug-uart";
592 clock-names = "se";
593 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
594 pinctrl-names = "default";
600 gpi_dma1: dma-controller@a00000 {
601 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
615 dma-channels = <12>;
616 dma-channel-mask = <0x3f>;
618 #dma-cells = <3>;
622 compatible = "qcom,geni-se-qup";
626 clock-names = "m-ahb", "s-ahb";
628 #address-cells = <2>;
629 #size-cells = <2>;
634 compatible = "qcom,geni-uart";
637 clock-names = "se";
638 pinctrl-0 = <&qup_uart8_default>;
639 pinctrl-names = "default";
641 #address-cells = <1>;
642 #size-cells = <0>;
647 compatible = "qcom,geni-i2c";
650 clock-names = "se";
652 pinctrl-0 = <&qup_i2c9_data_clk>;
653 pinctrl-names = "default";
654 #address-cells = <1>;
655 #size-cells = <0>;
660 compatible = "qcom,geni-spi";
662 #address-cells = <1>;
663 #size-cells = <0>;
666 clock-names = "se";
667 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
668 pinctrl-names = "default";
673 compatible = "qcom,geni-i2c";
676 clock-names = "se";
678 pinctrl-0 = <&qup_i2c10_data_clk>;
679 pinctrl-names = "default";
680 #address-cells = <1>;
681 #size-cells = <0>;
686 compatible = "qcom,geni-spi";
688 #address-cells = <1>;
689 #size-cells = <0>;
692 clock-names = "se";
693 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
694 pinctrl-names = "default";
699 compatible = "qcom,geni-i2c";
702 clock-names = "se";
704 pinctrl-0 = <&qup_i2c11_data_clk>;
705 pinctrl-names = "default";
706 #address-cells = <1>;
707 #size-cells = <0>;
712 compatible = "qcom,geni-spi";
714 #address-cells = <1>;
715 #size-cells = <0>;
718 clock-names = "se";
719 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
720 pinctrl-names = "default";
725 compatible = "qcom,geni-i2c";
728 clock-names = "se";
730 pinctrl-0 = <&qup_i2c12_data_clk>;
731 pinctrl-names = "default";
732 #address-cells = <1>;
733 #size-cells = <0>;
738 compatible = "qcom,geni-spi";
740 #address-cells = <1>;
741 #size-cells = <0>;
744 clock-names = "se";
745 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
746 pinctrl-names = "default";
751 compatible = "qcom,geni-i2c";
754 clock-names = "se";
756 pinctrl-0 = <&qup_i2c13_data_clk>;
757 pinctrl-names = "default";
758 #address-cells = <1>;
759 #size-cells = <0>;
764 compatible = "qcom,geni-uart";
767 clock-names = "se";
768 pinctrl-0 = <&qup_uart13_default>;
769 pinctrl-names = "default";
771 #address-cells = <1>;
772 #size-cells = <0>;
777 compatible = "qcom,geni-spi";
779 #address-cells = <1>;
780 #size-cells = <0>;
783 clock-names = "se";
784 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
785 pinctrl-names = "default";
790 compatible = "qcom,geni-i2c";
793 clock-names = "se";
795 pinctrl-0 = <&qup_i2c14_data_clk>;
796 pinctrl-names = "default";
797 #address-cells = <1>;
798 #size-cells = <0>;
803 compatible = "qcom,geni-spi";
805 #address-cells = <1>;
806 #size-cells = <0>;
809 clock-names = "se";
810 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
811 pinctrl-names = "default";
816 compatible = "qcom,geni-i2c";
819 clock-names = "se";
821 pinctrl-0 = <&qup_i2c15_data_clk>;
822 pinctrl-names = "default";
823 #address-cells = <1>;
824 #size-cells = <0>;
829 compatible = "qcom,geni-spi";
831 #address-cells = <1>;
832 #size-cells = <0>;
835 clock-names = "se";
836 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
837 pinctrl-names = "default";
843 compatible = "qcom,qdu1000-system-noc";
845 qcom,bcm-voters = <&apps_bcm_voter>;
846 #interconnect-cells = <2>;
850 compatible = "qcom,tcsr-mutex";
852 #hwlock-cells = <1>;
856 compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
859 reg-names = "hc", "cqhci";
863 interrupt-names = "hc_irq", "pwr_irq";
868 clock-names = "iface",
876 interconnect-names = "sdhc-ddr", "cpu-sdhc";
877 power-domains = <&rpmhpd QDU1000_CX>;
878 operating-points-v2 = <&sdhc1_opp_table>;
881 dma-coherent;
883 bus-width = <8>;
885 qcom,dll-config = <0x0007642c>;
886 qcom,ddr-config = <0x80040868>;
890 sdhc1_opp_table: opp-table {
891 compatible = "operating-points-v2";
893 opp-384000000 {
894 opp-hz = /bits/ 64 <384000000>;
895 required-opps = <&rpmhpd_opp_nom>;
896 opp-peak-kBps = <6528000 1652800>;
897 opp-avg-kBps = <400000 0>;
902 pdc: interrupt-controller@b220000 {
903 compatible = "qcom,qdu1000-pdc", "qcom,pdc";
905 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
907 #interrupt-cells = <2>;
908 interrupt-parent = <&intc>;
909 interrupt-controller;
913 compatible = "qcom,spmi-pmic-arb";
919 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
920 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
921 interrupt-names = "periph_irq";
924 #address-cells = <2>;
925 #size-cells = <0>;
926 interrupt-controller;
927 #interrupt-cells = <4>;
931 compatible = "qcom,qdu1000-tlmm";
934 gpio-controller;
935 #gpio-cells = <2>;
936 interrupt-controller;
937 #interrupt-cells = <2>;
938 gpio-ranges = <&tlmm 0 0 151>;
939 wakeup-parent = <&pdc>;
941 qup_uart0_default: qup-uart0-default-state {
946 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
951 qup_spi1_data_clk: qup-spi1-data-clk-state {
956 qup_spi1_cs: qup-spi1-cs-state {
961 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
966 qup_spi2_data_clk: qup-spi2-data-clk-state {
971 qup_spi2_cs: qup-spi2-cs-state {
976 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
981 qup_spi3_data_clk: qup-spi3-data-clk-state {
986 qup_spi3_cs: qup-spi3-cs-state {
991 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
996 qup_spi4_data_clk: qup-spi4-data-clk-state {
1001 qup_spi4_cs: qup-spi4-cs-state {
1006 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1011 qup_spi5_data_clk: qup-spi5-data-clk-state {
1016 qup_spi5_cs: qup-spi5-cs-state {
1021 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1026 qup_spi6_data_clk: qup-spi6-data-clk-state {
1031 qup_spi6_cs: qup-spi6-cs-state {
1036 qup_uart7_rx: qup-uart7-rx-state {
1041 qup_uart7_tx: qup-uart7-tx-state {
1046 qup_uart8_default: qup-uart8-default-state {
1051 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
1056 qup_spi9_data_clk: qup-spi9-data-clk-state {
1061 qup_spi9_cs: qup-spi9-cs-state {
1066 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
1071 qup_spi10_data_clk: qup-spi10-data-clk-state {
1076 qup_spi10_cs: qup-spi10-cs-state {
1081 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
1086 qup_spi11_data_clk: qup-spi11-data-clk-state {
1091 qup_spi11_cs: qup-spi11-cs-state {
1096 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
1101 qup_spi12_data_clk: qup-spi12-data-clk-state {
1106 qup_spi12_cs: qup-spi12-cs-state {
1111 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
1116 qup_spi13_data_clk: qup-spi13-data-clk-state {
1121 qup_spi13_cs: qup-spi13-cs-state {
1126 qup_uart13_default: qup-uart13-default-state {
1131 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
1136 qup_spi14_data_clk: qup-spi14-data-clk-state {
1141 qup_spi14_cs: qup-spi14-cs-state {
1146 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
1151 qup_spi15_data_clk: qup-spi15-data-clk-state {
1156 qup_spi15_cs: qup-spi15-cs-state {
1161 sdc_on_state: sdc-on-state {
1162 clk-pins {
1164 drive-strength = <16>;
1165 bias-disable;
1168 cmd-pins {
1170 drive-strength = <10>;
1171 bias-pull-up;
1174 data-pins {
1176 drive-strength = <10>;
1177 bias-pull-up;
1180 rclk-pins {
1182 bias-pull-down;
1186 sdc_off_state: sdc-off-state {
1187 clk-pins {
1189 drive-strength = <2>;
1190 bias-disable;
1193 cmd-pins {
1195 drive-strength = <2>;
1196 bias-pull-up;
1199 data-pins {
1201 drive-strength = <2>;
1202 bias-pull-up;
1205 rclk-pins {
1207 bias-pull-down;
1213 compatible = "qcom,qdu1000-imem", "syscon", "simple-mfd";
1216 #address-cells = <1>;
1217 #size-cells = <1>;
1219 pil-reloc@94c {
1220 compatible = "qcom,pil-reloc-info";
1226 compatible = "qcom,qdu1000-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1228 #iommu-cells = <2>;
1229 #global-interrupts = <2>;
1281 intc: interrupt-controller@17200000 {
1282 compatible = "arm,gic-v3";
1286 #interrupt-cells = <3>;
1287 interrupt-controller;
1288 #redistributor-regions = <1>;
1289 redistributor-stride = <0x0 0x20000>;
1293 compatible = "arm,armv7-timer-mem";
1295 #address-cells = <1>;
1296 #size-cells = <1>;
1304 frame-number = <0>;
1310 frame-number = <1>;
1318 frame-number = <2>;
1325 frame-number = <3>;
1332 frame-number = <4>;
1339 frame-number = <5>;
1346 frame-number = <6>;
1352 compatible = "qcom,rpmh-rsc";
1356 reg-names = "drv-0", "drv-1", "drv-2";
1360 qcom,tcs-offset = <0xd00>;
1361 qcom,drv-id = <2>;
1362 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1365 power-domains = <&CLUSTER_PD>;
1367 apps_bcm_voter: bcm-voter {
1368 compatible = "qcom,bcm-voter";
1371 rpmhcc: clock-controller {
1372 compatible = "qcom,qdu1000-rpmh-clk";
1374 clock-names = "xo";
1375 #clock-cells = <1>;
1378 rpmhpd: power-controller {
1379 compatible = "qcom,qdu1000-rpmhpd";
1380 #power-domain-cells = <1>;
1381 operating-points-v2 = <&rpmhpd_opp_table>;
1383 rpmhpd_opp_table: opp-table {
1384 compatible = "operating-points-v2";
1387 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1391 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1395 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1399 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1403 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1407 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1411 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1415 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1419 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1423 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1430 compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss";
1432 reg-names = "freq-domain0", "freq-domain1";
1434 clock-names = "xo", "alternate";
1435 #freq-domain-cells = <1>;
1436 #clock-cells = <1>;
1440 compatible = "qcom,qdu1000-gem-noc";
1442 qcom,bcm-voters = <&apps_bcm_voter>;
1443 #interconnect-cells = <2>;
1446 system-cache-controller@19200000 {
1447 compatible = "qcom,qdu1000-llcc";
1451 reg-names = "llcc_base",
1456 nvmem-cells = <&multi_chan_ddr>;
1457 nvmem-cell-names = "multi-chan-ddr";
1461 compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom";
1463 #address-cells = <1>;
1464 #size-cells = <1>;
1466 multi_chan_ddr: multi-chan-ddr@12b {
1474 compatible = "arm,armv8-timer";