Lines Matching +full:0 +full:x12c00000
24 #size-cells = <0>;
26 CPU0: cpu@0 {
29 reg = <0x0 0x0>;
30 clocks = <&cpufreq_hw 0>;
34 qcom,freq-domains = <&cpufreq_hw 0>;
52 reg = <0x0 0x100>;
53 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domains = <&cpufreq_hw 0>;
70 reg = <0x0 0x200>;
71 clocks = <&cpufreq_hw 0>;
75 qcom,freq-domains = <&cpufreq_hw 0>;
88 reg = <0x0 0x300>;
89 clocks = <&cpufreq_hw 0>;
93 qcom,freq-domains = <&cpufreq_hw 0>;
127 CPU_OFF: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x40000004>;
138 CLUSTER_SLEEP_0: cluster-sleep-0 {
143 arm,psci-suspend-param = <0x41000044>;
151 arm,psci-suspend-param = <0x41003344>;
161 mc_virt: interconnect-0 {
176 reg = <0x0 0x80000000 0x0 0x0>;
189 #power-domain-cells = <0>;
195 #power-domain-cells = <0>;
201 #power-domain-cells = <0>;
207 #power-domain-cells = <0>;
213 #power-domain-cells = <0>;
224 reg = <0x0 0x80000000 0x0 0x600000>;
229 reg = <0x0 0x80600000 0x0 0x40000>;
234 reg = <0x0 0x80640000 0x0 0x1c0000>;
239 reg = <0x0 0x80800000 0x0 0x60000>;
245 reg = <0x0 0x80860000 0x0 0x20000>;
250 reg = <0x0 0x80880000 0x0 0x20000>;
255 reg = <0x0 0x808a0000 0x0 0x40000>;
260 reg = <0x0 0x808e0000 0x0 0x4000>;
265 reg = <0x0 0x808e4000 0x0 0x10000>;
271 reg = <0x0 0x80900000 0x0 0x200000>;
277 reg = <0x0 0x80b00000 0x0 0x100000>;
282 reg = <0x0 0x80c00000 0x0 0x40000>;
287 reg = <0x0 0x81d00000 0x0 0x100000>;
292 reg = <0x0 0x81e00000 0x0 0x500000>;
297 reg = <0x0 0x82300000 0x0 0x500000>;
302 reg = <0x0 0x82800000 0x0 0xa00000>;
307 reg = <0x0 0x83200000 0x0 0x400000>;
312 reg = <0x0 0x83600000 0x0 0x400000>;
317 reg = <0x0 0x83a00000 0x0 0x400000>;
321 /* Linux kernel image is loaded at 0x83e00000 */
324 reg = <0x0 0x8be00000 0x0 0x10000>;
329 reg = <0x0 0x8be10000 0x0 0x14000>;
334 reg = <0x0 0x8c000000 0x0 0x12c00000>;
339 reg = <0x0 0x9ec00000 0x0 0x80000>;
344 reg = <0x0 0xa0000000 0x0 0x19600000>;
349 reg = <0x0 0xb9600000 0x0 0x6a00000>;
354 reg = <0x0 0xc0000000 0x0 0x3200000>;
359 reg = <0x0 0xc3200000 0x0 0x12c00000>;
364 soc: soc@0 {
368 ranges = <0 0 0 0 0x10 0>;
369 dma-ranges = <0 0 0 0 0x10 0>;
373 reg = <0x0 0x80000 0x0 0x1f4200>;
376 <0>,
377 <0>,
378 <0>;
386 reg = <0x0 0x900000 0x0 0x60000>;
400 dma-channel-mask = <0x3f>;
401 iommus = <&apps_smmu 0xf6 0x0>;
407 reg = <0x0 0x9c0000 0x0 0x2000>;
411 iommus = <&apps_smmu 0xe3 0x0>;
412 interconnects = <&clk_virt MASTER_QUP_CORE_0 0
413 &clk_virt SLAVE_QUP_CORE_0 0>;
423 reg = <0x0 0x980000 0x0 0x4000>;
426 pinctrl-0 = <&qup_uart0_default>;
434 reg = <0x0 0x984000 0x0 0x4000>;
438 pinctrl-0 = <&qup_i2c1_data_clk>;
441 #size-cells = <0>;
447 reg = <0x0 0x984000 0x0 0x4000>;
449 #size-cells = <0>;
453 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
460 reg = <0x0 0x988000 0x0 0x4000>;
464 pinctrl-0 = <&qup_i2c2_data_clk>;
467 #size-cells = <0>;
473 reg = <0x0 0x988000 0x0 0x4000>;
475 #size-cells = <0>;
479 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
486 reg = <0x0 0x98c000 0x0 0x4000>;
490 pinctrl-0 = <&qup_i2c3_data_clk>;
493 #size-cells = <0>;
499 reg = <0x0 0x98c000 0x0 0x4000>;
501 #size-cells = <0>;
505 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
512 reg = <0x0 0x990000 0x0 0x4000>;
516 pinctrl-0 = <&qup_i2c4_data_clk>;
519 #size-cells = <0>;
525 reg = <0x0 0x990000 0x0 0x4000>;
527 #size-cells = <0>;
531 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
538 reg = <0x0 0x994000 0x0 0x4000>;
542 pinctrl-0 = <&qup_i2c5_data_clk>;
545 #size-cells = <0>;
551 reg = <0x0 0x994000 0x0 0x4000>;
553 #size-cells = <0>;
557 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
564 reg = <0x0 0x998000 0x0 0x4000>;
568 pinctrl-0 = <&qup_i2c6_data_clk>;
571 #size-cells = <0>;
577 reg = <0x0 0x998000 0x0 0x4000>;
579 #size-cells = <0>;
583 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
590 reg = <0x0 0x99c000 0x0 0x4000>;
593 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
602 reg = <0x0 0xa00000 0x0 0x60000>;
616 dma-channel-mask = <0x3f>;
617 iommus = <&apps_smmu 0x116 0x0>;
623 reg = <0x0 0xac0000 0x0 0x2000>;
627 iommus = <&apps_smmu 0x103 0x0>;
635 reg = <0x0 0xa80000 0x0 0x4000>;
638 pinctrl-0 = <&qup_uart8_default>;
642 #size-cells = <0>;
648 reg = <0x0 0xa84000 0x0 0x4000>;
652 pinctrl-0 = <&qup_i2c9_data_clk>;
655 #size-cells = <0>;
661 reg = <0x0 0xa84000 0x0 0x4000>;
663 #size-cells = <0>;
667 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
674 reg = <0x0 0xa88000 0x0 0x4000>;
678 pinctrl-0 = <&qup_i2c10_data_clk>;
681 #size-cells = <0>;
687 reg = <0x0 0xa88000 0x0 0x4000>;
689 #size-cells = <0>;
693 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
700 reg = <0x0 0xa8c000 0x0 0x4000>;
704 pinctrl-0 = <&qup_i2c11_data_clk>;
707 #size-cells = <0>;
713 reg = <0x0 0xa8c000 0x0 0x4000>;
715 #size-cells = <0>;
719 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
726 reg = <0x0 0xa90000 0x0 0x4000>;
730 pinctrl-0 = <&qup_i2c12_data_clk>;
733 #size-cells = <0>;
739 reg = <0x0 0xa90000 0x0 0x4000>;
741 #size-cells = <0>;
745 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
752 reg = <0x0 0xa94000 0x0 0x4000>;
756 pinctrl-0 = <&qup_i2c13_data_clk>;
759 #size-cells = <0>;
765 reg = <0x0 0xa94000 0x0 0x4000>;
768 pinctrl-0 = <&qup_uart13_default>;
772 #size-cells = <0>;
778 reg = <0x0 0xa94000 0x0 0x4000>;
780 #size-cells = <0>;
784 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
791 reg = <0x0 0xa98000 0x0 0x4000>;
795 pinctrl-0 = <&qup_i2c14_data_clk>;
798 #size-cells = <0>;
804 reg = <0x0 0xa98000 0x0 0x4000>;
806 #size-cells = <0>;
810 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
817 reg = <0x0 0xa9c000 0x0 0x4000>;
821 pinctrl-0 = <&qup_i2c15_data_clk>;
824 #size-cells = <0>;
830 reg = <0x0 0xa9c000 0x0 0x4000>;
832 #size-cells = <0>;
836 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
844 reg = <0x0 0x1640000 0x0 0x45080>;
851 reg = <0x0 0x1f40000 0x0 0x20000>;
857 reg = <0x0 0x08804000 0x0 0x1000>,
858 <0x0 0x08805000 0x0 0x1000>;
874 interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
875 <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
880 iommus = <&apps_smmu 0x80 0x0>;
885 qcom,dll-config = <0x0007642c>;
886 qcom,ddr-config = <0x80040868>;
897 opp-avg-kBps = <400000 0>;
904 reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
905 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
914 reg = <0x0 0xc400000 0x0 0x3000>,
915 <0x0 0xc500000 0x0 0x400000>,
916 <0x0 0xc440000 0x0 0x80000>,
917 <0x0 0xc4c0000 0x0 0x10000>,
918 <0x0 0xc42d000 0x0 0x4000>;
922 qcom,ee = <0>;
923 qcom,channel = <0>;
925 #size-cells = <0>;
932 reg = <0x0 0xf000000 0x0 0x1000000>;
938 gpio-ranges = <&tlmm 0 0 151>;
1214 reg = <0 0x14680000 0 0x1000>;
1215 ranges = <0 0 0x14680000 0x1000>;
1221 reg = <0x94c 0xc8>;
1227 reg = <0x0 0x15000000 0x0 0x100000>;
1283 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
1284 <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */
1289 redistributor-stride = <0x0 0x20000>;
1294 reg = <0x0 0x17420000 0x0 0x1000>;
1297 ranges = <0x0 0x0 0x0 0x20000000>;
1300 reg = <0x17421000 0x1000>,
1301 <0x17422000 0x1000>;
1304 frame-number = <0>;
1308 reg = <0x17423000 0x1000>;
1315 reg = <0x17425000 0x1000>,
1316 <0x17426000 0x1000>;
1323 reg = <0x17427000 0x1000>;
1330 reg = <0x17429000 0x1000>;
1337 reg = <0x1742b000 0x1000>;
1344 reg = <0x1742d000 0x1000>;
1353 reg = <0x0 0x17a00000 0x0 0x10000>,
1354 <0x0 0x17a10000 0x0 0x10000>,
1355 <0x0 0x17a20000 0x0 0x10000>;
1356 reg-names = "drv-0", "drv-1", "drv-2";
1360 qcom,tcs-offset = <0xd00>;
1363 <WAKE_TCS 3>, <CONTROL_TCS 0>;
1431 reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>;
1441 reg = <0x0 0x19100000 0x0 0xB8080>;
1448 reg = <0 0x19200000 0 0xd80000>,
1449 <0 0x1a200000 0 0x80000>,
1450 <0 0x221c8128 0 0x4>;
1462 reg = <0 0x221c8000 0 0x1000>;
1467 reg = <0x12b 0x1>;
1468 bits = <0 2>;