Lines Matching +full:crit +full:- +full:soc +full:- +full:level
1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
8 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&intc>;
16 #address-cells = <2>;
17 #size-cells = <2>;
22 xo_board: xo-board {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <19200000>;
28 sleep_clk: sleep-clk {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <32768>;
36 #address-cells = <1>;
37 #size-cells = <0>;
41 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 cpu-idle-states = <&CPU_SLEEP_0>;
45 next-level-cache = <&L2_0>;
46 #cooling-cells = <2>;
48 operating-points-v2 = <&cpu_opp_table>;
49 power-domains = <&cpr>;
50 power-domain-names = "cpr";
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
58 cpu-idle-states = <&CPU_SLEEP_0>;
59 next-level-cache = <&L2_0>;
60 #cooling-cells = <2>;
62 operating-points-v2 = <&cpu_opp_table>;
63 power-domains = <&cpr>;
64 power-domain-names = "cpr";
69 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 cpu-idle-states = <&CPU_SLEEP_0>;
73 next-level-cache = <&L2_0>;
74 #cooling-cells = <2>;
76 operating-points-v2 = <&cpu_opp_table>;
77 power-domains = <&cpr>;
78 power-domain-names = "cpr";
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 cpu-idle-states = <&CPU_SLEEP_0>;
87 next-level-cache = <&L2_0>;
88 #cooling-cells = <2>;
90 operating-points-v2 = <&cpu_opp_table>;
91 power-domains = <&cpr>;
92 power-domain-names = "cpr";
95 L2_0: l2-cache {
97 cache-level = <2>;
98 cache-unified;
101 idle-states {
102 entry-method = "psci";
104 CPU_SLEEP_0: cpu-sleep-0 {
105 compatible = "arm,idle-state";
106 idle-state-name = "standalone-power-collapse";
107 arm,psci-suspend-param = <0x40000003>;
108 entry-latency-us = <125>;
109 exit-latency-us = <180>;
110 min-residency-us = <595>;
111 local-timer-stop;
116 cpu_opp_table: opp-table-cpu {
117 compatible = "operating-points-v2-kryo-cpu";
118 opp-shared;
120 opp-1094400000 {
121 opp-hz = /bits/ 64 <1094400000>;
122 required-opps = <&cpr_opp1>;
124 opp-1248000000 {
125 opp-hz = /bits/ 64 <1248000000>;
126 required-opps = <&cpr_opp2>;
128 opp-1401600000 {
129 opp-hz = /bits/ 64 <1401600000>;
130 required-opps = <&cpr_opp3>;
134 cpr_opp_table: opp-table-cpr {
135 compatible = "operating-points-v2-qcom-level";
138 opp-level = <1>;
139 qcom,opp-fuse-level = <1>;
142 opp-level = <2>;
143 qcom,opp-fuse-level = <2>;
146 opp-level = <3>;
147 qcom,opp-fuse-level = <3>;
153 compatible = "qcom,scm-qcs404", "qcom,scm";
154 #reset-cells = <1>;
165 compatible = "arm,psci-1.0";
170 compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc";
172 glink-edge {
173 compatible = "qcom,glink-rpm";
176 qcom,rpm-msg-ram = <&rpm_msg_ram>;
179 rpm_requests: rpm-requests {
180 compatible = "qcom,rpm-qcs404";
181 qcom,glink-channels = "rpm_requests";
183 rpmcc: clock-controller {
184 compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
185 #clock-cells = <1>;
187 clock-names = "xo";
190 rpmpd: power-controller {
191 compatible = "qcom,qcs404-rpmpd";
192 #power-domain-cells = <1>;
193 operating-points-v2 = <&rpmpd_opp_table>;
195 rpmpd_opp_table: opp-table {
196 compatible = "operating-points-v2";
199 opp-level = <16>;
203 opp-level = <32>;
207 opp-level = <48>;
211 opp-level = <64>;
215 opp-level = <128>;
219 opp-level = <192>;
223 opp-level = <256>;
227 opp-level = <320>;
231 opp-level = <384>;
235 opp-level = <416>;
239 opp-level = <512>;
247 reserved-memory {
248 #address-cells = <2>;
249 #size-cells = <2>;
254 no-map;
259 no-map;
264 no-map;
269 no-map;
274 no-map;
279 no-map;
284 no-map;
289 no-map;
294 no-map;
301 memory-region = <&smem_region>;
302 qcom,rpm-msg-ram = <&rpm_msg_ram>;
307 soc: soc@0 { label
308 #address-cells = <1>;
309 #size-cells = <1>;
311 compatible = "simple-bus";
313 turingcc: clock-controller@800000 {
314 compatible = "qcom,qcs404-turingcc";
318 #clock-cells = <1>;
319 #reset-cells = <1>;
325 compatible = "qcom,rpm-msg-ram";
330 compatible = "qcom,usb-ss-28nm-phy";
332 #phy-cells = <0>;
336 clock-names = "ref", "ahb", "pipe";
339 reset-names = "com", "phy";
344 compatible = "qcom,usb-hs-28nm-femtophy";
346 #phy-cells = <0>;
350 clock-names = "ref", "ahb", "sleep";
353 reset-names = "phy", "por";
358 compatible = "qcom,usb-hs-28nm-femtophy";
360 #phy-cells = <0>;
364 clock-names = "ref", "ahb", "sleep";
367 reset-names = "phy", "por";
372 compatible = "qcom,qcs404-qfprom", "qcom,qfprom";
374 #address-cells = <1>;
375 #size-cells = <1>;
381 tsens_s0_p1: s0-p1@1f8 {
386 tsens_s0_p2: s0-p2@1f8 {
391 tsens_s1_p1: s1-p1@1f9 {
396 tsens_s1_p2: s1-p2@1fa {
401 tsens_s2_p1: s2-p1@1fb {
406 tsens_s2_p2: s2-p2@1fb {
411 tsens_s3_p1: s3-p1@1fc {
416 tsens_s3_p2: s3-p2@1fd {
421 tsens_s4_p1: s4-p1@1fe {
426 tsens_s4_p2: s4-p2@1fe {
431 tsens_s5_p1: s5-p1@200 {
436 tsens_s5_p2: s5-p2@200 {
441 tsens_s6_p1: s6-p1@201 {
446 tsens_s6_p2: s6-p2@202 {
451 tsens_s7_p1: s7-p1@203 {
456 tsens_s7_p2: s7-p2@203 {
461 tsens_s8_p1: s8-p1@204 {
466 tsens_s8_p2: s8-p2@205 {
471 tsens_s9_p1: s9-p1@206 {
476 tsens_s9_p2: s9-p2@206 {
551 compatible = "qcom,prng-ee";
554 clock-names = "core";
559 compatible = "qcom,qcs404-bimc";
560 #interconnect-cells = <1>;
561 clock-names = "bus", "bus_a";
566 tsens: thermal-sensor@4a9000 {
567 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
570 nvmem-cells = <&tsens_mode>,
582 nvmem-cell-names = "mode",
596 interrupt-names = "uplow";
597 #thermal-sensor-cells = <1>;
602 compatible = "qcom,qcs404-pcnoc";
603 #interconnect-cells = <1>;
604 clock-names = "bus", "bus_a";
611 compatible = "qcom,qcs404-snoc";
612 #interconnect-cells = <1>;
613 clock-names = "bus", "bus_a";
619 compatible = "qcom,qcs404-cdsp-pas";
622 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
627 interrupt-names = "wdog", "fatal", "ready",
628 "handover", "stop-ack";
631 clock-names = "xo";
643 * clock-names = "xo",
652 * reset-names = "restart";
653 * qcom,halt-regs = <&tcsr 0x19004>;
656 memory-region = <&cdsp_fw_mem>;
658 qcom,smem-states = <&cdsp_smp2p_out 0>;
659 qcom,smem-state-names = "stop";
663 glink-edge {
666 qcom,remote-pid = <5>;
674 compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
676 #address-cells = <1>;
677 #size-cells = <1>;
683 clock-names = "core", "iface", "sleep", "mock_utmi";
684 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
686 assigned-clock-rates = <19200000>, <200000000>;
694 phy-names = "usb2-phy", "usb3-phy";
695 snps,has-lpm-erratum;
696 snps,hird-threshold = /bits/ 8 <0x10>;
703 compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
705 #address-cells = <1>;
706 #size-cells = <1>;
712 clock-names = "core", "iface", "sleep", "mock_utmi";
713 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
715 assigned-clock-rates = <19200000>, <133333333>;
723 phy-names = "usb2-phy";
724 snps,has-lpm-erratum;
725 snps,hird-threshold = /bits/ 8 <0x10>;
732 compatible = "qcom,qcs404-pinctrl";
736 reg-names = "south", "north", "east";
738 gpio-ranges = <&tlmm 0 0 120>;
739 gpio-controller;
740 #gpio-cells = <2>;
741 interrupt-controller;
742 #interrupt-cells = <2>;
744 blsp1_i2c0_default: blsp1-i2c0-default-state {
749 blsp1_i2c1_default: blsp1-i2c1-default-state {
754 blsp1_i2c2_default: blsp1-i2c2-default-state {
755 sda-pins {
760 scl-pins {
766 blsp1_i2c3_default: blsp1-i2c3-default-state {
771 blsp1_i2c4_default: blsp1-i2c4-default-state {
776 blsp1_uart0_default: blsp1-uart0-default-state {
781 blsp1_uart1_default: blsp1-uart1-default-state {
786 blsp1_uart2_default: blsp1-uart2-default-state {
787 rx-pins {
792 tx-pins {
798 blsp1_uart3_default: blsp1-uart3-default-state {
799 cts-pins {
804 rts-tx-pins {
809 rx-pins {
815 blsp2_i2c0_default: blsp2-i2c0-default-state {
820 blsp1_spi0_default: blsp1-spi0-default-state {
825 blsp1_spi1_default: blsp1-spi1-default-state {
826 mosi-pins {
831 miso-pins {
836 cs-n-pins {
841 clk-pins {
847 blsp1_spi2_default: blsp1-spi2-default-state {
852 blsp1_spi3_default: blsp1-spi3-default-state {
857 blsp1_spi4_default: blsp1-spi4-default-state {
862 blsp2_spi0_default: blsp2-spi0-default-state {
867 blsp2_uart0_default: blsp2-uart0-default-state {
873 gcc: clock-controller@1800000 {
874 compatible = "qcom,gcc-qcs404";
876 #clock-cells = <1>;
877 #reset-cells = <1>;
878 #power-domain-cells = <1>;
887 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
888 assigned-clock-rates = <19200000>;
892 compatible = "qcom,tcsr-mutex";
894 #hwlock-cells = <1>;
898 compatible = "qcom,qcs404-tcsr", "syscon";
903 compatible = "qcom,rpm-stats";
908 compatible = "qcom,spmi-pmic-arb";
914 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
915 interrupt-names = "periph_irq";
919 #address-cells = <2>;
920 #size-cells = <0>;
921 interrupt-controller;
922 #interrupt-cells = <4>;
926 compatible = "qcom,qcs404-wcss-pas";
929 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
934 interrupt-names = "wdog", "fatal", "ready",
935 "handover", "stop-ack";
938 clock-names = "xo";
940 memory-region = <&wlan_fw_mem>;
942 qcom,smem-states = <&wcss_smp2p_out 0>;
943 qcom,smem-state-names = "stop";
947 glink-edge {
950 qcom,remote-pid = <1>;
958 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
964 reset-names = "phy", "pipe";
966 clock-output-names = "pcie_0_pipe_clk";
967 #clock-cells = <0>;
968 #phy-cells = <0>;
974 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
976 reg-names = "hc", "cqhci";
980 interrupt-names = "hc_irq", "pwr_irq";
985 clock-names = "iface", "core", "xo";
990 blsp1_dma: dma-controller@7884000 {
991 compatible = "qcom,bam-v1.7.0";
995 clock-names = "bam_clk";
996 #dma-cells = <1>;
1002 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1006 clock-names = "core", "iface";
1008 dma-names = "tx", "rx";
1009 pinctrl-names = "default";
1010 pinctrl-0 = <&blsp1_uart0_default>;
1015 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1019 clock-names = "core", "iface";
1021 dma-names = "tx", "rx";
1022 pinctrl-names = "default";
1023 pinctrl-0 = <&blsp1_uart1_default>;
1028 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1032 clock-names = "core", "iface";
1034 dma-names = "tx", "rx";
1035 pinctrl-names = "default";
1036 pinctrl-0 = <&blsp1_uart2_default>;
1041 compatible = "qcom,qcs404-ethqos";
1044 reg-names = "stmmaceth", "rgmii";
1045 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
1052 interrupt-names = "macirq", "eth_lpi";
1055 rx-fifo-depth = <4096>;
1056 tx-fifo-depth = <4096>;
1062 compatible = "qcom,wcn3990-wifi";
1064 reg-names = "membase";
1065 memory-region = <&wlan_msa_mem>;
1082 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1086 clock-names = "core", "iface";
1088 dma-names = "tx", "rx";
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&blsp1_uart3_default>;
1095 compatible = "qcom,i2c-qup-v2.2.1";
1100 clock-names = "core", "iface";
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&blsp1_i2c0_default>;
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1109 compatible = "qcom,spi-qup-v2.2.1";
1114 clock-names = "core", "iface";
1115 pinctrl-names = "default";
1116 pinctrl-0 = <&blsp1_spi0_default>;
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1123 compatible = "qcom,i2c-qup-v2.2.1";
1128 clock-names = "core", "iface";
1129 pinctrl-names = "default";
1130 pinctrl-0 = <&blsp1_i2c1_default>;
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1137 compatible = "qcom,spi-qup-v2.2.1";
1142 clock-names = "core", "iface";
1143 pinctrl-names = "default";
1144 pinctrl-0 = <&blsp1_spi1_default>;
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1151 compatible = "qcom,i2c-qup-v2.2.1";
1156 clock-names = "core", "iface";
1157 pinctrl-names = "default";
1158 pinctrl-0 = <&blsp1_i2c2_default>;
1159 #address-cells = <1>;
1160 #size-cells = <0>;
1165 compatible = "qcom,spi-qup-v2.2.1";
1170 clock-names = "core", "iface";
1171 pinctrl-names = "default";
1172 pinctrl-0 = <&blsp1_spi2_default>;
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1179 compatible = "qcom,i2c-qup-v2.2.1";
1184 clock-names = "core", "iface";
1185 pinctrl-names = "default";
1186 pinctrl-0 = <&blsp1_i2c3_default>;
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1193 compatible = "qcom,spi-qup-v2.2.1";
1198 clock-names = "core", "iface";
1199 pinctrl-names = "default";
1200 pinctrl-0 = <&blsp1_spi3_default>;
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1207 compatible = "qcom,i2c-qup-v2.2.1";
1212 clock-names = "core", "iface";
1213 pinctrl-names = "default";
1214 pinctrl-0 = <&blsp1_i2c4_default>;
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1221 compatible = "qcom,spi-qup-v2.2.1";
1226 clock-names = "core", "iface";
1227 pinctrl-names = "default";
1228 pinctrl-0 = <&blsp1_spi4_default>;
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1234 blsp2_dma: dma-controller@7ac4000 {
1235 compatible = "qcom,bam-v1.7.0";
1239 clock-names = "bam_clk";
1240 #dma-cells = <1>;
1246 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1250 clock-names = "core", "iface";
1252 dma-names = "tx", "rx";
1253 pinctrl-names = "default";
1254 pinctrl-0 = <&blsp2_uart0_default>;
1259 compatible = "qcom,i2c-qup-v2.2.1";
1264 clock-names = "core", "iface";
1265 pinctrl-names = "default";
1266 pinctrl-0 = <&blsp2_i2c0_default>;
1267 #address-cells = <1>;
1268 #size-cells = <0>;
1273 compatible = "qcom,spi-qup-v2.2.1";
1278 clock-names = "core", "iface";
1279 pinctrl-names = "default";
1280 pinctrl-0 = <&blsp2_spi0_default>;
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1287 compatible = "qcom,qcs404-imem", "syscon", "simple-mfd";
1290 #address-cells = <1>;
1291 #size-cells = <1>;
1295 pil-reloc@94c {
1296 compatible = "qcom,pil-reloc-info";
1301 intc: interrupt-controller@b000000 {
1302 compatible = "qcom,msm-qgic2";
1303 interrupt-controller;
1304 #interrupt-cells = <3>;
1310 compatible = "qcom,qcs404-apcs-apps-global",
1311 "qcom,msm8916-apcs-kpss-global", "syscon";
1313 #mbox-cells = <1>;
1315 clock-names = "pll", "aux";
1316 #clock-cells = <0>;
1319 apcs_hfpll: clock-controller@b016000 {
1322 #clock-cells = <0>;
1323 clock-output-names = "apcs_hfpll";
1325 clock-names = "xo";
1329 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
1334 cpr: power-controller@b018000 {
1335 compatible = "qcom,qcs404-cpr", "qcom,cpr";
1339 clock-names = "ref";
1340 vdd-apc-supply = <&pms405_s3>;
1341 #power-domain-cells = <0>;
1342 operating-points-v2 = <&cpr_opp_table>;
1343 acc-syscon = <&tcsr>;
1345 nvmem-cells = <&cpr_efuse_quot_offset1>,
1358 nvmem-cell-names = "cpr_quotient_offset1",
1374 #address-cells = <1>;
1375 #size-cells = <1>;
1377 compatible = "arm,armv7-timer-mem";
1379 clock-frequency = <19200000>;
1382 frame-number = <0>;
1390 frame-number = <1>;
1397 frame-number = <2>;
1404 frame-number = <3>;
1411 frame-number = <4>;
1418 frame-number = <5>;
1425 frame-number = <6>;
1433 compatible = "qcom,qcs404-adsp-pas";
1436 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
1441 interrupt-names = "wdog", "fatal", "ready",
1442 "handover", "stop-ack";
1445 clock-names = "xo";
1447 memory-region = <&adsp_fw_mem>;
1449 qcom,smem-states = <&adsp_smp2p_out 0>;
1450 qcom,smem-state-names = "stop";
1454 glink-edge {
1457 qcom,remote-pid = <2>;
1465 compatible = "qcom,pcie-qcs404";
1470 reg-names = "dbi", "elbi", "parf", "config";
1472 linux,pci-domain = <0>;
1473 bus-range = <0x00 0xff>;
1474 num-lanes = <1>;
1475 #address-cells = <3>;
1476 #size-cells = <2>;
1482 interrupt-names = "msi";
1483 #interrupt-cells = <1>;
1484 interrupt-map-mask = <0 0 0 0x7>;
1485 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1493 clock-names = "iface", "aux", "master_bus", "slave_bus";
1501 reset-names = "axi_m",
1509 phy-names = "pciephy";
1516 compatible = "arm,armv8-timer";
1523 smp2p-adsp {
1528 qcom,local-pid = <0>;
1529 qcom,remote-pid = <2>;
1531 adsp_smp2p_out: master-kernel {
1532 qcom,entry-name = "master-kernel";
1533 #qcom,smem-state-cells = <1>;
1536 adsp_smp2p_in: slave-kernel {
1537 qcom,entry-name = "slave-kernel";
1538 interrupt-controller;
1539 #interrupt-cells = <2>;
1543 smp2p-cdsp {
1548 qcom,local-pid = <0>;
1549 qcom,remote-pid = <5>;
1551 cdsp_smp2p_out: master-kernel {
1552 qcom,entry-name = "master-kernel";
1553 #qcom,smem-state-cells = <1>;
1556 cdsp_smp2p_in: slave-kernel {
1557 qcom,entry-name = "slave-kernel";
1558 interrupt-controller;
1559 #interrupt-cells = <2>;
1563 smp2p-wcss {
1568 qcom,local-pid = <0>;
1569 qcom,remote-pid = <1>;
1571 wcss_smp2p_out: master-kernel {
1572 qcom,entry-name = "master-kernel";
1573 #qcom,smem-state-cells = <1>;
1576 wcss_smp2p_in: slave-kernel {
1577 qcom,entry-name = "slave-kernel";
1578 interrupt-controller;
1579 #interrupt-cells = <2>;
1583 thermal-zones {
1584 aoss-thermal {
1585 polling-delay-passive = <250>;
1586 polling-delay = <1000>;
1588 thermal-sensors = <&tsens 0>;
1591 aoss_alert0: trip-point0 {
1599 q6-hvx-thermal {
1600 polling-delay-passive = <250>;
1601 polling-delay = <1000>;
1603 thermal-sensors = <&tsens 1>;
1606 q6_hvx_alert0: trip-point0 {
1614 lpass-thermal {
1615 polling-delay-passive = <250>;
1616 polling-delay = <1000>;
1618 thermal-sensors = <&tsens 2>;
1621 lpass_alert0: trip-point0 {
1629 wlan-thermal {
1630 polling-delay-passive = <250>;
1631 polling-delay = <1000>;
1633 thermal-sensors = <&tsens 3>;
1636 wlan_alert0: trip-point0 {
1644 cluster-thermal {
1645 polling-delay-passive = <250>;
1646 polling-delay = <1000>;
1648 thermal-sensors = <&tsens 4>;
1651 cluster_alert0: trip-point0 {
1656 cluster_alert1: trip-point1 {
1661 cluster_crit: cluster-crit {
1667 cooling-maps {
1670 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1678 cpu0-thermal {
1679 polling-delay-passive = <250>;
1680 polling-delay = <1000>;
1682 thermal-sensors = <&tsens 5>;
1685 cpu0_alert0: trip-point0 {
1690 cpu0_alert1: trip-point1 {
1695 cpu0_crit: cpu-crit {
1701 cooling-maps {
1704 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1712 cpu1-thermal {
1713 polling-delay-passive = <250>;
1714 polling-delay = <1000>;
1716 thermal-sensors = <&tsens 6>;
1719 cpu1_alert0: trip-point0 {
1724 cpu1_alert1: trip-point1 {
1729 cpu1_crit: cpu-crit {
1735 cooling-maps {
1738 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1746 cpu2-thermal {
1747 polling-delay-passive = <250>;
1748 polling-delay = <1000>;
1750 thermal-sensors = <&tsens 7>;
1753 cpu2_alert0: trip-point0 {
1758 cpu2_alert1: trip-point1 {
1763 cpu2_crit: cpu-crit {
1769 cooling-maps {
1772 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1780 cpu3-thermal {
1781 polling-delay-passive = <250>;
1782 polling-delay = <1000>;
1784 thermal-sensors = <&tsens 8>;
1787 cpu3_alert0: trip-point0 {
1792 cpu3_alert1: trip-point1 {
1797 cpu3_crit: cpu-crit {
1803 cooling-maps {
1806 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1814 gpu-thermal {
1815 polling-delay-passive = <250>;
1816 polling-delay = <1000>;
1818 thermal-sensors = <&tsens 9>;
1821 gpu_alert0: trip-point0 {