Lines Matching +full:0 +full:x04a90000
27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
45 clocks = <&cpufreq_hw 0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
63 reg = <0x0 0x1>;
64 clocks = <&cpufreq_hw 0>;
69 qcom,freq-domain = <&cpufreq_hw 0>;
77 reg = <0x0 0x2>;
78 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
91 reg = <0x0 0x3>;
92 clocks = <&cpufreq_hw 0>;
97 qcom,freq-domain = <&cpufreq_hw 0>;
123 CLUSTER_SLEEP: cluster-sleep-0 {
125 arm,psci-suspend-param = <0x41000043>;
135 CPU_SLEEP: cpu-sleep-0 {
138 arm,psci-suspend-param = <0x40000003>;
159 reg = <0 0x40000000 0 0>;
172 #power-domain-cells = <0>;
178 #power-domain-cells = <0>;
184 #power-domain-cells = <0>;
190 #power-domain-cells = <0>;
196 #power-domain-cells = <0>;
208 mboxes = <&apcs_glb 0>;
272 reg = <0x0 0x45700000 0x0 0x600000>;
277 reg = <0x0 0x45e00000 0x0 0x140000>;
282 reg = <0x0 0x45fff000 0x0 0x1000>;
288 reg = <0x0 0x46000000 0x0 0x200000>;
296 reg = <0x0 0x4ab00000 0x0 0x6900000>;
301 reg = <0x0 0x51400000 0x0 0x500000>;
306 reg = <0x0 0x51900000 0x0 0x100000>;
311 reg = <0x0 0x51a00000 0x0 0x1c00000>;
316 reg = <0x0 0x53600000 0x0 0x10000>;
321 reg = <0x0 0x53610000 0x0 0x5000>;
327 reg = <0x0 0x53615000 0x0 0x2000>;
332 reg = <0x0 0x5c000000 0x0 0x00f00000>;
337 reg = <0x0 0x5cf00000 0x0 0x0100000>;
342 reg = <0x0 0x60000000 0x0 0x3900000>;
348 reg = <0x0 0x89b01000 0x0 0x200000>;
364 qcom,local-pid = <0>;
387 qcom,local-pid = <0>;
408 soc: soc@0 {
412 ranges = <0 0 0 0 0x10 0>;
413 dma-ranges = <0 0 0 0 0x10 0>;
417 reg = <0x0 0x00340000 0x0 0x20000>;
423 reg = <0x0 0x003c0000 0x0 0x40000>;
428 reg = <0x0 0x00500000 0x0 0x300000>;
431 gpio-ranges = <&tlmm 0 0 127>;
627 reg = <0x0 0x01400000 0x0 0x1f0000>;
637 reg = <0x0 0x01613000 0x0 0x180>;
645 #phy-cells = <0>;
652 reg = <0x0 0x01615000 0x0 0x1000>;
668 #clock-cells = <0>;
671 #phy-cells = <0>;
673 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
680 reg = <0x0 0x01b44000 0x0 0x3000>;
685 reg = <0x25b 0x1>;
692 reg = <0x0 0x01c40000 0x0 0x1100>,
693 <0x0 0x01e00000 0x0 0x2000000>,
694 <0x0 0x03e00000 0x0 0x100000>,
695 <0x0 0x03f00000 0x0 0xa0000>,
696 <0x0 0x01c0a000 0x0 0x26000>;
704 qcom,ee = <0>;
705 qcom,channel = <0>;
707 #size-cells = <0>;
714 reg = <0x0 0x04411000 0x0 0x1ff>,
715 <0x0 0x04410000 0x0 0x8>;
725 reg = <0x0 0x04453000 0x0 0x1000>;
732 reg = <0x0 0x045f0000 0x0 0x7000>;
737 reg = <0x0 0x04690000 0x0 0x10000>;
742 reg = <0x0 0x04744000 0x0 0x1000>,
743 <0x0 0x04745000 0x0 0x1000>,
744 <0x0 0x04748000 0x0 0x8000>;
765 iommus = <&apps_smmu 0xc0 0x0>;
767 qcom,dll-config = <0x000f642c>;
768 qcom,ddr-config = <0x80040868>;
776 reg = <0x0 0x04784000 0x0 0x1000>;
794 iommus = <&apps_smmu 0xa0 0x0>;
796 qcom,dll-config = <0x0007642c>;
797 qcom,ddr-config = <0x80040868>;
819 reg = <0x0 0x04a00000 0x0 0x60000>;
831 dma-channel-mask = <0x1f>;
832 iommus = <&apps_smmu 0xf6 0x0>;
839 reg = <0x0 0x04ac0000 0x0 0x2000>;
843 iommus = <&apps_smmu 0xe3 0x0>;
851 reg = <0x0 0x04a80000 0x0 0x4000>;
855 pinctrl-0 = <&qup_i2c0_default>;
857 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
858 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
861 #size-cells = <0>;
867 reg = <0x0 0x04a80000 0x0 0x4000>;
871 pinctrl-0 = <&qup_spi0_default>;
873 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
874 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
877 #size-cells = <0>;
883 reg = <0x0 0x04a80000 0x0 0x4000>;
887 pinctrl-0 = <&qup_uart0_default>;
894 reg = <0x0 0x04a84000 0x0 0x4000>;
898 pinctrl-0 = <&qup_i2c1_default>;
900 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
904 #size-cells = <0>;
910 reg = <0x0 0x04a84000 0x0 0x4000>;
914 pinctrl-0 = <&qup_spi1_default>;
916 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
920 #size-cells = <0>;
926 reg = <0x0 0x04a88000 0x0 0x4000>;
930 pinctrl-0 = <&qup_i2c2_default>;
932 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
936 #size-cells = <0>;
942 reg = <0x0 0x04a88000 0x0 0x4000>;
946 pinctrl-0 = <&qup_spi2_default>;
948 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
952 #size-cells = <0>;
958 reg = <0x0 0x04a8c000 0x0 0x4000>;
962 pinctrl-0 = <&qup_i2c3_default>;
964 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
968 #size-cells = <0>;
974 reg = <0x0 0x04a8c000 0x0 0x4000>;
978 pinctrl-0 = <&qup_spi3_default>;
980 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
984 #size-cells = <0>;
990 reg = <0x0 0x04a90000 0x0 0x4000>;
994 pinctrl-0 = <&qup_i2c4_default>;
996 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1000 #size-cells = <0>;
1006 reg = <0x0 0x04a90000 0x0 0x4000>;
1011 pinctrl-0 = <&qup_spi4_default>;
1012 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1016 #size-cells = <0>;
1022 reg = <0x0 0x04a90000 0x0 0x4000>;
1026 pinctrl-0 = <&qup_uart4_default>;
1033 reg = <0x0 0x04a94000 0x0 0x4000>;
1037 pinctrl-0 = <&qup_i2c5_default>;
1039 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1043 #size-cells = <0>;
1049 reg = <0x0 0x04a94000 0x0 0x4000>;
1053 pinctrl-0 = <&qup_spi5_default>;
1055 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1059 #size-cells = <0>;
1066 reg = <0x0 0x04ef8800 0x0 0x400>;
1100 reg = <0x0 0x04e00000 0x0 0xcd00>;
1104 iommus = <&apps_smmu 0x120 0x0>;
1108 snps,hird-threshold = /bits/ 8 <0x10>;
1117 reg = <0x0 0x06080000 0x0 0x100>;
1120 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1139 qcom,smem-states = <&modem_smp2p_out 0>;
1154 reg = <0x0 0x0ab00000 0x0 0x100>;
1157 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1175 qcom,smem-states = <&adsp_smp2p_out 0>;
1190 reg = <0x0 0x0c600000 0x0 0x80000>;
1263 reg = <0x0 0x0c800000 0x0 0x800000>;
1278 iommus = <&apps_smmu 0x1a0 0x1>;
1285 reg = <0x0 0x0f017000 0x0 0x1000>;
1293 reg = <0x0 0x0f111000 0x0 0x1000>;
1299 reg = <0x0 0x0f120000 0x0 0x1000>;
1302 ranges = <0 0x0 0x0f121000 0x8000>;
1304 frame@0 {
1305 reg = <0x0 0x1000>,
1306 <0x1000 0x1000>;
1309 frame-number = <0>;
1313 reg = <0x2000 0x1000>;
1320 reg = <0x3000 0x1000>;
1327 reg = <0x4000 0x1000>;
1334 reg = <0x5000 0x1000>;
1341 reg = <0x6000 0x1000>;
1348 reg = <0x7000 0x1000>;
1357 reg = <0x0 0x0f200000 0x0 0x10000>,
1358 <0x0 0x0f300000 0x0 0x100000>;
1364 redistributor-stride = <0x0 0x20000>;
1369 reg = <0x0 0x0f521000 0x0 0x1000>;
1372 interrupt-names = "dcvsh-irq-0";
1383 polling-delay-passive = <0>;
1384 polling-delay = <0>;
1386 thermal-sensors = <&tsens0 0>;
1410 polling-delay-passive = <0>;
1411 polling-delay = <0>;
1437 polling-delay-passive = <0>;
1438 polling-delay = <0>;
1464 polling-delay-passive = <0>;
1465 polling-delay = <0>;
1491 polling-delay-passive = <0>;
1492 polling-delay = <0>;
1518 polling-delay-passive = <0>;
1519 polling-delay = <0>;
1545 polling-delay-passive = <0>;
1546 polling-delay = <0>;
1572 polling-delay-passive = <0>;
1573 polling-delay = <0>;
1599 polling-delay-passive = <0>;
1600 polling-delay = <0>;
1626 polling-delay-passive = <0>;
1627 polling-delay = <0>;
1658 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;