Lines Matching full:mmcc
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
2732 mmcc: clock-controller@c8c0000 { label
2733 compatible = "qcom,mmcc-msm8998";
2770 clocks = <&mmcc MDSS_AHB_CLK>,
2771 <&mmcc MDSS_AXI_CLK>,
2772 <&mmcc MDSS_MDP_CLK>;
2777 power-domains = <&mmcc MDSS_GDSC>;
2800 clocks = <&mmcc MDSS_AHB_CLK>,
2801 <&mmcc MDSS_AXI_CLK>,
2802 <&mmcc MNOC_AHB_CLK>,
2803 <&mmcc MDSS_MDP_CLK>,
2804 <&mmcc MDSS_VSYNC_CLK>;
2811 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2871 clocks = <&mmcc MDSS_BYTE0_CLK>,
2872 <&mmcc MDSS_BYTE0_INTF_CLK>,
2873 <&mmcc MDSS_PCLK0_CLK>,
2874 <&mmcc MDSS_ESC0_CLK>,
2875 <&mmcc MDSS_AHB_CLK>,
2876 <&mmcc MDSS_AXI_CLK>;
2883 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2884 <&mmcc PCLK0_CLK_SRC>;
2929 clocks = <&mmcc MDSS_AHB_CLK>,
2947 clocks = <&mmcc MDSS_BYTE1_CLK>,
2948 <&mmcc MDSS_BYTE1_INTF_CLK>,
2949 <&mmcc MDSS_PCLK1_CLK>,
2950 <&mmcc MDSS_ESC1_CLK>,
2951 <&mmcc MDSS_AHB_CLK>,
2952 <&mmcc MDSS_AXI_CLK>;
2959 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2960 <&mmcc PCLK1_CLK_SRC>;
3005 clocks = <&mmcc MDSS_AHB_CLK>,
3022 clocks = <&mmcc MNOC_AHB_CLK>,
3023 <&mmcc BIMC_SMMU_AHB_CLK>,
3024 <&mmcc BIMC_SMMU_AXI_CLK>;
3052 power-domains = <&mmcc BIMC_SMMU_GDSC>;