Lines Matching +full:0 +full:x0c9b8000
15 qcom,msm-id = <292 0x0>;
25 reg = <0x0 0x80000000 0x0 0x0>;
34 reg = <0x0 0x85800000 0x0 0x600000>;
39 reg = <0x0 0x85e00000 0x0 0x100000>;
44 reg = <0x0 0x86000000 0x0 0x200000>;
49 reg = <0x0 0x86200000 0x0 0x2d00000>;
55 reg = <0x0 0x88f00000 0x0 0x200000>;
63 reg = <0x0 0x8ab00000 0x0 0x700000>;
68 reg = <0x0 0x8b200000 0x0 0x1a00000>;
73 reg = <0x0 0x8cc00000 0x0 0x7000000>;
78 reg = <0x0 0x93c00000 0x0 0x500000>;
83 reg = <0x0 0x94100000 0x0 0x200000>;
88 reg = <0x0 0x94300000 0x0 0xf00000>;
93 reg = <0x0 0x95200000 0x0 0x10000>;
98 reg = <0x0 0x95210000 0x0 0x5000>;
103 reg = <0x0 0x95600000 0x0 0x100000>;
108 reg = <0x0 0x95700000 0x0 0x100000>;
113 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
114 size = <0x0 0x4000>;
122 #clock-cells = <0>;
129 #clock-cells = <0>;
136 #size-cells = <0>;
138 CPU0: cpu@0 {
141 reg = <0x0 0x0>;
156 reg = <0x0 0x1>;
166 reg = <0x0 0x2>;
176 reg = <0x0 0x3>;
186 reg = <0x0 0x100>;
201 reg = <0x0 0x101>;
211 reg = <0x0 0x102>;
221 reg = <0x0 0x103>;
269 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
273 arm,psci-suspend-param = <0x00000002>;
279 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
283 arm,psci-suspend-param = <0x40000003>;
290 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
294 arm,psci-suspend-param = <0x00000002>;
304 arm,psci-suspend-param = <0x40000003>;
351 mboxes = <&apcs_glb 0>;
431 qcom,local-pid = <0>;
452 qcom,local-pid = <0>;
472 qcom,local-pid = <0>;
827 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
830 soc: soc@0 {
833 ranges = <0 0 0 0xffffffff>;
841 reg = <0x00100000 0xb0000>;
864 reg = <0x00778000 0x7000>;
869 reg = <0x00784000 0x621c>;
874 reg = <0x23a 0x1>;
875 bits = <0 4>;
881 reg = <0x010ab000 0x1000>, /* TM */
882 <0x010aa000 0x1000>; /* SROT */
892 reg = <0x010ae000 0x1000>, /* TM */
893 <0x010ad000 0x1000>; /* SROT */
903 reg = <0x01680000 0x10000>;
906 #global-interrupts = <0>;
918 reg = <0x016c0000 0x40000>;
921 #global-interrupts = <0>;
937 reg = <0x01c00000 0x2000>,
938 <0x1b000000 0xf1d>,
939 <0x1b000f20 0xa8>,
940 <0x1b100000 0x100000>;
943 linux,pci-domain = <0>;
944 bus-range = <0x00 0xff>;
952 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
953 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
958 interrupt-map-mask = <0 0 0 0x7>;
959 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
960 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
961 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
962 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
972 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
978 reg = <0x01c06000 0x18c>;
996 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
997 #phy-cells = <0>;
1002 #clock-cells = <0>;
1008 reg = <0x01da4000 0x2500>;
1037 <0 0>,
1038 <0 0>,
1040 <0 0>,
1041 <0 0>,
1042 <0 0>,
1043 <0 0>;
1051 reg = <0x01da7000 0x18c>;
1065 resets = <&ufshc 0>;
1068 reg = <0x01da7400 0x128>,
1069 <0x01da7600 0x1fc>,
1070 <0x01da7c00 0x1dc>,
1071 <0x01da7800 0x128>,
1072 <0x01da7a00 0x1fc>;
1073 #phy-cells = <0>;
1079 reg = <0x01f40000 0x20000>;
1085 reg = <0x01f60000 0x20000>;
1090 reg = <0x03400000 0xc00000>;
1092 gpio-ranges = <&tlmm 0 0 150>;
1439 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1444 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1464 qcom,smem-states = <&modem_smp2p_out 0>;
1470 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1500 reg = <0x05000000 0x40000>;
1517 iommus = <&adreno_smmu 0>;
1527 opp-supported-hw = <0xff>;
1533 opp-supported-hw = <0xff>;
1539 opp-supported-hw = <0xff>;
1545 opp-supported-hw = <0xff>;
1551 opp-supported-hw = <0xff>;
1557 opp-supported-hw = <0xff>;
1563 opp-supported-hw = <0xff>;
1570 reg = <0x05040000 0x10000>;
1576 #global-interrupts = <0>;
1598 reg = <0x05065000 0x9000>;
1608 reg = <0x05800000 0x4040>;
1611 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1626 qcom,smem-states = <&slpi_smp2p_out 0>;
1644 reg = <0x06002000 0x1000>,
1645 <0x16280000 0x180000>;
1663 reg = <0x06041000 0x1000>;
1680 #size-cells = <0>;
1693 reg = <0x06042000 0x1000>;
1710 #size-cells = <0>;
1724 reg = <0x06045000 0x1000>;
1741 #size-cells = <0>;
1743 port@0 {
1744 reg = <0>;
1763 reg = <0x06046000 0x1000>;
1788 reg = <0x06047000 0x1000>;
1815 reg = <0x06048000 0x1000>;
1834 reg = <0x07840000 0x1000>;
1854 reg = <0x07940000 0x1000>;
1874 reg = <0x07a40000 0x1000>;
1894 reg = <0x07b40000 0x1000>;
1914 reg = <0x07b60000 0x1000>;
1931 #size-cells = <0>;
1933 port@0 {
1934 reg = <0>;
2001 reg = <0x07b70000 0x1000>;
2028 reg = <0x07c40000 0x1000>;
2047 reg = <0x07d40000 0x1000>;
2066 reg = <0x07e40000 0x1000>;
2085 reg = <0x07f40000 0x1000>;
2104 reg = <0x00290000 0x10000>;
2109 reg = <0x0800f000 0x1000>,
2110 <0x08400000 0x1000000>,
2111 <0x09400000 0x1000000>,
2112 <0x0a400000 0x220000>,
2113 <0x0800a000 0x3000>;
2117 qcom,ee = <0>;
2118 qcom,channel = <0>;
2120 #size-cells = <0>;
2127 reg = <0x0a8f8800 0x400>;
2158 reg = <0x0a800000 0xcd00>;
2166 snps,hird-threshold = /bits/ 8 <0x10>;
2172 reg = <0x0c010000 0x1000>;
2183 #clock-cells = <0>;
2184 #phy-cells = <0>;
2196 reg = <0x0c012000 0x2a8>;
2198 #phy-cells = <0>;
2211 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2228 reg = <0x0c144000 0x25000>;
2233 qcom,ee = <0>;
2241 reg = <0x0c171000 0x1000>;
2249 pinctrl-0 = <&blsp1_uart3_on>;
2255 reg = <0x0c175000 0x600>;
2264 pinctrl-0 = <&blsp1_i2c1_default>;
2270 #size-cells = <0>;
2275 reg = <0x0c176000 0x600>;
2284 pinctrl-0 = <&blsp1_i2c2_default>;
2290 #size-cells = <0>;
2295 reg = <0x0c177000 0x600>;
2304 pinctrl-0 = <&blsp1_i2c3_default>;
2310 #size-cells = <0>;
2315 reg = <0x0c178000 0x600>;
2324 pinctrl-0 = <&blsp1_i2c4_default>;
2330 #size-cells = <0>;
2335 reg = <0x0c179000 0x600>;
2344 pinctrl-0 = <&blsp1_i2c5_default>;
2350 #size-cells = <0>;
2355 reg = <0x0c17a000 0x600>;
2364 pinctrl-0 = <&blsp1_i2c6_default>;
2370 #size-cells = <0>;
2375 reg = <0x0c175000 0x600>;
2384 pinctrl-0 = <&blsp1_spi1_default>;
2388 #size-cells = <0>;
2393 reg = <0x0c176000 0x600>;
2402 pinctrl-0 = <&blsp1_spi2_default>;
2406 #size-cells = <0>;
2411 reg = <0x0c177000 0x600>;
2420 pinctrl-0 = <&blsp1_spi3_default>;
2424 #size-cells = <0>;
2429 reg = <0x0c178000 0x600>;
2438 pinctrl-0 = <&blsp1_spi4_default>;
2442 #size-cells = <0>;
2447 reg = <0x0c179000 0x600>;
2456 pinctrl-0 = <&blsp1_spi5_default>;
2460 #size-cells = <0>;
2465 reg = <0x0c17a000 0x600>;
2474 pinctrl-0 = <&blsp1_spi6_default>;
2478 #size-cells = <0>;
2483 reg = <0x0c184000 0x25000>;
2488 qcom,ee = <0>;
2496 reg = <0x0c1b0000 0x1000>;
2506 reg = <0x0c1b5000 0x600>;
2515 pinctrl-0 = <&blsp2_i2c1_default>;
2521 #size-cells = <0>;
2526 reg = <0x0c1b6000 0x600>;
2535 pinctrl-0 = <&blsp2_i2c2_default>;
2541 #size-cells = <0>;
2546 reg = <0x0c1b7000 0x600>;
2555 pinctrl-0 = <&blsp2_i2c3_default>;
2561 #size-cells = <0>;
2566 reg = <0x0c1b8000 0x600>;
2575 pinctrl-0 = <&blsp2_i2c4_default>;
2581 #size-cells = <0>;
2586 reg = <0x0c1b9000 0x600>;
2595 pinctrl-0 = <&blsp2_i2c5_default>;
2601 #size-cells = <0>;
2606 reg = <0x0c1ba000 0x600>;
2615 pinctrl-0 = <&blsp2_i2c6_default>;
2621 #size-cells = <0>;
2626 reg = <0x0c1b5000 0x600>;
2635 pinctrl-0 = <&blsp2_spi1_default>;
2639 #size-cells = <0>;
2644 reg = <0x0c1b6000 0x600>;
2653 pinctrl-0 = <&blsp2_spi2_default>;
2657 #size-cells = <0>;
2662 reg = <0x0c1b7000 0x600>;
2671 pinctrl-0 = <&blsp2_spi3_default>;
2675 #size-cells = <0>;
2680 reg = <0x0c1b8000 0x600>;
2689 pinctrl-0 = <&blsp2_spi4_default>;
2693 #size-cells = <0>;
2698 reg = <0x0c1b9000 0x600>;
2707 pinctrl-0 = <&blsp2_spi5_default>;
2711 #size-cells = <0>;
2716 reg = <0x0c1ba000 0x600>;
2725 pinctrl-0 = <&blsp2_spi6_default>;
2729 #size-cells = <0>;
2737 reg = <0xc8c0000 0x40000>;
2752 <&mdss_dsi0_phy 0>,
2754 <&mdss_dsi1_phy 0>,
2755 <0>,
2756 <0>,
2757 <0>,
2763 reg = <0x0c900000 0x1000>;
2778 iommus = <&mmss_smmu 0>;
2788 reg = <0x0c901000 0x8f000>,
2789 <0x0c9a8e00 0xf0>,
2790 <0x0c9b0000 0x2008>,
2791 <0x0c9b8000 0x1040>;
2798 interrupts = <0>;
2843 #size-cells = <0>;
2845 port@0 {
2846 reg = <0>;
2865 reg = <0x0c994000 0x400>;
2885 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2895 #size-cells = <0>;
2901 #size-cells = <0>;
2903 port@0 {
2904 reg = <0>;
2922 reg = <0x0c994400 0x200>,
2923 <0x0c994600 0x280>,
2924 <0x0c994a00 0x1e0>;
2934 #phy-cells = <0>;
2941 reg = <0x0c996000 0x400>;
2961 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2971 #size-cells = <0>;
2977 #size-cells = <0>;
2979 port@0 {
2980 reg = <0>;
2998 reg = <0x0c996400 0x200>,
2999 <0x0c996600 0x280>,
3000 <0x0c996a00 0x10e>;
3011 #phy-cells = <0>;
3019 reg = <0x0cd00000 0x40000>;
3029 #global-interrupts = <0>;
3057 reg = <0x17300000 0x4040>;
3060 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3072 qcom,smem-states = <&adsp_smp2p_out 0>;
3091 reg = <0x17911000 0x1000>;
3101 reg = <0x17920000 0x1000>;
3104 frame-number = <0>;
3107 reg = <0x17921000 0x1000>,
3108 <0x17922000 0x1000>;
3114 reg = <0x17923000 0x1000>;
3121 reg = <0x17924000 0x1000>;
3128 reg = <0x17925000 0x1000>;
3135 reg = <0x17926000 0x1000>;
3142 reg = <0x17927000 0x1000>;
3149 reg = <0x17928000 0x1000>;
3156 reg = <0x17a00000 0x10000>, /* GICD */
3157 <0x17b00000 0x100000>; /* GICR * 8 */
3164 redistributor-stride = <0x0 0x20000>;
3171 reg = <0x18800000 0x800000>;
3189 iommus = <&anoc2_smmu 0x1900>,
3190 <&anoc2_smmu 0x1901>;