Lines Matching +full:slim +full:- +full:ngd
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm8996.h>
11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,apr.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&intc>;
20 #address-cells = <2>;
21 #size-cells = <2>;
26 xo_board: xo-board {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <19200000>;
30 clock-output-names = "xo_board";
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <32764>;
37 clock-output-names = "sleep_clk";
42 #address-cells = <2>;
43 #size-cells = <0>;
49 enable-method = "psci";
50 cpu-idle-states = <&CPU_SLEEP_0>;
51 capacity-dmips-mhz = <1024>;
54 operating-points-v2 = <&cluster0_opp>;
55 #cooling-cells = <2>;
56 next-level-cache = <&L2_0>;
57 L2_0: l2-cache {
59 cache-level = <2>;
60 cache-unified;
68 enable-method = "psci";
69 cpu-idle-states = <&CPU_SLEEP_0>;
70 capacity-dmips-mhz = <1024>;
73 operating-points-v2 = <&cluster0_opp>;
74 #cooling-cells = <2>;
75 next-level-cache = <&L2_0>;
82 enable-method = "psci";
83 cpu-idle-states = <&CPU_SLEEP_0>;
84 capacity-dmips-mhz = <1024>;
87 operating-points-v2 = <&cluster1_opp>;
88 #cooling-cells = <2>;
89 next-level-cache = <&L2_1>;
90 L2_1: l2-cache {
92 cache-level = <2>;
93 cache-unified;
101 enable-method = "psci";
102 cpu-idle-states = <&CPU_SLEEP_0>;
103 capacity-dmips-mhz = <1024>;
106 operating-points-v2 = <&cluster1_opp>;
107 #cooling-cells = <2>;
108 next-level-cache = <&L2_1>;
111 cpu-map {
133 idle-states {
134 entry-method = "psci";
136 CPU_SLEEP_0: cpu-sleep-0 {
137 compatible = "arm,idle-state";
138 idle-state-name = "standalone-power-collapse";
139 arm,psci-suspend-param = <0x00000004>;
140 entry-latency-us = <130>;
141 exit-latency-us = <80>;
142 min-residency-us = <300>;
147 cluster0_opp: opp-table-cluster0 {
148 compatible = "operating-points-v2-kryo-cpu";
149 nvmem-cells = <&speedbin_efuse>;
150 opp-shared;
153 opp-307200000 {
154 opp-hz = /bits/ 64 <307200000>;
155 opp-supported-hw = <0xf>;
156 clock-latency-ns = <200000>;
157 opp-peak-kBps = <307200>;
159 opp-422400000 {
160 opp-hz = /bits/ 64 <422400000>;
161 opp-supported-hw = <0xf>;
162 clock-latency-ns = <200000>;
163 opp-peak-kBps = <307200>;
165 opp-480000000 {
166 opp-hz = /bits/ 64 <480000000>;
167 opp-supported-hw = <0xf>;
168 clock-latency-ns = <200000>;
169 opp-peak-kBps = <307200>;
171 opp-556800000 {
172 opp-hz = /bits/ 64 <556800000>;
173 opp-supported-hw = <0xf>;
174 clock-latency-ns = <200000>;
175 opp-peak-kBps = <307200>;
177 opp-652800000 {
178 opp-hz = /bits/ 64 <652800000>;
179 opp-supported-hw = <0xf>;
180 clock-latency-ns = <200000>;
181 opp-peak-kBps = <384000>;
183 opp-729600000 {
184 opp-hz = /bits/ 64 <729600000>;
185 opp-supported-hw = <0xf>;
186 clock-latency-ns = <200000>;
187 opp-peak-kBps = <460800>;
189 opp-844800000 {
190 opp-hz = /bits/ 64 <844800000>;
191 opp-supported-hw = <0xf>;
192 clock-latency-ns = <200000>;
193 opp-peak-kBps = <537600>;
195 opp-960000000 {
196 opp-hz = /bits/ 64 <960000000>;
197 opp-supported-hw = <0xf>;
198 clock-latency-ns = <200000>;
199 opp-peak-kBps = <672000>;
201 opp-1036800000 {
202 opp-hz = /bits/ 64 <1036800000>;
203 opp-supported-hw = <0xf>;
204 clock-latency-ns = <200000>;
205 opp-peak-kBps = <672000>;
207 opp-1113600000 {
208 opp-hz = /bits/ 64 <1113600000>;
209 opp-supported-hw = <0xf>;
210 clock-latency-ns = <200000>;
211 opp-peak-kBps = <825600>;
213 opp-1190400000 {
214 opp-hz = /bits/ 64 <1190400000>;
215 opp-supported-hw = <0xf>;
216 clock-latency-ns = <200000>;
217 opp-peak-kBps = <825600>;
219 opp-1228800000 {
220 opp-hz = /bits/ 64 <1228800000>;
221 opp-supported-hw = <0xf>;
222 clock-latency-ns = <200000>;
223 opp-peak-kBps = <902400>;
225 opp-1324800000 {
226 opp-hz = /bits/ 64 <1324800000>;
227 opp-supported-hw = <0xd>;
228 clock-latency-ns = <200000>;
229 opp-peak-kBps = <1056000>;
231 opp-1363200000 {
232 opp-hz = /bits/ 64 <1363200000>;
233 opp-supported-hw = <0x2>;
234 clock-latency-ns = <200000>;
235 opp-peak-kBps = <1132800>;
237 opp-1401600000 {
238 opp-hz = /bits/ 64 <1401600000>;
239 opp-supported-hw = <0xd>;
240 clock-latency-ns = <200000>;
241 opp-peak-kBps = <1132800>;
243 opp-1478400000 {
244 opp-hz = /bits/ 64 <1478400000>;
245 opp-supported-hw = <0x9>;
246 clock-latency-ns = <200000>;
247 opp-peak-kBps = <1190400>;
249 opp-1497600000 {
250 opp-hz = /bits/ 64 <1497600000>;
251 opp-supported-hw = <0x04>;
252 clock-latency-ns = <200000>;
253 opp-peak-kBps = <1305600>;
255 opp-1593600000 {
256 opp-hz = /bits/ 64 <1593600000>;
257 opp-supported-hw = <0x9>;
258 clock-latency-ns = <200000>;
259 opp-peak-kBps = <1382400>;
263 cluster1_opp: opp-table-cluster1 {
264 compatible = "operating-points-v2-kryo-cpu";
265 nvmem-cells = <&speedbin_efuse>;
266 opp-shared;
269 opp-307200000 {
270 opp-hz = /bits/ 64 <307200000>;
271 opp-supported-hw = <0xf>;
272 clock-latency-ns = <200000>;
273 opp-peak-kBps = <307200>;
275 opp-403200000 {
276 opp-hz = /bits/ 64 <403200000>;
277 opp-supported-hw = <0xf>;
278 clock-latency-ns = <200000>;
279 opp-peak-kBps = <307200>;
281 opp-480000000 {
282 opp-hz = /bits/ 64 <480000000>;
283 opp-supported-hw = <0xf>;
284 clock-latency-ns = <200000>;
285 opp-peak-kBps = <307200>;
287 opp-556800000 {
288 opp-hz = /bits/ 64 <556800000>;
289 opp-supported-hw = <0xf>;
290 clock-latency-ns = <200000>;
291 opp-peak-kBps = <307200>;
293 opp-652800000 {
294 opp-hz = /bits/ 64 <652800000>;
295 opp-supported-hw = <0xf>;
296 clock-latency-ns = <200000>;
297 opp-peak-kBps = <307200>;
299 opp-729600000 {
300 opp-hz = /bits/ 64 <729600000>;
301 opp-supported-hw = <0xf>;
302 clock-latency-ns = <200000>;
303 opp-peak-kBps = <307200>;
305 opp-806400000 {
306 opp-hz = /bits/ 64 <806400000>;
307 opp-supported-hw = <0xf>;
308 clock-latency-ns = <200000>;
309 opp-peak-kBps = <384000>;
311 opp-883200000 {
312 opp-hz = /bits/ 64 <883200000>;
313 opp-supported-hw = <0xf>;
314 clock-latency-ns = <200000>;
315 opp-peak-kBps = <460800>;
317 opp-940800000 {
318 opp-hz = /bits/ 64 <940800000>;
319 opp-supported-hw = <0xf>;
320 clock-latency-ns = <200000>;
321 opp-peak-kBps = <537600>;
323 opp-1036800000 {
324 opp-hz = /bits/ 64 <1036800000>;
325 opp-supported-hw = <0xf>;
326 clock-latency-ns = <200000>;
327 opp-peak-kBps = <595200>;
329 opp-1113600000 {
330 opp-hz = /bits/ 64 <1113600000>;
331 opp-supported-hw = <0xf>;
332 clock-latency-ns = <200000>;
333 opp-peak-kBps = <672000>;
335 opp-1190400000 {
336 opp-hz = /bits/ 64 <1190400000>;
337 opp-supported-hw = <0xf>;
338 clock-latency-ns = <200000>;
339 opp-peak-kBps = <672000>;
341 opp-1248000000 {
342 opp-hz = /bits/ 64 <1248000000>;
343 opp-supported-hw = <0xf>;
344 clock-latency-ns = <200000>;
345 opp-peak-kBps = <748800>;
347 opp-1324800000 {
348 opp-hz = /bits/ 64 <1324800000>;
349 opp-supported-hw = <0xf>;
350 clock-latency-ns = <200000>;
351 opp-peak-kBps = <825600>;
353 opp-1401600000 {
354 opp-hz = /bits/ 64 <1401600000>;
355 opp-supported-hw = <0xf>;
356 clock-latency-ns = <200000>;
357 opp-peak-kBps = <902400>;
359 opp-1478400000 {
360 opp-hz = /bits/ 64 <1478400000>;
361 opp-supported-hw = <0xf>;
362 clock-latency-ns = <200000>;
363 opp-peak-kBps = <979200>;
365 opp-1555200000 {
366 opp-hz = /bits/ 64 <1555200000>;
367 opp-supported-hw = <0xf>;
368 clock-latency-ns = <200000>;
369 opp-peak-kBps = <1056000>;
371 opp-1632000000 {
372 opp-hz = /bits/ 64 <1632000000>;
373 opp-supported-hw = <0xf>;
374 clock-latency-ns = <200000>;
375 opp-peak-kBps = <1190400>;
377 opp-1708800000 {
378 opp-hz = /bits/ 64 <1708800000>;
379 opp-supported-hw = <0xf>;
380 clock-latency-ns = <200000>;
381 opp-peak-kBps = <1228800>;
383 opp-1785600000 {
384 opp-hz = /bits/ 64 <1785600000>;
385 opp-supported-hw = <0xf>;
386 clock-latency-ns = <200000>;
387 opp-peak-kBps = <1305600>;
389 opp-1804800000 {
390 opp-hz = /bits/ 64 <1804800000>;
391 opp-supported-hw = <0xe>;
392 clock-latency-ns = <200000>;
393 opp-peak-kBps = <1305600>;
395 opp-1824000000 {
396 opp-hz = /bits/ 64 <1824000000>;
397 opp-supported-hw = <0x1>;
398 clock-latency-ns = <200000>;
399 opp-peak-kBps = <1382400>;
401 opp-1900800000 {
402 opp-hz = /bits/ 64 <1900800000>;
403 opp-supported-hw = <0x4>;
404 clock-latency-ns = <200000>;
405 opp-peak-kBps = <1305600>;
407 opp-1920000000 {
408 opp-hz = /bits/ 64 <1920000000>;
409 opp-supported-hw = <0x1>;
410 clock-latency-ns = <200000>;
411 opp-peak-kBps = <1459200>;
413 opp-1996800000 {
414 opp-hz = /bits/ 64 <1996800000>;
415 opp-supported-hw = <0x1>;
416 clock-latency-ns = <200000>;
417 opp-peak-kBps = <1593600>;
419 opp-2073600000 {
420 opp-hz = /bits/ 64 <2073600000>;
421 opp-supported-hw = <0x1>;
422 clock-latency-ns = <200000>;
423 opp-peak-kBps = <1593600>;
425 opp-2150400000 {
426 opp-hz = /bits/ 64 <2150400000>;
427 opp-supported-hw = <0x1>;
428 clock-latency-ns = <200000>;
429 opp-peak-kBps = <1593600>;
435 compatible = "qcom,scm-msm8996", "qcom,scm";
436 qcom,dload-mode = <&tcsr_2 0x13000>;
447 compatible = "qcom,coresight-remote-etm";
449 out-ports {
452 remote-endpoint =
460 compatible = "arm,psci-1.0";
465 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
467 glink-edge {
468 compatible = "qcom,glink-rpm";
470 qcom,rpm-msg-ram = <&rpm_msg_ram>;
473 rpm_requests: rpm-requests {
474 compatible = "qcom,rpm-msm8996";
475 qcom,glink-channels = "rpm_requests";
477 rpmcc: clock-controller {
478 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
479 #clock-cells = <1>;
481 clock-names = "xo";
484 rpmpd: power-controller {
485 compatible = "qcom,msm8996-rpmpd";
486 #power-domain-cells = <1>;
487 operating-points-v2 = <&rpmpd_opp_table>;
489 rpmpd_opp_table: opp-table {
490 compatible = "operating-points-v2";
493 opp-level = <1>;
497 opp-level = <2>;
501 opp-level = <3>;
505 opp-level = <4>;
509 opp-level = <5>;
513 opp-level = <6>;
521 reserved-memory {
522 #address-cells = <2>;
523 #size-cells = <2>;
528 no-map;
533 no-map;
536 smem_mem: smem-mem@86000000 {
538 no-map;
543 no-map;
547 compatible = "qcom,rmtfs-mem";
550 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
551 no-map;
553 qcom,client-id = <1>;
559 no-map;
564 no-map;
569 no-map;
573 compatible = "shared-dma-pool";
575 no-map;
580 no-map;
585 no-map;
588 mdata_mem: mpss-metadata {
589 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
591 no-map;
597 memory-region = <&smem_mem>;
601 smp2p-adsp {
609 qcom,local-pid = <0>;
610 qcom,remote-pid = <2>;
612 adsp_smp2p_out: master-kernel {
613 qcom,entry-name = "master-kernel";
614 #qcom,smem-state-cells = <1>;
617 adsp_smp2p_in: slave-kernel {
618 qcom,entry-name = "slave-kernel";
620 interrupt-controller;
621 #interrupt-cells = <2>;
625 smp2p-mpss {
633 qcom,local-pid = <0>;
634 qcom,remote-pid = <1>;
636 mpss_smp2p_out: master-kernel {
637 qcom,entry-name = "master-kernel";
638 #qcom,smem-state-cells = <1>;
641 mpss_smp2p_in: slave-kernel {
642 qcom,entry-name = "slave-kernel";
644 interrupt-controller;
645 #interrupt-cells = <2>;
649 smp2p-slpi {
657 qcom,local-pid = <0>;
658 qcom,remote-pid = <3>;
660 slpi_smp2p_out: master-kernel {
661 qcom,entry-name = "master-kernel";
662 #qcom,smem-state-cells = <1>;
665 slpi_smp2p_in: slave-kernel {
666 qcom,entry-name = "slave-kernel";
668 interrupt-controller;
669 #interrupt-cells = <2>;
674 #address-cells = <1>;
675 #size-cells = <1>;
677 compatible = "simple-bus";
679 pcie_phy: phy-wrapper@34000 {
680 compatible = "qcom,msm8996-qmp-pcie-phy";
682 #address-cells = <1>;
683 #size-cells = <1>;
689 clock-names = "aux", "cfg_ahb", "ref";
694 reset-names = "phy", "common", "cfg";
704 clock-names = "pipe0";
706 reset-names = "lane0";
708 #clock-cells = <0>;
709 clock-output-names = "pcie_0_pipe_clk_src";
711 #phy-cells = <0>;
720 clock-names = "pipe1";
722 reset-names = "lane1";
724 #clock-cells = <0>;
725 clock-output-names = "pcie_1_pipe_clk_src";
727 #phy-cells = <0>;
736 clock-names = "pipe2";
738 reset-names = "lane2";
740 #clock-cells = <0>;
741 clock-output-names = "pcie_2_pipe_clk_src";
743 #phy-cells = <0>;
748 compatible = "qcom,rpm-msg-ram";
753 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
755 #address-cells = <1>;
756 #size-cells = <1>;
775 compatible = "qcom,prng-ee";
778 clock-names = "core";
781 gcc: clock-controller@300000 {
782 compatible = "qcom,gcc-msm8996";
783 #clock-cells = <1>;
784 #reset-cells = <1>;
785 #power-domain-cells = <1>;
798 clock-names = "cxo",
811 compatible = "qcom,msm8996-bimc";
813 #interconnect-cells = <1>;
814 clock-names = "bus", "bus_a";
819 tsens0: thermal-sensor@4a9000 {
820 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
826 interrupt-names = "uplow", "critical";
827 #thermal-sensor-cells = <1>;
830 tsens1: thermal-sensor@4ad000 {
831 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
837 interrupt-names = "uplow", "critical";
838 #thermal-sensor-cells = <1>;
841 cryptobam: dma-controller@644000 {
842 compatible = "qcom,bam-v1.7.0";
846 clock-names = "bam_clk";
847 #dma-cells = <1>;
849 qcom,controlled-remotely;
853 compatible = "qcom,crypto-v5.4";
858 clock-names = "iface", "bus", "core";
860 dma-names = "rx", "tx";
864 compatible = "qcom,msm8996-cnoc";
866 #interconnect-cells = <1>;
867 clock-names = "bus", "bus_a";
873 compatible = "qcom,msm8996-snoc";
875 #interconnect-cells = <1>;
876 clock-names = "bus", "bus_a";
882 compatible = "qcom,msm8996-a0noc";
884 #interconnect-cells = <1>;
885 clock-names = "aggre0_snoc_axi",
891 power-domains = <&gcc AGGRE0_NOC_GDSC>;
895 compatible = "qcom,msm8996-a1noc";
897 #interconnect-cells = <1>;
898 clock-names = "bus", "bus_a";
904 compatible = "qcom,msm8996-a2noc";
906 #interconnect-cells = <1>;
907 clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi";
915 compatible = "qcom,msm8996-mnoc";
917 #interconnect-cells = <1>;
918 clock-names = "bus", "bus_a", "iface";
925 compatible = "qcom,msm8996-pnoc";
927 #interconnect-cells = <1>;
928 clock-names = "bus", "bus_a";
934 compatible = "qcom,tcsr-mutex";
936 #hwlock-cells = <1>;
940 compatible = "qcom,tcsr-msm8996", "syscon";
945 compatible = "qcom,tcsr-msm8996", "syscon";
949 mmcc: clock-controller@8c0000 {
950 compatible = "qcom,mmcc-msm8996";
951 #clock-cells = <1>;
952 #reset-cells = <1>;
953 #power-domain-cells = <1>;
963 clock-names = "xo",
971 assigned-clocks = <&mmcc MMPLL9_PLL>,
976 assigned-clock-rates = <624000000>,
983 mdss: display-subsystem@900000 {
989 reg-names = "mdss_phys",
993 power-domains = <&mmcc MDSS_GDSC>;
996 interrupt-controller;
997 #interrupt-cells = <1>;
1001 clock-names = "iface", "core";
1003 #address-cells = <1>;
1004 #size-cells = <1>;
1009 mdp: display-controller@901000 {
1010 compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
1012 reg-names = "mdp_phys";
1014 interrupt-parent = <&mdss>;
1022 clock-names = "iface",
1030 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1032 assigned-clock-rates = <300000000>,
1038 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1047 remote-endpoint = <&mdss_hdmi_in>;
1054 remote-endpoint = <&mdss_dsi0_in>;
1061 remote-endpoint = <&mdss_dsi1_in>;
1068 compatible = "qcom,msm8996-dsi-ctrl",
1069 "qcom,mdss-dsi-ctrl";
1071 reg-names = "dsi_ctrl";
1073 interrupt-parent = <&mdss>;
1083 clock-names = "mdp_core",
1090 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1091 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1096 #address-cells = <1>;
1097 #size-cells = <0>;
1100 #address-cells = <1>;
1101 #size-cells = <0>;
1106 remote-endpoint = <&mdp5_intf1_out>;
1119 compatible = "qcom,dsi-phy-14nm";
1123 reg-names = "dsi_phy",
1127 #clock-cells = <1>;
1128 #phy-cells = <0>;
1131 clock-names = "iface", "ref";
1136 compatible = "qcom,msm8996-dsi-ctrl",
1137 "qcom,mdss-dsi-ctrl";
1139 reg-names = "dsi_ctrl";
1141 interrupt-parent = <&mdss>;
1151 clock-names = "mdp_core",
1158 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1159 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1164 #address-cells = <1>;
1165 #size-cells = <0>;
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1174 remote-endpoint = <&mdp5_intf2_out>;
1187 compatible = "qcom,dsi-phy-14nm";
1191 reg-names = "dsi_phy",
1195 #clock-cells = <1>;
1196 #phy-cells = <0>;
1199 clock-names = "iface", "ref";
1203 mdss_hdmi: hdmi-tx@9a0000 {
1204 compatible = "qcom,hdmi-tx-8996";
1208 reg-names = "core_physical",
1212 interrupt-parent = <&mdss>;
1220 clock-names =
1228 #sound-dai-cells = <1>;
1233 #address-cells = <1>;
1234 #size-cells = <0>;
1239 remote-endpoint = <&mdp5_intf3_out>;
1246 #phy-cells = <0>;
1247 compatible = "qcom,hdmi-phy-8996";
1254 reg-names = "hdmi_pll",
1264 clock-names = "iface",
1268 #clock-cells = <0>;
1275 compatible = "qcom,adreno-530.2", "qcom,adreno";
1278 reg-names = "kgsl_3d0_reg_memory";
1288 clock-names = "core",
1295 interconnect-names = "gfx-mem";
1297 power-domains = <&mmcc GPU_GX_GDSC>;
1300 nvmem-cells = <&speedbin_efuse>;
1301 nvmem-cell-names = "speed_bin";
1303 operating-points-v2 = <&gpu_opp_table>;
1307 #cooling-cells = <2>;
1309 gpu_opp_table: opp-table {
1310 compatible = "operating-points-v2";
1317 opp-624000000 {
1318 opp-hz = /bits/ 64 <624000000>;
1319 opp-supported-hw = <0x09>;
1321 opp-560000000 {
1322 opp-hz = /bits/ 64 <560000000>;
1323 opp-supported-hw = <0x0d>;
1325 opp-510000000 {
1326 opp-hz = /bits/ 64 <510000000>;
1327 opp-supported-hw = <0xff>;
1329 opp-401800000 {
1330 opp-hz = /bits/ 64 <401800000>;
1331 opp-supported-hw = <0xff>;
1333 opp-315000000 {
1334 opp-hz = /bits/ 64 <315000000>;
1335 opp-supported-hw = <0xff>;
1337 opp-214000000 {
1338 opp-hz = /bits/ 64 <214000000>;
1339 opp-supported-hw = <0xff>;
1341 opp-133000000 {
1342 opp-hz = /bits/ 64 <133000000>;
1343 opp-supported-hw = <0xff>;
1347 zap-shader {
1348 memory-region = <&gpu_mem>;
1353 compatible = "qcom,msm8996-pinctrl";
1356 gpio-controller;
1357 gpio-ranges = <&tlmm 0 0 150>;
1358 #gpio-cells = <2>;
1359 interrupt-controller;
1360 #interrupt-cells = <2>;
1362 blsp1_spi1_default: blsp1-spi1-default-state {
1363 spi-pins {
1366 drive-strength = <12>;
1367 bias-disable;
1370 cs-pins {
1373 drive-strength = <16>;
1374 bias-disable;
1375 output-high;
1379 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
1382 drive-strength = <2>;
1383 bias-pull-down;
1386 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
1389 drive-strength = <16>;
1390 bias-disable;
1393 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
1396 drive-strength = <2>;
1397 bias-disable;
1400 blsp2_i2c2_default: blsp2-i2c2-state {
1403 drive-strength = <16>;
1404 bias-disable;
1407 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1410 drive-strength = <2>;
1411 bias-disable;
1414 blsp1_i2c6_default: blsp1-i2c6-state {
1417 drive-strength = <16>;
1418 bias-disable;
1421 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1424 drive-strength = <2>;
1425 bias-pull-up;
1428 cci0_default: cci0-default-state {
1431 drive-strength = <16>;
1432 bias-disable;
1436 camera_rear_default: camera-rear-default-state {
1437 camera0_mclk: mclk0-pins {
1440 drive-strength = <16>;
1441 bias-disable;
1444 camera0_rst: rst-pins {
1447 drive-strength = <16>;
1448 bias-disable;
1451 camera0_pwdn: pwdn-pins {
1454 drive-strength = <16>;
1455 bias-disable;
1459 cci1_default: cci1-default-state {
1462 drive-strength = <16>;
1463 bias-disable;
1467 camera_board_default: camera-board-default-state {
1468 mclk1-pins {
1471 drive-strength = <16>;
1472 bias-disable;
1475 pwdn-pins {
1478 drive-strength = <16>;
1479 bias-disable;
1482 rst-pins {
1485 drive-strength = <16>;
1486 bias-disable;
1491 camera_front_default: camera-front-default-state {
1492 camera2_mclk: mclk2-pins {
1495 drive-strength = <16>;
1496 bias-disable;
1499 camera2_rst: rst-pins {
1502 drive-strength = <16>;
1503 bias-disable;
1506 pwdn-pins {
1509 drive-strength = <16>;
1510 bias-disable;
1514 pcie0_state_on: pcie0-state-on-state {
1515 perst-pins {
1518 drive-strength = <2>;
1519 bias-pull-down;
1522 clkreq-pins {
1525 drive-strength = <2>;
1526 bias-pull-up;
1529 wake-pins {
1532 drive-strength = <2>;
1533 bias-pull-up;
1537 pcie0_state_off: pcie0-state-off-state {
1538 perst-pins {
1541 drive-strength = <2>;
1542 bias-pull-down;
1545 clkreq-pins {
1548 drive-strength = <2>;
1549 bias-disable;
1552 wake-pins {
1555 drive-strength = <2>;
1556 bias-disable;
1560 blsp1_uart2_default: blsp1-uart2-default-state {
1563 drive-strength = <16>;
1564 bias-disable;
1567 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
1570 drive-strength = <2>;
1571 bias-disable;
1574 blsp1_i2c3_default: blsp1-i2c3-default-state {
1577 drive-strength = <16>;
1578 bias-disable;
1581 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1584 drive-strength = <2>;
1585 bias-disable;
1588 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
1591 drive-strength = <16>;
1592 bias-disable;
1595 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
1598 drive-strength = <2>;
1599 bias-disable;
1602 blsp2_i2c3_default: blsp2-i2c3-state-state {
1605 drive-strength = <16>;
1606 bias-disable;
1609 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1612 drive-strength = <2>;
1613 bias-disable;
1616 wcd_intr_default: wcd-intr-default-state {
1619 drive-strength = <2>;
1620 bias-pull-down;
1623 blsp2_i2c1_default: blsp2-i2c1-state {
1626 drive-strength = <16>;
1627 bias-disable;
1630 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1633 drive-strength = <2>;
1634 bias-disable;
1637 blsp2_i2c5_default: blsp2-i2c5-state {
1640 drive-strength = <2>;
1641 bias-disable;
1646 cdc_reset_active: cdc-reset-active-state {
1649 drive-strength = <16>;
1650 bias-pull-down;
1651 output-high;
1654 cdc_reset_sleep: cdc-reset-sleep-state {
1657 drive-strength = <16>;
1658 bias-disable;
1659 output-low;
1662 blsp2_spi6_default: blsp2-spi6-default-state {
1663 spi-pins {
1666 drive-strength = <12>;
1667 bias-disable;
1670 cs-pins {
1673 drive-strength = <16>;
1674 bias-disable;
1675 output-high;
1679 blsp2_spi6_sleep: blsp2-spi6-sleep-state {
1682 drive-strength = <2>;
1683 bias-pull-down;
1686 blsp2_i2c6_default: blsp2-i2c6-state {
1689 drive-strength = <16>;
1690 bias-disable;
1693 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1696 drive-strength = <2>;
1697 bias-disable;
1700 pcie1_state_on: pcie1-on-state {
1701 perst-pins {
1704 drive-strength = <2>;
1705 bias-pull-down;
1708 clkreq-pins {
1711 drive-strength = <2>;
1712 bias-pull-up;
1715 wake-pins {
1718 drive-strength = <2>;
1719 bias-pull-down;
1723 pcie1_state_off: pcie1-off-state {
1725 clkreq-pins {
1728 drive-strength = <2>;
1729 bias-disable;
1732 wake-pins {
1735 drive-strength = <2>;
1736 bias-disable;
1740 pcie2_state_on: pcie2-on-state {
1741 perst-pins {
1744 drive-strength = <2>;
1745 bias-pull-down;
1748 clkreq-pins {
1751 drive-strength = <2>;
1752 bias-pull-up;
1755 wake-pins {
1758 drive-strength = <2>;
1759 bias-pull-down;
1763 pcie2_state_off: pcie2-off-state {
1765 clkreq-pins {
1768 drive-strength = <2>;
1769 bias-disable;
1772 wake-pins {
1775 drive-strength = <2>;
1776 bias-disable;
1780 sdc1_state_on: sdc1-on-state {
1781 clk-pins {
1783 bias-disable;
1784 drive-strength = <16>;
1787 cmd-pins {
1789 bias-pull-up;
1790 drive-strength = <10>;
1793 data-pins {
1795 bias-pull-up;
1796 drive-strength = <10>;
1799 rclk-pins {
1801 bias-pull-down;
1805 sdc1_state_off: sdc1-off-state {
1806 clk-pins {
1808 bias-disable;
1809 drive-strength = <2>;
1812 cmd-pins {
1814 bias-pull-up;
1815 drive-strength = <2>;
1818 data-pins {
1820 bias-pull-up;
1821 drive-strength = <2>;
1824 rclk-pins {
1826 bias-pull-down;
1830 sdc2_state_on: sdc2-on-state {
1831 clk-pins {
1833 bias-disable;
1834 drive-strength = <16>;
1837 cmd-pins {
1839 bias-pull-up;
1840 drive-strength = <10>;
1843 data-pins {
1845 bias-pull-up;
1846 drive-strength = <10>;
1850 sdc2_state_off: sdc2-off-state {
1851 clk-pins {
1853 bias-disable;
1854 drive-strength = <2>;
1857 cmd-pins {
1859 bias-pull-up;
1860 drive-strength = <2>;
1863 data-pins {
1865 bias-pull-up;
1866 drive-strength = <2>;
1872 compatible = "qcom,rpm-stats";
1877 compatible = "qcom,spmi-pmic-arb";
1883 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1884 interrupt-names = "periph_irq";
1888 #address-cells = <2>;
1889 #size-cells = <0>;
1890 interrupt-controller;
1891 #interrupt-cells = <4>;
1895 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1896 compatible = "simple-pm-bus";
1897 #address-cells = <1>;
1898 #size-cells = <1>;
1902 compatible = "qcom,pcie-msm8996";
1904 power-domains = <&gcc PCIE0_GDSC>;
1905 bus-range = <0x00 0xff>;
1906 num-lanes = <1>;
1912 reg-names = "parf", "dbi", "elbi","config";
1915 phy-names = "pciephy";
1917 #address-cells = <3>;
1918 #size-cells = <2>;
1925 interrupt-names = "msi";
1926 #interrupt-cells = <1>;
1927 interrupt-map-mask = <0 0 0 0x7>;
1928 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1933 pinctrl-names = "default", "sleep";
1934 pinctrl-0 = <&pcie0_state_on>;
1935 pinctrl-1 = <&pcie0_state_off>;
1937 linux,pci-domain = <0>;
1945 clock-names = "pipe",
1953 compatible = "qcom,pcie-msm8996";
1954 power-domains = <&gcc PCIE1_GDSC>;
1955 bus-range = <0x00 0xff>;
1956 num-lanes = <1>;
1965 reg-names = "parf", "dbi", "elbi","config";
1968 phy-names = "pciephy";
1970 #address-cells = <3>;
1971 #size-cells = <2>;
1978 interrupt-names = "msi";
1979 #interrupt-cells = <1>;
1980 interrupt-map-mask = <0 0 0 0x7>;
1981 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1986 pinctrl-names = "default", "sleep";
1987 pinctrl-0 = <&pcie1_state_on>;
1988 pinctrl-1 = <&pcie1_state_off>;
1990 linux,pci-domain = <1>;
1998 clock-names = "pipe",
2006 compatible = "qcom,pcie-msm8996";
2007 power-domains = <&gcc PCIE2_GDSC>;
2008 bus-range = <0x00 0xff>;
2009 num-lanes = <1>;
2016 reg-names = "parf", "dbi", "elbi","config";
2019 phy-names = "pciephy";
2021 #address-cells = <3>;
2022 #size-cells = <2>;
2029 interrupt-names = "msi";
2030 #interrupt-cells = <1>;
2031 interrupt-map-mask = <0 0 0 0x7>;
2032 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2037 pinctrl-names = "default", "sleep";
2038 pinctrl-0 = <&pcie2_state_on>;
2039 pinctrl-1 = <&pcie2_state_off>;
2041 linux,pci-domain = <2>;
2048 clock-names = "pipe",
2057 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
2058 "jedec,ufs-2.0";
2063 phy-names = "ufsphy";
2065 power-domains = <&gcc UFS_GDSC>;
2067 clock-names =
2091 freq-table-hz =
2106 interconnect-names = "ufs-ddr", "cpu-ufs";
2108 lanes-per-direction = <1>;
2109 #reset-cells = <1>;
2114 compatible = "qcom,msm8996-qmp-ufs-phy";
2116 #address-cells = <1>;
2117 #size-cells = <1>;
2121 clock-names = "ref";
2124 reset-names = "ufsphy";
2131 #clock-cells = <1>;
2132 #phy-cells = <0>;
2137 compatible = "qcom,msm8996-camss";
2152 reg-names = "csiphy0",
2176 interrupt-names = "csiphy0",
2186 power-domains = <&mmcc VFE0_GDSC>,
2224 clock-names = "top_ahb",
2266 #address-cells = <1>;
2267 #size-cells = <0>;
2272 compatible = "qcom,msm8996-cci";
2273 #address-cells = <1>;
2274 #size-cells = <0>;
2277 power-domains = <&mmcc CAMSS_GDSC>;
2282 clock-names = "camss_top_ahb",
2286 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2288 assigned-clock-rates = <80000000>, <37500000>;
2289 pinctrl-names = "default";
2290 pinctrl-0 = <&cci0_default &cci1_default>;
2293 cci_i2c0: i2c-bus@0 {
2295 clock-frequency = <400000>;
2296 #address-cells = <1>;
2297 #size-cells = <0>;
2300 cci_i2c1: i2c-bus@1 {
2302 clock-frequency = <400000>;
2303 #address-cells = <1>;
2304 #size-cells = <0>;
2309 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2312 #global-interrupts = <1>;
2316 #iommu-cells = <1>;
2320 clock-names = "bus", "iface";
2322 power-domains = <&mmcc GPU_GDSC>;
2325 venus: video-codec@c00000 {
2326 compatible = "qcom,msm8996-venus";
2329 power-domains = <&mmcc VENUS_GDSC>;
2334 clock-names = "core", "iface", "bus", "mbus";
2337 interconnect-names = "video-mem", "cpu-cfg";
2358 memory-region = <&venus_mem>;
2361 video-decoder {
2362 compatible = "venus-decoder";
2364 clock-names = "core";
2365 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2368 video-encoder {
2369 compatible = "venus-encoder";
2371 clock-names = "core";
2372 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2377 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2380 #global-interrupts = <1>;
2384 #iommu-cells = <1>;
2387 clock-names = "bus", "iface";
2389 power-domains = <&mmcc MDSS_GDSC>;
2393 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2395 #global-interrupts = <1>;
2404 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2407 clock-names = "bus", "iface";
2408 #iommu-cells = <1>;
2413 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2416 #global-interrupts = <1>;
2420 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2423 clock-names = "bus", "iface";
2424 #iommu-cells = <1>;
2428 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2430 #iommu-cells = <1>;
2431 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2433 #global-interrupts = <1>;
2450 clock-names = "bus", "iface";
2454 compatible = "qcom,msm8996-slpi-pil";
2457 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2462 interrupt-names = "wdog",
2466 "stop-ack";
2470 clock-names = "xo", "aggre2";
2472 memory-region = <&slpi_mem>;
2474 qcom,smem-states = <&slpi_smp2p_out 0>;
2475 qcom,smem-state-names = "stop";
2477 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2478 power-domain-names = "ssc_cx";
2482 smd-edge {
2487 qcom,smd-edge = <3>;
2488 qcom,remote-pid = <3>;
2493 compatible = "qcom,msm8996-mss-pil";
2496 reg-names = "qdsp6", "rmb";
2498 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2504 interrupt-names = "wdog", "fatal", "ready",
2505 "handover", "stop-ack",
2506 "shutdown-ack";
2517 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
2521 reset-names = "mss_restart";
2523 power-domains = <&rpmpd MSM8996_VDDCX>,
2525 power-domain-names = "cx", "mx";
2527 qcom,smem-states = <&mpss_smp2p_out 0>;
2528 qcom,smem-state-names = "stop";
2530 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2535 memory-region = <&mba_mem>;
2539 memory-region = <&mpss_mem>;
2543 memory-region = <&mdata_mem>;
2546 smd-edge {
2551 qcom,smd-edge = <0>;
2552 qcom,remote-pid = <1>;
2557 compatible = "arm,coresight-stm", "arm,primecell";
2560 reg-names = "stm-base", "stm-stimulus-base";
2563 clock-names = "apb_pclk", "atclk";
2565 out-ports {
2568 remote-endpoint =
2576 compatible = "arm,coresight-tpiu", "arm,primecell";
2580 clock-names = "apb_pclk", "atclk";
2582 in-ports {
2585 remote-endpoint =
2593 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2597 clock-names = "apb_pclk", "atclk";
2599 in-ports {
2600 #address-cells = <1>;
2601 #size-cells = <0>;
2606 remote-endpoint =
2612 out-ports {
2615 remote-endpoint =
2623 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2627 clock-names = "apb_pclk", "atclk";
2629 in-ports {
2630 #address-cells = <1>;
2631 #size-cells = <0>;
2636 remote-endpoint =
2642 out-ports {
2645 remote-endpoint =
2653 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2657 clock-names = "apb_pclk", "atclk";
2659 in-ports {
2662 remote-endpoint =
2668 out-ports {
2671 remote-endpoint =
2679 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2683 clock-names = "apb_pclk", "atclk";
2685 in-ports {
2686 #address-cells = <1>;
2687 #size-cells = <0>;
2692 remote-endpoint =
2700 remote-endpoint =
2708 remote-endpoint =
2714 out-ports {
2717 remote-endpoint =
2725 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2729 clock-names = "apb_pclk", "atclk";
2731 in-ports {
2734 remote-endpoint =
2740 out-ports {
2741 #address-cells = <1>;
2742 #size-cells = <0>;
2747 remote-endpoint =
2755 remote-endpoint =
2763 compatible = "arm,coresight-tmc", "arm,primecell";
2767 clock-names = "apb_pclk", "atclk";
2769 in-ports {
2772 remote-endpoint =
2778 out-ports {
2781 remote-endpoint =
2789 compatible = "arm,coresight-tmc", "arm,primecell";
2793 clock-names = "apb_pclk", "atclk";
2794 arm,scatter-gather;
2796 in-ports {
2799 remote-endpoint =
2807 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2811 clock-names = "apb_pclk";
2817 compatible = "arm,coresight-etm4x", "arm,primecell";
2821 clock-names = "apb_pclk", "atclk";
2825 out-ports {
2828 remote-endpoint =
2836 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2840 clock-names = "apb_pclk";
2846 compatible = "arm,coresight-etm4x", "arm,primecell";
2850 clock-names = "apb_pclk", "atclk";
2854 out-ports {
2857 remote-endpoint =
2865 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2869 clock-names = "apb_pclk", "atclk";
2871 in-ports {
2872 #address-cells = <1>;
2873 #size-cells = <0>;
2878 remote-endpoint = <&etm0_out>;
2885 remote-endpoint = <&etm1_out>;
2890 out-ports {
2893 remote-endpoint =
2901 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2905 clock-names = "apb_pclk";
2911 compatible = "arm,coresight-etm4x", "arm,primecell";
2915 clock-names = "apb_pclk", "atclk";
2919 out-ports {
2922 remote-endpoint =
2930 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2934 clock-names = "apb_pclk";
2940 compatible = "arm,coresight-etm4x", "arm,primecell";
2944 clock-names = "apb_pclk", "atclk";
2948 out-ports {
2951 remote-endpoint =
2959 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2963 clock-names = "apb_pclk", "atclk";
2965 in-ports {
2966 #address-cells = <1>;
2967 #size-cells = <0>;
2972 remote-endpoint = <&etm2_out>;
2979 remote-endpoint = <&etm3_out>;
2984 out-ports {
2987 remote-endpoint =
2995 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2999 clock-names = "apb_pclk", "atclk";
3001 in-ports {
3002 #address-cells = <1>;
3003 #size-cells = <0>;
3008 remote-endpoint =
3016 remote-endpoint =
3022 out-ports {
3025 remote-endpoint =
3032 kryocc: clock-controller@6400000 {
3033 compatible = "qcom,msm8996-apcc";
3036 clock-names = "xo", "sys_apcs_aux";
3039 #clock-cells = <1>;
3043 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3045 #address-cells = <1>;
3046 #size-cells = <1>;
3051 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3058 clock-names = "cfg_noc",
3064 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3066 assigned-clock-rates = <19200000>, <120000000>;
3070 interconnect-names = "usb-ddr", "apps-usb";
3072 power-domains = <&gcc USB30_GDSC>;
3080 phy-names = "usb2-phy", "usb3-phy";
3081 snps,hird-threshold = /bits/ 8 <0>;
3084 snps,is-utmi-l1-suspend;
3085 snps,parkmode-disable-ss-quirk;
3086 tx-fifo-resize;
3091 compatible = "qcom,msm8996-qmp-usb3-phy";
3093 #address-cells = <1>;
3094 #size-cells = <1>;
3100 clock-names = "aux", "cfg_ahb", "ref";
3104 reset-names = "phy", "common";
3111 #phy-cells = <0>;
3113 #clock-cells = <0>;
3114 clock-output-names = "usb3_phy_pipe_clk_src";
3116 clock-names = "pipe0";
3121 compatible = "qcom,msm8996-qusb2-phy";
3123 #phy-cells = <0>;
3127 clock-names = "cfg_ahb", "ref";
3130 nvmem-cells = <&qusb2p_hstx_trim>;
3135 compatible = "qcom,msm8996-qusb2-phy";
3137 #phy-cells = <0>;
3141 clock-names = "cfg_ahb", "ref";
3144 nvmem-cells = <&qusb2s_hstx_trim>;
3149 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3151 reg-names = "hc", "core";
3155 interrupt-names = "hc_irq", "pwr_irq";
3157 clock-names = "iface", "core", "xo";
3163 pinctrl-names = "default", "sleep";
3164 pinctrl-0 = <&sdc1_state_on>;
3165 pinctrl-1 = <&sdc1_state_off>;
3167 bus-width = <8>;
3168 non-removable;
3173 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3175 reg-names = "hc", "core";
3179 interrupt-names = "hc_irq", "pwr_irq";
3181 clock-names = "iface", "core", "xo";
3187 pinctrl-names = "default", "sleep";
3188 pinctrl-0 = <&sdc2_state_on>;
3189 pinctrl-1 = <&sdc2_state_off>;
3191 bus-width = <4>;
3195 blsp1_dma: dma-controller@7544000 {
3196 compatible = "qcom,bam-v1.7.0";
3200 clock-names = "bam_clk";
3201 qcom,controlled-remotely;
3202 #dma-cells = <1>;
3207 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3212 clock-names = "core", "iface";
3213 pinctrl-names = "default", "sleep";
3214 pinctrl-0 = <&blsp1_uart2_default>;
3215 pinctrl-1 = <&blsp1_uart2_sleep>;
3217 dma-names = "tx", "rx";
3222 compatible = "qcom,spi-qup-v2.2.1";
3227 clock-names = "core", "iface";
3228 pinctrl-names = "default", "sleep";
3229 pinctrl-0 = <&blsp1_spi1_default>;
3230 pinctrl-1 = <&blsp1_spi1_sleep>;
3232 dma-names = "tx", "rx";
3233 #address-cells = <1>;
3234 #size-cells = <0>;
3239 compatible = "qcom,i2c-qup-v2.2.1";
3244 clock-names = "core", "iface";
3245 pinctrl-names = "default", "sleep";
3246 pinctrl-0 = <&blsp1_i2c3_default>;
3247 pinctrl-1 = <&blsp1_i2c3_sleep>;
3249 dma-names = "tx", "rx";
3250 #address-cells = <1>;
3251 #size-cells = <0>;
3256 compatible = "qcom,i2c-qup-v2.2.1";
3261 clock-names = "core", "iface";
3262 pinctrl-names = "default", "sleep";
3263 pinctrl-0 = <&blsp1_i2c6_default>;
3264 pinctrl-1 = <&blsp1_i2c6_sleep>;
3266 dma-names = "tx", "rx";
3267 #address-cells = <1>;
3268 #size-cells = <0>;
3272 blsp2_dma: dma-controller@7584000 {
3273 compatible = "qcom,bam-v1.7.0";
3277 clock-names = "bam_clk";
3278 qcom,controlled-remotely;
3279 #dma-cells = <1>;
3284 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3289 clock-names = "core", "iface";
3294 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3299 clock-names = "core", "iface";
3304 compatible = "qcom,i2c-qup-v2.2.1";
3309 clock-names = "core", "iface";
3310 pinctrl-names = "default", "sleep";
3311 pinctrl-0 = <&blsp2_i2c1_default>;
3312 pinctrl-1 = <&blsp2_i2c1_sleep>;
3314 dma-names = "tx", "rx";
3315 #address-cells = <1>;
3316 #size-cells = <0>;
3321 compatible = "qcom,i2c-qup-v2.2.1";
3326 clock-names = "core", "iface";
3327 pinctrl-names = "default", "sleep";
3328 pinctrl-0 = <&blsp2_i2c2_default>;
3329 pinctrl-1 = <&blsp2_i2c2_sleep>;
3331 dma-names = "tx", "rx";
3332 #address-cells = <1>;
3333 #size-cells = <0>;
3338 compatible = "qcom,i2c-qup-v2.2.1";
3343 clock-names = "core", "iface";
3344 clock-frequency = <400000>;
3345 pinctrl-names = "default", "sleep";
3346 pinctrl-0 = <&blsp2_i2c3_default>;
3347 pinctrl-1 = <&blsp2_i2c3_sleep>;
3349 dma-names = "tx", "rx";
3350 #address-cells = <1>;
3351 #size-cells = <0>;
3356 compatible = "qcom,i2c-qup-v2.2.1";
3361 clock-names = "core", "iface";
3362 pinctrl-names = "default";
3363 pinctrl-0 = <&blsp2_i2c5_default>;
3365 dma-names = "tx", "rx";
3366 #address-cells = <1>;
3367 #size-cells = <0>;
3372 compatible = "qcom,i2c-qup-v2.2.1";
3377 clock-names = "core", "iface";
3378 pinctrl-names = "default", "sleep";
3379 pinctrl-0 = <&blsp2_i2c6_default>;
3380 pinctrl-1 = <&blsp2_i2c6_sleep>;
3382 dma-names = "tx", "rx";
3383 #address-cells = <1>;
3384 #size-cells = <0>;
3389 compatible = "qcom,spi-qup-v2.2.1";
3394 clock-names = "core", "iface";
3395 pinctrl-names = "default", "sleep";
3396 pinctrl-0 = <&blsp2_spi6_default>;
3397 pinctrl-1 = <&blsp2_spi6_sleep>;
3399 dma-names = "tx", "rx";
3400 #address-cells = <1>;
3401 #size-cells = <0>;
3406 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3408 #address-cells = <1>;
3409 #size-cells = <1>;
3413 interrupt-names = "hs_phy_irq";
3420 clock-names = "cfg_noc",
3426 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3428 assigned-clock-rates = <19200000>, <60000000>;
3430 power-domains = <&gcc USB30_GDSC>;
3431 qcom,select-utmi-as-pipe-clk;
3439 phy-names = "usb2-phy";
3440 maximum-speed = "high-speed";
3446 slimbam: dma-controller@9184000 {
3447 compatible = "qcom,bam-v1.7.0";
3448 qcom,controlled-remotely;
3450 num-channels = <31>;
3452 #dma-cells = <1>;
3454 qcom,num-ees = <2>;
3457 slim_msm: slim-ngd@91c0000 {
3458 compatible = "qcom,slim-ngd-v1.5.0";
3462 dma-names = "rx", "tx";
3463 #address-cells = <1>;
3464 #size-cells = <0>;
3470 compatible = "qcom,msm8996-adsp-pil";
3473 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3478 interrupt-names = "wdog", "fatal", "ready",
3479 "handover", "stop-ack";
3482 clock-names = "xo";
3484 memory-region = <&adsp_mem>;
3486 qcom,smem-states = <&adsp_smp2p_out 0>;
3487 qcom,smem-state-names = "stop";
3489 power-domains = <&rpmpd MSM8996_VDDCX>;
3490 power-domain-names = "cx";
3494 smd-edge {
3499 qcom,smd-edge = <1>;
3500 qcom,remote-pid = <2>;
3503 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3504 compatible = "qcom,apr-v2";
3505 qcom,smd-channels = "apr_audio_svc";
3507 #address-cells = <1>;
3508 #size-cells = <0>;
3519 compatible = "qcom,q6afe-dais";
3520 #address-cells = <1>;
3521 #size-cells = <0>;
3522 #sound-dai-cells = <1>;
3533 compatible = "qcom,q6asm-dais";
3534 #address-cells = <1>;
3535 #size-cells = <0>;
3536 #sound-dai-cells = <1>;
3545 compatible = "qcom,q6adm-routing";
3546 #sound-dai-cells = <0>;
3554 compatible = "qcom,msm8996-apcs-hmss-global";
3557 #mbox-cells = <1>;
3558 #clock-cells = <0>;
3562 #address-cells = <1>;
3563 #size-cells = <1>;
3565 compatible = "arm,armv7-timer-mem";
3567 clock-frequency = <19200000>;
3570 frame-number = <0>;
3578 frame-number = <1>;
3585 frame-number = <2>;
3592 frame-number = <3>;
3599 frame-number = <4>;
3606 frame-number = <5>;
3613 frame-number = <6>;
3625 cbf: clock-controller@9a11000 {
3626 compatible = "qcom,msm8996-cbf";
3629 #clock-cells = <0>;
3630 #interconnect-cells = <1>;
3633 intc: interrupt-controller@9bc0000 {
3634 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3635 #interrupt-cells = <3>;
3636 interrupt-controller;
3637 #redistributor-regions = <1>;
3638 redistributor-stride = <0x0 0x40000>;
3648 thermal-zones {
3649 cpu0-thermal {
3650 polling-delay-passive = <250>;
3651 polling-delay = <1000>;
3653 thermal-sensors = <&tsens0 3>;
3656 cpu0_alert0: trip-point0 {
3662 cpu0_crit: cpu-crit {
3670 cpu1-thermal {
3671 polling-delay-passive = <250>;
3672 polling-delay = <1000>;
3674 thermal-sensors = <&tsens0 5>;
3677 cpu1_alert0: trip-point0 {
3683 cpu1_crit: cpu-crit {
3691 cpu2-thermal {
3692 polling-delay-passive = <250>;
3693 polling-delay = <1000>;
3695 thermal-sensors = <&tsens0 8>;
3698 cpu2_alert0: trip-point0 {
3704 cpu2_crit: cpu-crit {
3712 cpu3-thermal {
3713 polling-delay-passive = <250>;
3714 polling-delay = <1000>;
3716 thermal-sensors = <&tsens0 10>;
3719 cpu3_alert0: trip-point0 {
3725 cpu3_crit: cpu-crit {
3733 gpu-top-thermal {
3734 polling-delay-passive = <250>;
3735 polling-delay = <1000>;
3737 thermal-sensors = <&tsens1 6>;
3740 gpu1_alert0: trip-point0 {
3747 cooling-maps {
3750 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3755 gpu-bottom-thermal {
3756 polling-delay-passive = <250>;
3757 polling-delay = <1000>;
3759 thermal-sensors = <&tsens1 7>;
3762 gpu2_alert0: trip-point0 {
3769 cooling-maps {
3772 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3777 m4m-thermal {
3778 polling-delay-passive = <250>;
3779 polling-delay = <1000>;
3781 thermal-sensors = <&tsens0 1>;
3784 m4m_alert0: trip-point0 {
3792 l3-or-venus-thermal {
3793 polling-delay-passive = <250>;
3794 polling-delay = <1000>;
3796 thermal-sensors = <&tsens0 2>;
3799 l3_or_venus_alert0: trip-point0 {
3807 cluster0-l2-thermal {
3808 polling-delay-passive = <250>;
3809 polling-delay = <1000>;
3811 thermal-sensors = <&tsens0 7>;
3814 cluster0_l2_alert0: trip-point0 {
3822 cluster1-l2-thermal {
3823 polling-delay-passive = <250>;
3824 polling-delay = <1000>;
3826 thermal-sensors = <&tsens0 12>;
3829 cluster1_l2_alert0: trip-point0 {
3837 camera-thermal {
3838 polling-delay-passive = <250>;
3839 polling-delay = <1000>;
3841 thermal-sensors = <&tsens1 1>;
3844 camera_alert0: trip-point0 {
3852 q6-dsp-thermal {
3853 polling-delay-passive = <250>;
3854 polling-delay = <1000>;
3856 thermal-sensors = <&tsens1 2>;
3859 q6_dsp_alert0: trip-point0 {
3867 mem-thermal {
3868 polling-delay-passive = <250>;
3869 polling-delay = <1000>;
3871 thermal-sensors = <&tsens1 3>;
3874 mem_alert0: trip-point0 {
3882 modemtx-thermal {
3883 polling-delay-passive = <250>;
3884 polling-delay = <1000>;
3886 thermal-sensors = <&tsens1 4>;
3889 modemtx_alert0: trip-point0 {
3899 compatible = "arm,armv8-timer";