Lines Matching full:mmcc
8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
921 <&mmcc AHB_CLK_SRC>;
949 mmcc: clock-controller@8c0000 { label
950 compatible = "qcom,mmcc-msm8996";
971 assigned-clocks = <&mmcc MMPLL9_PLL>,
972 <&mmcc MMPLL1_PLL>,
973 <&mmcc MMPLL3_PLL>,
974 <&mmcc MMPLL4_PLL>,
975 <&mmcc MMPLL5_PLL>;
993 power-domains = <&mmcc MDSS_GDSC>;
999 clocks = <&mmcc MDSS_AHB_CLK>,
1000 <&mmcc MDSS_MDP_CLK>;
1017 clocks = <&mmcc MDSS_AHB_CLK>,
1018 <&mmcc MDSS_AXI_CLK>,
1019 <&mmcc MDSS_MDP_CLK>,
1020 <&mmcc SMMU_MDP_AXI_CLK>,
1021 <&mmcc MDSS_VSYNC_CLK>;
1030 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1031 <&mmcc MDSS_VSYNC_CLK>;
1076 clocks = <&mmcc MDSS_MDP_CLK>,
1077 <&mmcc MDSS_BYTE0_CLK>,
1078 <&mmcc MDSS_AHB_CLK>,
1079 <&mmcc MDSS_AXI_CLK>,
1080 <&mmcc MMSS_MISC_AHB_CLK>,
1081 <&mmcc MDSS_PCLK0_CLK>,
1082 <&mmcc MDSS_ESC0_CLK>;
1090 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1130 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1144 clocks = <&mmcc MDSS_MDP_CLK>,
1145 <&mmcc MDSS_BYTE1_CLK>,
1146 <&mmcc MDSS_AHB_CLK>,
1147 <&mmcc MDSS_AXI_CLK>,
1148 <&mmcc MMSS_MISC_AHB_CLK>,
1149 <&mmcc MDSS_PCLK1_CLK>,
1150 <&mmcc MDSS_ESC1_CLK>;
1158 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1198 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1215 clocks = <&mmcc MDSS_MDP_CLK>,
1216 <&mmcc MDSS_AHB_CLK>,
1217 <&mmcc MDSS_HDMI_CLK>,
1218 <&mmcc MDSS_HDMI_AHB_CLK>,
1219 <&mmcc MDSS_EXTPCLK_CLK>;
1261 clocks = <&mmcc MDSS_AHB_CLK>,
1282 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1283 <&mmcc GPU_AHB_CLK>,
1284 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1297 power-domains = <&mmcc GPU_GX_GDSC>;
2186 power-domains = <&mmcc VFE0_GDSC>,
2187 <&mmcc VFE1_GDSC>;
2188 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2189 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2190 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2191 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2192 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2193 <&mmcc CAMSS_CSI0_AHB_CLK>,
2194 <&mmcc CAMSS_CSI0_CLK>,
2195 <&mmcc CAMSS_CSI0PHY_CLK>,
2196 <&mmcc CAMSS_CSI0PIX_CLK>,
2197 <&mmcc CAMSS_CSI0RDI_CLK>,
2198 <&mmcc CAMSS_CSI1_AHB_CLK>,
2199 <&mmcc CAMSS_CSI1_CLK>,
2200 <&mmcc CAMSS_CSI1PHY_CLK>,
2201 <&mmcc CAMSS_CSI1PIX_CLK>,
2202 <&mmcc CAMSS_CSI1RDI_CLK>,
2203 <&mmcc CAMSS_CSI2_AHB_CLK>,
2204 <&mmcc CAMSS_CSI2_CLK>,
2205 <&mmcc CAMSS_CSI2PHY_CLK>,
2206 <&mmcc CAMSS_CSI2PIX_CLK>,
2207 <&mmcc CAMSS_CSI2RDI_CLK>,
2208 <&mmcc CAMSS_CSI3_AHB_CLK>,
2209 <&mmcc CAMSS_CSI3_CLK>,
2210 <&mmcc CAMSS_CSI3PHY_CLK>,
2211 <&mmcc CAMSS_CSI3PIX_CLK>,
2212 <&mmcc CAMSS_CSI3RDI_CLK>,
2213 <&mmcc CAMSS_AHB_CLK>,
2214 <&mmcc CAMSS_VFE0_CLK>,
2215 <&mmcc CAMSS_CSI_VFE0_CLK>,
2216 <&mmcc CAMSS_VFE0_AHB_CLK>,
2217 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2218 <&mmcc CAMSS_VFE1_CLK>,
2219 <&mmcc CAMSS_CSI_VFE1_CLK>,
2220 <&mmcc CAMSS_VFE1_AHB_CLK>,
2221 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2222 <&mmcc CAMSS_VFE_AHB_CLK>,
2223 <&mmcc CAMSS_VFE_AXI_CLK>;
2277 power-domains = <&mmcc CAMSS_GDSC>;
2278 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2279 <&mmcc CAMSS_CCI_AHB_CLK>,
2280 <&mmcc CAMSS_CCI_CLK>,
2281 <&mmcc CAMSS_AHB_CLK>;
2286 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2287 <&mmcc CAMSS_CCI_CLK>;
2319 <&mmcc GPU_AHB_CLK>;
2322 power-domains = <&mmcc GPU_GDSC>;
2329 power-domains = <&mmcc VENUS_GDSC>;
2330 clocks = <&mmcc VIDEO_CORE_CLK>,
2331 <&mmcc VIDEO_AHB_CLK>,
2332 <&mmcc VIDEO_AXI_CLK>,
2333 <&mmcc VIDEO_MAXI_CLK>;
2363 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2365 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2370 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2372 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2385 clocks = <&mmcc SMMU_MDP_AXI_CLK>,
2386 <&mmcc SMMU_MDP_AHB_CLK>;
2389 power-domains = <&mmcc MDSS_GDSC>;
2404 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2405 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
2406 <&mmcc SMMU_VIDEO_AHB_CLK>;
2420 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2421 clocks = <&mmcc SMMU_VFE_AXI_CLK>,
2422 <&mmcc SMMU_VFE_AHB_CLK>;