Lines Matching +full:0 +full:x00a30000
28 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
52 clocks = <&kryocc 0>;
67 reg = <0x0 0x1>;
71 clocks = <&kryocc 0>;
81 reg = <0x0 0x100>;
100 reg = <0x0 0x101>;
136 CPU_SLEEP_0: cpu-sleep-0 {
139 arm,psci-suspend-param = <0x00000004>;
155 opp-supported-hw = <0xf>;
161 opp-supported-hw = <0xf>;
167 opp-supported-hw = <0xf>;
173 opp-supported-hw = <0xf>;
179 opp-supported-hw = <0xf>;
185 opp-supported-hw = <0xf>;
191 opp-supported-hw = <0xf>;
197 opp-supported-hw = <0xf>;
203 opp-supported-hw = <0xf>;
209 opp-supported-hw = <0xf>;
215 opp-supported-hw = <0xf>;
221 opp-supported-hw = <0xf>;
227 opp-supported-hw = <0xd>;
233 opp-supported-hw = <0x2>;
239 opp-supported-hw = <0xd>;
245 opp-supported-hw = <0x9>;
251 opp-supported-hw = <0x04>;
257 opp-supported-hw = <0x9>;
271 opp-supported-hw = <0xf>;
277 opp-supported-hw = <0xf>;
283 opp-supported-hw = <0xf>;
289 opp-supported-hw = <0xf>;
295 opp-supported-hw = <0xf>;
301 opp-supported-hw = <0xf>;
307 opp-supported-hw = <0xf>;
313 opp-supported-hw = <0xf>;
319 opp-supported-hw = <0xf>;
325 opp-supported-hw = <0xf>;
331 opp-supported-hw = <0xf>;
337 opp-supported-hw = <0xf>;
343 opp-supported-hw = <0xf>;
349 opp-supported-hw = <0xf>;
355 opp-supported-hw = <0xf>;
361 opp-supported-hw = <0xf>;
367 opp-supported-hw = <0xf>;
373 opp-supported-hw = <0xf>;
379 opp-supported-hw = <0xf>;
385 opp-supported-hw = <0xf>;
391 opp-supported-hw = <0xe>;
397 opp-supported-hw = <0x1>;
403 opp-supported-hw = <0x4>;
409 opp-supported-hw = <0x1>;
415 opp-supported-hw = <0x1>;
421 opp-supported-hw = <0x1>;
427 opp-supported-hw = <0x1>;
436 qcom,dload-mode = <&tcsr_2 0x13000>;
443 reg = <0x0 0x80000000 0x0 0x0>;
471 mboxes = <&apcs_glb 0>;
527 reg = <0x0 0x85800000 0x0 0x600000>;
532 reg = <0x0 0x85e00000 0x0 0x200000>;
537 reg = <0x0 0x86000000 0x0 0x200000>;
542 reg = <0x0 0x86200000 0x0 0x2600000>;
549 size = <0x0 0x200000>;
550 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
558 reg = <0x0 0x88800000 0x0 0x6200000>;
563 reg = <0x0 0x8ea00000 0x0 0x1b00000>;
568 reg = <0x0 0x90500000 0x0 0xa00000>;
574 reg = <0x0 0x90f00000 0x0 0x100000>;
579 reg = <0x0 0x91000000 0x0 0x500000>;
584 reg = <0x0 0x91500000 0x0 0x200000>;
589 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
590 size = <0x0 0x4000>;
609 qcom,local-pid = <0>;
633 qcom,local-pid = <0>;
657 qcom,local-pid = <0>;
673 soc: soc@0 {
676 ranges = <0 0 0 0xffffffff>;
681 reg = <0x00034000 0x488>;
684 ranges = <0x0 0x00034000 0x4000>;
699 reg = <0x1000 0x130>,
700 <0x1200 0x200>,
701 <0x1400 0x1dc>;
708 #clock-cells = <0>;
711 #phy-cells = <0>;
715 reg = <0x2000 0x130>,
716 <0x2200 0x200>,
717 <0x2400 0x1dc>;
724 #clock-cells = <0>;
727 #phy-cells = <0>;
731 reg = <0x3000 0x130>,
732 <0x3200 0x200>,
733 <0x3400 0x1dc>;
740 #clock-cells = <0>;
743 #phy-cells = <0>;
749 reg = <0x00068000 0x6000>;
754 reg = <0x00074000 0x8ff>;
759 reg = <0x24e 0x2>;
764 reg = <0x24f 0x1>;
769 reg = <0x133 0x1>;
776 reg = <0x00083000 0x1000>;
786 reg = <0x00300000 0x90000>;
795 <&ufsphy_lane 0>,
812 reg = <0x00408000 0x5a000>;
821 reg = <0x004a9000 0x1000>, /* TM */
822 <0x004a8000 0x1000>; /* SROT */
832 reg = <0x004ad000 0x1000>, /* TM */
833 <0x004ac000 0x1000>; /* SROT */
843 reg = <0x00644000 0x24000>;
848 qcom,ee = <0>;
854 reg = <0x0067a000 0x6000>;
865 reg = <0x00500000 0x1000>;
874 reg = <0x00524000 0x1c000>;
883 reg = <0x00543000 0x6000>;
896 reg = <0x00562000 0x5000>;
905 reg = <0x00583000 0x7000>;
916 reg = <0x005a4000 0x1c000>;
926 reg = <0x005c0000 0x3000>;
935 reg = <0x00740000 0x20000>;
941 reg = <0x00760000 0x20000>;
946 reg = <0x007a0000 0x18000>;
954 reg = <0x008c0000 0x40000>;
959 <&mdss_dsi0_phy 0>,
961 <&mdss_dsi1_phy 0>,
986 reg = <0x00900000 0x1000>,
987 <0x009b0000 0x1040>,
988 <0x009b8000 0x1040>;
1011 reg = <0x00901000 0x90000>;
1015 interrupts = <0>;
1028 iommus = <&mdp_smmu 0>;
1042 #size-cells = <0>;
1044 port@0 {
1045 reg = <0>;
1070 reg = <0x00994000 0x400>;
1091 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1097 #size-cells = <0>;
1101 #size-cells = <0>;
1103 port@0 {
1104 reg = <0>;
1120 reg = <0x00994400 0x100>,
1121 <0x00994500 0x300>,
1122 <0x00994800 0x188>;
1128 #phy-cells = <0>;
1138 reg = <0x00996000 0x400>;
1159 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1165 #size-cells = <0>;
1169 #size-cells = <0>;
1171 port@0 {
1172 reg = <0>;
1188 reg = <0x00996400 0x100>,
1189 <0x00996500 0x300>,
1190 <0x00996800 0x188>;
1196 #phy-cells = <0>;
1205 reg = <0x009a0000 0x50c>,
1206 <0x00070000 0x6158>,
1207 <0x009e0000 0xfff>;
1234 #size-cells = <0>;
1236 port@0 {
1237 reg = <0>;
1246 #phy-cells = <0>;
1248 reg = <0x009a0600 0x1c4>,
1249 <0x009a0a00 0x124>,
1250 <0x009a0c00 0x124>,
1251 <0x009a0e00 0x124>,
1252 <0x009a1000 0x124>,
1253 <0x009a1200 0x0c8>;
1268 #clock-cells = <0>;
1277 reg = <0x00b00000 0x3f000>;
1298 iommus = <&adreno_smmu 0>;
1313 * 624Mhz is only available on speed bins 0 and 3.
1314 * 560Mhz is only available on speed bins 0, 2 and 3.
1319 opp-supported-hw = <0x09>;
1323 opp-supported-hw = <0x0d>;
1327 opp-supported-hw = <0xff>;
1331 opp-supported-hw = <0xff>;
1335 opp-supported-hw = <0xff>;
1339 opp-supported-hw = <0xff>;
1343 opp-supported-hw = <0xff>;
1354 reg = <0x01010000 0x300000>;
1357 gpio-ranges = <&tlmm 0 0 150>;
1873 reg = <0x00290000 0x10000>;
1878 reg = <0x0400f000 0x1000>,
1879 <0x04400000 0x800000>,
1880 <0x04c00000 0x800000>,
1881 <0x05800000 0x200000>,
1882 <0x0400a000 0x002100>;
1886 qcom,ee = <0>;
1887 qcom,channel = <0>;
1889 #size-cells = <0>;
1894 bus@0 {
1899 ranges = <0x0 0x0 0xffffffff>;
1905 bus-range = <0x00 0xff>;
1908 reg = <0x00600000 0x2000>,
1909 <0x0c000000 0xf1d>,
1910 <0x0c000f20 0xa8>,
1911 <0x0c100000 0x100000>;
1919 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1920 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1927 interrupt-map-mask = <0 0 0 0x7>;
1928 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1929 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1930 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1931 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1934 pinctrl-0 = <&pcie0_state_on>;
1937 linux,pci-domain = <0>;
1955 bus-range = <0x00 0xff>;
1960 reg = <0x00608000 0x2000>,
1961 <0x0d000000 0xf1d>,
1962 <0x0d000f20 0xa8>,
1963 <0x0d100000 0x100000>;
1972 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1973 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1980 interrupt-map-mask = <0 0 0 0x7>;
1981 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1982 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1983 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1984 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1987 pinctrl-0 = <&pcie1_state_on>;
2008 bus-range = <0x00 0xff>;
2011 reg = <0x00610000 0x2000>,
2012 <0x0e000000 0xf1d>,
2013 <0x0e000f20 0xa8>,
2014 <0x0e100000 0x100000>;
2023 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
2024 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2031 interrupt-map-mask = <0 0 0 0x7>;
2032 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2033 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2034 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2035 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2038 pinctrl-0 = <&pcie2_state_on>;
2059 reg = <0x00624000 0x2500>;
2094 <0 0>,
2095 <0 0>,
2096 <0 0>,
2098 <0 0>,
2099 <0 0>,
2100 <0 0>,
2101 <0 0>,
2102 <0 0>;
2115 reg = <0x00627000 0x1c4>;
2123 resets = <&ufshc 0>;
2128 reg = <0x627400 0x12c>,
2129 <0x627600 0x200>,
2130 <0x627c00 0x1b4>;
2132 #phy-cells = <0>;
2138 reg = <0x00a34000 0x1000>,
2139 <0x00a00030 0x4>,
2140 <0x00a35000 0x1000>,
2141 <0x00a00038 0x4>,
2142 <0x00a36000 0x1000>,
2143 <0x00a00040 0x4>,
2144 <0x00a30000 0x100>,
2145 <0x00a30400 0x100>,
2146 <0x00a30800 0x100>,
2147 <0x00a30c00 0x100>,
2148 <0x00a31000 0x500>,
2149 <0x00a00020 0x10>,
2150 <0x00a10000 0x1000>,
2151 <0x00a14000 0x1000>;
2260 iommus = <&vfe_smmu 0>,
2267 #size-cells = <0>;
2274 #size-cells = <0>;
2275 reg = <0xa0c000 0x1000>;
2290 pinctrl-0 = <&cci0_default &cci1_default>;
2293 cci_i2c0: i2c-bus@0 {
2294 reg = <0>;
2297 #size-cells = <0>;
2304 #size-cells = <0>;
2310 reg = <0x00b40000 0x10000>;
2327 reg = <0x00c00000 0xff000>;
2338 iommus = <&venus_smmu 0x00>,
2339 <&venus_smmu 0x01>,
2340 <&venus_smmu 0x0a>,
2341 <&venus_smmu 0x07>,
2342 <&venus_smmu 0x0e>,
2343 <&venus_smmu 0x0f>,
2344 <&venus_smmu 0x08>,
2345 <&venus_smmu 0x09>,
2346 <&venus_smmu 0x0b>,
2347 <&venus_smmu 0x0c>,
2348 <&venus_smmu 0x0d>,
2349 <&venus_smmu 0x10>,
2350 <&venus_smmu 0x11>,
2351 <&venus_smmu 0x21>,
2352 <&venus_smmu 0x28>,
2353 <&venus_smmu 0x29>,
2354 <&venus_smmu 0x2b>,
2355 <&venus_smmu 0x2c>,
2356 <&venus_smmu 0x2d>,
2357 <&venus_smmu 0x31>;
2378 reg = <0x00d00000 0x10000>;
2394 reg = <0x00d40000 0x20000>;
2414 reg = <0x00da0000 0x10000>;
2429 reg = <0x01600000 0x20000>;
2455 reg = <0x01c00000 0x4000>;
2457 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2458 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2474 qcom,smem-states = <&slpi_smp2p_out 0>;
2494 reg = <0x2080000 0x100>,
2495 <0x2180000 0x020>;
2498 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2499 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2527 qcom,smem-states = <&mpss_smp2p_out 0>;
2530 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2551 qcom,smd-edge = <0>;
2558 reg = <0x3002000 0x1000>,
2559 <0x8280000 0x180000>;
2577 reg = <0x3020000 0x1000>;
2594 reg = <0x3021000 0x1000>;
2601 #size-cells = <0>;
2624 reg = <0x3022000 0x1000>;
2631 #size-cells = <0>;
2654 reg = <0x3023000 0x1000>;
2680 reg = <0x3025000 0x1000>;
2687 #size-cells = <0>;
2689 port@0 {
2690 reg = <0>;
2726 reg = <0x3026000 0x1000>;
2742 #size-cells = <0>;
2744 port@0 {
2745 reg = <0>;
2764 reg = <0x3027000 0x1000>;
2790 reg = <0x3028000 0x1000>;
2808 reg = <0x3810000 0x1000>;
2818 reg = <0x3840000 0x1000>;
2837 reg = <0x3910000 0x1000>;
2847 reg = <0x3940000 0x1000>;
2864 funnel@39b0000 { /* APSS Funnel 0 */
2866 reg = <0x39b0000 0x1000>;
2873 #size-cells = <0>;
2875 port@0 {
2876 reg = <0>;
2902 reg = <0x3a10000 0x1000>;
2912 reg = <0x3a40000 0x1000>;
2931 reg = <0x3b10000 0x1000>;
2941 reg = <0x3b40000 0x1000>;
2960 reg = <0x3bb0000 0x1000>;
2967 #size-cells = <0>;
2969 port@0 {
2970 reg = <0>;
2996 reg = <0x3bc0000 0x1000>;
3003 #size-cells = <0>;
3005 port@0 {
3006 reg = <0>;
3034 reg = <0x06400000 0x90000>;
3044 reg = <0x06af8800 0x400>;
3077 reg = <0x06a00000 0xcc00>;
3081 snps,hird-threshold = /bits/ 8 <0>;
3092 reg = <0x07410000 0x1c4>;
3108 reg = <0x07410200 0x200>,
3109 <0x07410400 0x130>,
3110 <0x07410600 0x1a8>;
3111 #phy-cells = <0>;
3113 #clock-cells = <0>;
3122 reg = <0x07411000 0x180>;
3123 #phy-cells = <0>;
3136 reg = <0x07412000 0x180>;
3137 #phy-cells = <0>;
3150 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3164 pinctrl-0 = <&sdc1_state_on>;
3174 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3188 pinctrl-0 = <&sdc2_state_on>;
3197 reg = <0x07544000 0x2b000>;
3203 qcom,ee = <0>;
3208 reg = <0x07570000 0x1000>;
3214 pinctrl-0 = <&blsp1_uart2_default>;
3223 reg = <0x07575000 0x600>;
3229 pinctrl-0 = <&blsp1_spi1_default>;
3234 #size-cells = <0>;
3240 reg = <0x07577000 0x1000>;
3246 pinctrl-0 = <&blsp1_i2c3_default>;
3251 #size-cells = <0>;
3257 reg = <0x757a000 0x1000>;
3263 pinctrl-0 = <&blsp1_i2c6_default>;
3268 #size-cells = <0>;
3274 reg = <0x07584000 0x2b000>;
3280 qcom,ee = <0>;
3285 reg = <0x075b0000 0x1000>;
3295 reg = <0x075b1000 0x1000>;
3305 reg = <0x075b5000 0x1000>;
3311 pinctrl-0 = <&blsp2_i2c1_default>;
3316 #size-cells = <0>;
3322 reg = <0x075b6000 0x1000>;
3328 pinctrl-0 = <&blsp2_i2c2_default>;
3333 #size-cells = <0>;
3339 reg = <0x075b7000 0x1000>;
3346 pinctrl-0 = <&blsp2_i2c3_default>;
3351 #size-cells = <0>;
3357 reg = <0x75b9000 0x1000>;
3363 pinctrl-0 = <&blsp2_i2c5_default>;
3367 #size-cells = <0>;
3373 reg = <0x75ba000 0x1000>;
3379 pinctrl-0 = <&blsp2_i2c6_default>;
3384 #size-cells = <0>;
3390 reg = <0x075ba000 0x600>;
3396 pinctrl-0 = <&blsp2_spi6_default>;
3401 #size-cells = <0>;
3407 reg = <0x076f8800 0x400>;
3436 reg = <0x07600000 0xcc00>;
3449 reg = <0x09184000 0x32000>;
3459 reg = <0x091c0000 0x2c000>;
3464 #size-cells = <0>;
3471 reg = <0x09300000 0x80000>;
3473 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3474 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3486 qcom,smem-states = <&adsp_smp2p_out 0>;
3508 #size-cells = <0>;
3521 #size-cells = <0>;
3535 #size-cells = <0>;
3546 #sound-dai-cells = <0>;
3555 reg = <0x09820000 0x1000>;
3558 #clock-cells = <0>;
3566 reg = <0x09840000 0x1000>;
3570 frame-number = <0>;
3573 reg = <0x09850000 0x1000>,
3574 <0x09860000 0x1000>;
3580 reg = <0x09870000 0x1000>;
3587 reg = <0x09880000 0x1000>;
3594 reg = <0x09890000 0x1000>;
3601 reg = <0x098a0000 0x1000>;
3608 reg = <0x098b0000 0x1000>;
3615 reg = <0x098c0000 0x1000>;
3622 reg = <0x09a10000 0x1000>;
3627 reg = <0x09a11000 0x10000>;
3629 #clock-cells = <0>;
3638 redistributor-stride = <0x0 0x40000>;
3639 reg = <0x09bc0000 0x10000>,
3640 <0x09c00000 0x100000>;