Lines Matching +full:tsens +full:- +full:v1
1 // SPDX-License-Identifier: BSD-3-Clause
4 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/soc/qcom,apr.h>
10 #include <dt-bindings/sound/qcom,q6afe.h>
11 #include <dt-bindings/sound/qcom,q6asm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&intc>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 sleep_clk: sleep-clk {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <32768>;
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <19200000>;
33 clock-output-names = "xo";
38 #address-cells = <1>;
39 #size-cells = <0>;
43 compatible = "arm,cortex-a53";
45 enable-method = "psci";
46 capacity-dmips-mhz = <1024>;
47 next-level-cache = <&L2_0>;
48 #cooling-cells = <2>;
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 capacity-dmips-mhz = <1024>;
57 next-level-cache = <&L2_0>;
58 #cooling-cells = <2>;
63 compatible = "arm,cortex-a53";
65 enable-method = "psci";
66 capacity-dmips-mhz = <1024>;
67 next-level-cache = <&L2_0>;
68 #cooling-cells = <2>;
73 compatible = "arm,cortex-a53";
75 enable-method = "psci";
76 capacity-dmips-mhz = <1024>;
77 next-level-cache = <&L2_0>;
78 #cooling-cells = <2>;
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 capacity-dmips-mhz = <1024>;
87 next-level-cache = <&L2_1>;
88 #cooling-cells = <2>;
93 compatible = "arm,cortex-a53";
95 enable-method = "psci";
96 capacity-dmips-mhz = <1024>;
97 next-level-cache = <&L2_1>;
98 #cooling-cells = <2>;
103 compatible = "arm,cortex-a53";
105 enable-method = "psci";
106 capacity-dmips-mhz = <1024>;
107 next-level-cache = <&L2_1>;
108 #cooling-cells = <2>;
113 compatible = "arm,cortex-a53";
115 enable-method = "psci";
116 capacity-dmips-mhz = <1024>;
117 next-level-cache = <&L2_1>;
118 #cooling-cells = <2>;
121 cpu-map {
153 L2_0: l2-cache-0 {
155 cache-level = <2>;
156 cache-unified;
159 L2_1: l2-cache-1 {
161 cache-level = <2>;
162 cache-unified;
168 compatible = "qcom,scm-msm8953", "qcom,scm";
172 clock-names = "core", "bus", "iface";
173 #reset-cells = <1>;
184 compatible = "arm,cortex-a53-pmu";
189 compatible = "arm,psci-1.0";
194 compatible = "qcom,msm8953-rpm-proc", "qcom,rpm-proc";
196 smd-edge {
199 qcom,smd-edge = <15>;
201 rpm_requests: rpm-requests {
202 compatible = "qcom,rpm-msm8953";
203 qcom,smd-channels = "rpm_requests";
205 rpmcc: clock-controller {
206 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
208 clock-names = "xo";
209 #clock-cells = <1>;
212 rpmpd: power-controller {
213 compatible = "qcom,msm8953-rpmpd";
214 #power-domain-cells = <1>;
215 operating-points-v2 = <&rpmpd_opp_table>;
217 rpmpd_opp_table: opp-table {
218 compatible = "operating-points-v2";
221 opp-level = <RPM_SMD_LEVEL_RETENTION>;
225 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
229 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
233 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
237 opp-level = <RPM_SMD_LEVEL_SVS>;
241 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
245 opp-level = <RPM_SMD_LEVEL_NOM>;
249 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
253 opp-level = <RPM_SMD_LEVEL_TURBO>;
261 reserved-memory {
262 #address-cells = <2>;
263 #size-cells = <2>;
267 compatible = "shared-dma-pool";
269 no-map;
274 no-map;
280 qcom,rpm-msg-ram = <&rpm_msg_ram>;
282 no-map;
287 no-map;
292 no-map;
297 no-map;
302 no-map;
305 dfps_data_mem: dfps-data@90000000 {
307 no-map;
310 cont_splash_mem: cont-splash@90001000 {
312 no-map;
317 no-map;
322 no-map;
326 compatible = "qcom,rmtfs-mem";
328 no-map;
330 qcom,client-id = <1>;
334 smp2p-adsp {
342 qcom,local-pid = <0>;
343 qcom,remote-pid = <2>;
345 smp2p_adsp_out: master-kernel {
346 qcom,entry-name = "master-kernel";
347 #qcom,smem-state-cells = <1>;
350 smp2p_adsp_in: slave-kernel {
351 qcom,entry-name = "slave-kernel";
353 interrupt-controller;
354 #interrupt-cells = <2>;
358 smp2p-modem {
366 qcom,local-pid = <0>;
367 qcom,remote-pid = <1>;
369 smp2p_modem_out: master-kernel {
370 qcom,entry-name = "master-kernel";
372 #qcom,smem-state-cells = <1>;
375 smp2p_modem_in: slave-kernel {
376 qcom,entry-name = "slave-kernel";
378 interrupt-controller;
379 #interrupt-cells = <2>;
383 smp2p-wcnss {
391 qcom,local-pid = <0>;
392 qcom,remote-pid = <4>;
394 smp2p_wcnss_out: master-kernel {
395 qcom,entry-name = "master-kernel";
397 #qcom,smem-state-cells = <1>;
400 smp2p_wcnss_in: slave-kernel {
401 qcom,entry-name = "slave-kernel";
403 interrupt-controller;
404 #interrupt-cells = <2>;
411 #address-cells = <1>;
412 #size-cells = <0>;
414 qcom,ipc-1 = <&apcs 8 13>;
415 qcom,ipc-3 = <&apcs 8 19>;
420 #qcom,smem-state-cells = <1>;
427 interrupt-controller;
428 #interrupt-cells = <2>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
441 #address-cells = <1>;
442 #size-cells = <1>;
444 compatible = "simple-bus";
447 compatible = "qcom,rpm-msg-ram";
452 compatible = "qcom,msm8953-qusb2-phy";
454 #phy-cells = <0>;
458 clock-names = "cfg_ahb", "ref";
460 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>;
471 clock-names = "core";
474 tsens0: thermal-sensor@4a9000 {
475 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2";
481 interrupt-names = "uplow", "critical";
482 #thermal-sensor-cells = <1>;
491 compatible = "qcom,msm8953-pinctrl";
494 gpio-controller;
495 gpio-ranges = <&tlmm 0 0 142>;
496 #gpio-cells = <2>;
497 interrupt-controller;
498 #interrupt-cells = <2>;
500 uart_console_active: uart-console-active-state {
503 drive-strength = <2>;
504 bias-disable;
507 uart_console_sleep: uart-console-sleep-state {
510 drive-strength = <2>;
511 bias-pull-down;
514 sdc1_clk_on: sdc1-clk-on-state {
516 bias-disable;
517 drive-strength = <16>;
520 sdc1_clk_off: sdc1-clk-off-state {
522 bias-disable;
523 drive-strength = <2>;
526 sdc1_cmd_on: sdc1-cmd-on-state {
528 bias-disable;
529 drive-strength = <10>;
532 sdc1_cmd_off: sdc1-cmd-off-state {
534 bias-disable;
535 drive-strength = <2>;
538 sdc1_data_on: sdc1-data-on-state {
540 bias-pull-up;
541 drive-strength = <10>;
544 sdc1_data_off: sdc1-data-off-state {
546 bias-pull-up;
547 drive-strength = <2>;
550 sdc1_rclk_on: sdc1-rclk-on-state {
552 bias-pull-down;
555 sdc1_rclk_off: sdc1-rclk-off-state {
557 bias-pull-down;
560 sdc2_clk_on: sdc2-clk-on-state {
562 drive-strength = <16>;
563 bias-disable;
566 sdc2_clk_off: sdc2-clk-off-state {
568 bias-disable;
569 drive-strength = <2>;
572 sdc2_cmd_on: sdc2-cmd-on-state {
574 bias-pull-up;
575 drive-strength = <10>;
578 sdc2_cmd_off: sdc2-cmd-off-state {
580 bias-pull-up;
581 drive-strength = <2>;
584 sdc2_data_on: sdc2-data-on-state {
586 bias-pull-up;
587 drive-strength = <10>;
590 sdc2_data_off: sdc2-data-off-state {
592 bias-pull-up;
593 drive-strength = <2>;
596 sdc2_cd_on: cd-on-state {
599 drive-strength = <2>;
600 bias-pull-up;
603 sdc2_cd_off: cd-off-state {
606 drive-strength = <2>;
607 bias-disable;
610 gpio_key_default: gpio-key-default-state {
613 drive-strength = <2>;
614 bias-pull-up;
617 i2c_1_default: i2c-1-default-state {
620 drive-strength = <2>;
621 bias-disable;
624 i2c_1_sleep: i2c-1-sleep-state {
627 drive-strength = <2>;
628 bias-disable;
631 i2c_2_default: i2c-2-default-state {
634 drive-strength = <2>;
635 bias-disable;
638 i2c_2_sleep: i2c-2-sleep-state {
641 drive-strength = <2>;
642 bias-disable;
645 i2c_3_default: i2c-3-default-state {
648 drive-strength = <2>;
649 bias-disable;
652 i2c_3_sleep: i2c-3-sleep-state {
655 drive-strength = <2>;
656 bias-disable;
659 i2c_4_default: i2c-4-default-state {
662 drive-strength = <2>;
663 bias-disable;
666 i2c_4_sleep: i2c-4-sleep-state {
669 drive-strength = <2>;
670 bias-disable;
673 i2c_5_default: i2c-5-default-state {
676 drive-strength = <2>;
677 bias-disable;
680 i2c_5_sleep: i2c-5-sleep-state {
683 drive-strength = <2>;
684 bias-disable;
687 i2c_6_default: i2c-6-default-state {
690 drive-strength = <2>;
691 bias-disable;
694 i2c_6_sleep: i2c-6-sleep-state {
697 drive-strength = <2>;
698 bias-disable;
701 i2c_7_default: i2c-7-default-state {
704 drive-strength = <2>;
705 bias-disable;
708 i2c_7_sleep: i2c-7-sleep-state {
711 drive-strength = <2>;
712 bias-disable;
715 i2c_8_default: i2c-8-default-state {
718 drive-strength = <2>;
719 bias-disable;
722 i2c_8_sleep: i2c-8-sleep-state {
725 drive-strength = <2>;
726 bias-disable;
729 wcnss_pin_a: wcnss-active-state {
731 wcss-wlan2-pins {
734 drive-strength = <6>;
735 bias-pull-up;
738 wcss-wlan1-pins {
741 drive-strength = <6>;
742 bias-pull-up;
745 wcss-wlan0-pins {
748 drive-strength = <6>;
749 bias-pull-up;
752 wcss-wlan-pins {
755 drive-strength = <6>;
756 bias-pull-up;
761 gcc: clock-controller@1800000 {
762 compatible = "qcom,gcc-msm8953";
764 #clock-cells = <1>;
765 #reset-cells = <1>;
766 #power-domain-cells = <1>;
773 clock-names = "xo",
782 compatible = "qcom,tcsr-mutex";
784 #hwlock-cells = <1>;
788 compatible = "qcom,tcsr-msm8953", "syscon";
793 compatible = "qcom,tcsr-msm8953", "syscon";
797 mdss: display-subsystem@1a00000 {
802 reg-names = "mdss_phys",
805 power-domains = <&gcc MDSS_GDSC>;
808 interrupt-controller;
809 #interrupt-cells = <1>;
815 clock-names = "iface",
820 #address-cells = <1>;
821 #size-cells = <1>;
826 mdp: display-controller@1a01000 {
827 compatible = "qcom,msm8953-mdp5", "qcom,mdp5";
829 reg-names = "mdp_phys";
831 interrupt-parent = <&mdss>;
834 power-domains = <&gcc MDSS_GDSC>;
840 clock-names = "iface",
848 #address-cells = <1>;
849 #size-cells = <0>;
854 remote-endpoint = <&mdss_dsi0_in>;
861 remote-endpoint = <&mdss_dsi1_in>;
868 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
870 reg-names = "dsi_ctrl";
872 interrupt-parent = <&mdss>;
875 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
877 assigned-clock-parents = <&mdss_dsi0_phy 0>,
886 clock-names = "mdp_core",
895 #address-cells = <1>;
896 #size-cells = <0>;
901 #address-cells = <1>;
902 #size-cells = <0>;
907 remote-endpoint = <&mdp5_intf1_out>;
920 compatible = "qcom,dsi-phy-14nm-8953";
924 reg-names = "dsi_phy",
928 #clock-cells = <1>;
929 #phy-cells = <0>;
932 clock-names = "iface", "ref";
938 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
940 reg-names = "dsi_ctrl";
942 interrupt-parent = <&mdss>;
945 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
947 assigned-clock-parents = <&mdss_dsi1_phy 0>,
956 clock-names = "mdp_core",
968 #address-cells = <1>;
969 #size-cells = <0>;
974 remote-endpoint = <&mdp5_intf2_out>;
987 compatible = "qcom,dsi-phy-14nm-8953";
991 reg-names = "dsi_phy",
995 #clock-cells = <1>;
996 #phy-cells = <0>;
999 clock-names = "iface", "ref";
1006 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1";
1011 clock-names = "iface", "bus";
1013 qcom,iommu-secure-id = <17>;
1015 #address-cells = <1>;
1016 #iommu-cells = <1>;
1017 #size-cells = <1>;
1020 iommu-ctx@14000 {
1021 compatible = "qcom,msm-iommu-v1-ns";
1027 iommu-ctx@15000 {
1028 compatible = "qcom,msm-iommu-v1-ns";
1034 iommu-ctx@16000 {
1035 compatible = "qcom,msm-iommu-v1-ns";
1042 compatible = "qcom,spmi-pmic-arb";
1048 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1049 interrupt-names = "periph_irq";
1053 interrupt-controller;
1055 #interrupt-cells = <4>;
1056 #address-cells = <2>;
1057 #size-cells = <0>;
1061 compatible = "qcom,msm8953-mss-pil";
1064 reg-names = "qdsp6", "rmb";
1066 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1071 interrupt-names = "wdog", "fatal", "ready",
1072 "handover", "stop-ack";
1074 power-domains = <&rpmpd MSM8953_VDDCX>,
1077 power-domain-names = "cx", "mx","mss";
1083 clock-names = "iface", "bus", "mem", "xo";
1085 qcom,smem-states = <&smp2p_modem_out 0>;
1086 qcom,smem-state-names = "stop";
1089 reset-names = "mss_restart";
1091 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1096 memory-region = <&mba_mem>;
1100 memory-region = <&mpss_mem>;
1103 smd-edge {
1106 qcom,smd-edge = <0>;
1108 qcom,remote-pid = <1>;
1115 compatible = "qcom,msm8953-dwc3", "qcom,dwc3";
1117 #address-cells = <1>;
1118 #size-cells = <1>;
1123 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1130 clock-names = "cfg_noc",
1136 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1138 assigned-clock-rates = <19200000>, <133330000>;
1140 power-domains = <&gcc USB30_GDSC>;
1142 qcom,select-utmi-as-pipe-clk;
1151 phy-names = "usb2-phy";
1153 snps,usb2-gadget-lpm-disable;
1154 snps,dis-u1-entry-quirk;
1155 snps,dis-u2-entry-quirk;
1156 snps,is-utmi-l1-suspend;
1157 snps,hird-threshold = /bits/ 8 <0x00>;
1159 maximum-speed = "high-speed";
1164 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
1167 reg-names = "hc", "core";
1171 interrupt-names = "hc_irq", "pwr_irq";
1176 clock-names = "iface", "core", "xo";
1178 power-domains = <&rpmpd MSM8953_VDDCX>;
1179 operating-points-v2 = <&sdhc1_opp_table>;
1181 pinctrl-names = "default", "sleep";
1182 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
1183 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
1185 mmc-hs400-1_8v;
1186 mmc-hs200-1_8v;
1187 mmc-ddr-1_8v;
1188 bus-width = <8>;
1189 non-removable;
1193 sdhc1_opp_table: opp-table-sdhc1 {
1194 compatible = "operating-points-v2";
1196 opp-25000000 {
1197 opp-hz = /bits/ 64 <25000000>;
1198 required-opps = <&rpmpd_opp_low_svs>;
1201 opp-50000000 {
1202 opp-hz = /bits/ 64 <50000000>;
1203 required-opps = <&rpmpd_opp_svs>;
1206 opp-100000000 {
1207 opp-hz = /bits/ 64 <100000000>;
1208 required-opps = <&rpmpd_opp_svs>;
1211 opp-192000000 {
1212 opp-hz = /bits/ 64 <192000000>;
1213 required-opps = <&rpmpd_opp_nom>;
1216 opp-384000000 {
1217 opp-hz = /bits/ 64 <384000000>;
1218 required-opps = <&rpmpd_opp_nom>;
1224 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
1227 reg-names = "hc", "core";
1231 interrupt-names = "hc_irq", "pwr_irq";
1236 clock-names = "iface", "core", "xo";
1238 power-domains = <&rpmpd MSM8953_VDDCX>;
1239 operating-points-v2 = <&sdhc2_opp_table>;
1241 pinctrl-names = "default", "sleep";
1242 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
1243 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
1245 bus-width = <4>;
1249 sdhc2_opp_table: opp-table-sdhc2 {
1250 compatible = "operating-points-v2";
1252 opp-25000000 {
1253 opp-hz = /bits/ 64 <25000000>;
1254 required-opps = <&rpmpd_opp_low_svs>;
1257 opp-50000000 {
1258 opp-hz = /bits/ 64 <50000000>;
1259 required-opps = <&rpmpd_opp_svs>;
1262 opp-100000000 {
1263 opp-hz = /bits/ 64 <100000000>;
1264 required-opps = <&rpmpd_opp_svs>;
1267 opp-177770000 {
1268 opp-hz = /bits/ 64 <177770000>;
1269 required-opps = <&rpmpd_opp_nom>;
1272 opp-200000000 {
1273 opp-hz = /bits/ 64 <200000000>;
1274 required-opps = <&rpmpd_opp_nom>;
1279 blsp1_dma: dma-controller@7884000 {
1280 compatible = "qcom,bam-v1.7.0";
1284 clock-names = "bam_clk";
1285 num-channels = <12>;
1286 #dma-cells = <1>;
1288 qcom,num-ees = <4>;
1289 qcom,controlled-remotely;
1293 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1298 clock-names = "core", "iface";
1304 compatible = "qcom,i2c-qup-v2.2.1";
1307 clock-names = "core", "iface";
1311 dma-names = "tx", "rx";
1313 pinctrl-names = "default", "sleep";
1314 pinctrl-0 = <&i2c_1_default>;
1315 pinctrl-1 = <&i2c_1_sleep>;
1317 #address-cells = <1>;
1318 #size-cells = <0>;
1324 compatible = "qcom,i2c-qup-v2.2.1";
1327 clock-names = "core", "iface";
1331 dma-names = "tx", "rx";
1333 pinctrl-names = "default", "sleep";
1334 pinctrl-0 = <&i2c_2_default>;
1335 pinctrl-1 = <&i2c_2_sleep>;
1337 #address-cells = <1>;
1338 #size-cells = <0>;
1344 compatible = "qcom,i2c-qup-v2.2.1";
1347 clock-names = "core", "iface";
1351 dma-names = "tx", "rx";
1353 pinctrl-names = "default", "sleep";
1354 pinctrl-0 = <&i2c_3_default>;
1355 pinctrl-1 = <&i2c_3_sleep>;
1357 #address-cells = <1>;
1358 #size-cells = <0>;
1364 compatible = "qcom,i2c-qup-v2.2.1";
1367 clock-names = "core", "iface";
1371 dma-names = "tx", "rx";
1373 pinctrl-names = "default", "sleep";
1374 pinctrl-0 = <&i2c_4_default>;
1375 pinctrl-1 = <&i2c_4_sleep>;
1377 #address-cells = <1>;
1378 #size-cells = <0>;
1383 blsp2_dma: dma-controller@7ac4000 {
1384 compatible = "qcom,bam-v1.7.0";
1388 clock-names = "bam_clk";
1389 num-channels = <12>;
1390 #dma-cells = <1>;
1392 qcom,num-ees = <4>;
1393 qcom,controlled-remotely;
1397 compatible = "qcom,i2c-qup-v2.2.1";
1400 clock-names = "core", "iface";
1404 dma-names = "tx", "rx";
1406 pinctrl-names = "default", "sleep";
1407 pinctrl-0 = <&i2c_5_default>;
1408 pinctrl-1 = <&i2c_5_sleep>;
1410 #address-cells = <1>;
1411 #size-cells = <0>;
1417 compatible = "qcom,i2c-qup-v2.2.1";
1420 clock-names = "core", "iface";
1424 dma-names = "tx", "rx";
1426 pinctrl-names = "default", "sleep";
1427 pinctrl-0 = <&i2c_6_default>;
1428 pinctrl-1 = <&i2c_6_sleep>;
1430 #address-cells = <1>;
1431 #size-cells = <0>;
1437 compatible = "qcom,i2c-qup-v2.2.1";
1440 clock-names = "core", "iface";
1444 dma-names = "tx", "rx";
1446 pinctrl-names = "default", "sleep";
1447 pinctrl-0 = <&i2c_7_default>;
1448 pinctrl-1 = <&i2c_7_sleep>;
1450 #address-cells = <1>;
1451 #size-cells = <0>;
1457 compatible = "qcom,i2c-qup-v2.2.1";
1460 clock-names = "core", "iface";
1464 dma-names = "tx", "rx";
1466 pinctrl-names = "default", "sleep";
1467 pinctrl-0 = <&i2c_8_default>;
1468 pinctrl-1 = <&i2c_8_sleep>;
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1477 compatible = "qcom,pronto-v3-pil", "qcom,pronto";
1479 reg-names = "ccu", "dxe", "pmu";
1481 memory-region = <&wcnss_fw_mem>;
1483 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1488 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1490 power-domains = <&rpmpd MSM8953_VDDCX>,
1492 power-domain-names = "cx", "mx";
1494 qcom,smem-states = <&smp2p_wcnss_out 0>;
1495 qcom,smem-state-names = "stop";
1497 pinctrl-names = "default";
1498 pinctrl-0 = <&wcnss_pin_a>;
1503 /* Separate chip, compatible is board-specific */
1505 clock-names = "xo";
1508 smd-edge {
1512 qcom,smd-edge = <6>;
1513 qcom,remote-pid = <4>;
1519 qcom,smd-channels = "WCNSS_CTRL";
1524 compatible = "qcom,wcnss-bt";
1528 compatible = "qcom,wcnss-wlan";
1532 interrupt-names = "tx", "rx";
1534 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1535 qcom,smem-state-names = "tx-enable",
1536 "tx-rings-empty";
1542 intc: interrupt-controller@b000000 {
1543 compatible = "qcom,msm-qgic2";
1544 interrupt-controller;
1545 #interrupt-cells = <3>;
1550 compatible = "qcom,msm8953-apcs-kpss-global", "syscon";
1552 #mbox-cells = <1>;
1556 compatible = "arm,armv7-timer-mem";
1558 #address-cells = <1>;
1559 #size-cells = <1>;
1563 frame-number = <0>;
1571 frame-number = <1>;
1578 frame-number = <2>;
1585 frame-number = <3>;
1592 frame-number = <4>;
1599 frame-number = <5>;
1606 frame-number = <6>;
1614 compatible = "qcom,msm8953-adsp-pil";
1617 interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>,
1622 interrupt-names = "wdog", "fatal", "ready",
1623 "handover", "stop-ack";
1625 clock-names = "xo";
1627 power-domains = <&rpmpd MSM8953_VDDCX>;
1628 power-domain-names = "cx";
1630 memory-region = <&adsp_fw_mem>;
1632 qcom,smem-states = <&smp2p_adsp_out 0>;
1633 qcom,smem-state-names = "stop";
1637 smd-edge {
1642 qcom,smd-edge = <1>;
1643 qcom,remote-pid = <2>;
1646 compatible = "qcom,apr-v2";
1647 qcom,smd-channels = "apr_audio_svc";
1648 qcom,apr-domain = <APR_DOMAIN_ADSP>;
1649 #address-cells = <1>;
1650 #size-cells = <0>;
1661 compatible = "qcom,q6afe-dais";
1662 #address-cells = <1>;
1663 #size-cells = <0>;
1664 #sound-dai-cells = <1>;
1668 qcom,sd-lines = <0 1>;
1672 qcom,sd-lines = <0 1>;
1676 qcom,sd-lines = <0>;
1680 q6afecc: clock-controller {
1681 compatible = "qcom,q6afe-clocks";
1682 #clock-cells = <2>;
1690 compatible = "qcom,q6asm-dais";
1691 #address-cells = <1>;
1692 #size-cells = <0>;
1693 #sound-dai-cells = <1>;
1710 is-compress-dai;
1719 compatible = "qcom,q6adm-routing";
1720 #sound-dai-cells = <0>;
1728 thermal-zones {
1729 cpu0-thermal {
1730 polling-delay-passive = <250>;
1731 polling-delay = <1000>;
1732 thermal-sensors = <&tsens0 9>;
1734 cpu0_alert: trip-point0 {
1745 cooling-maps {
1748 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1752 cpu1-thermal {
1753 polling-delay-passive = <250>;
1754 polling-delay = <1000>;
1755 thermal-sensors = <&tsens0 10>;
1757 cpu1_alert: trip-point0 {
1768 cooling-maps {
1771 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1775 cpu2-thermal {
1776 polling-delay-passive = <250>;
1777 polling-delay = <1000>;
1778 thermal-sensors = <&tsens0 11>;
1780 cpu2_alert: trip-point0 {
1791 cooling-maps {
1794 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1798 cpu3-thermal {
1799 polling-delay-passive = <250>;
1800 polling-delay = <1000>;
1801 thermal-sensors = <&tsens0 12>;
1803 cpu3_alert: trip-point0 {
1814 cooling-maps {
1817 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1821 cpu4-thermal {
1822 polling-delay-passive = <250>;
1823 polling-delay = <1000>;
1824 thermal-sensors = <&tsens0 4>;
1826 cpu4_alert: trip-point0 {
1837 cooling-maps {
1840 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1844 cpu5-thermal {
1845 polling-delay-passive = <250>;
1846 polling-delay = <1000>;
1847 thermal-sensors = <&tsens0 5>;
1849 cpu5_alert: trip-point0 {
1860 cooling-maps {
1863 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1867 cpu6-thermal {
1868 polling-delay-passive = <250>;
1869 polling-delay = <1000>;
1870 thermal-sensors = <&tsens0 6>;
1872 cpu6_alert: trip-point0 {
1883 cooling-maps {
1886 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1890 cpu7-thermal {
1891 polling-delay-passive = <250>;
1892 polling-delay = <1000>;
1893 thermal-sensors = <&tsens0 7>;
1895 cpu7_alert: trip-point0 {
1906 cooling-maps {
1909 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1916 compatible = "arm,armv8-timer";