Lines Matching +full:tsens +full:- +full:v0_1
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8939.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&intc>;
19 * Stock LK wants address-cells/size-cells = 2
21 * hence the disparity between top-level and /soc below.
23 #address-cells = <2>;
24 #size-cells = <2>;
27 xo_board: xo-board {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <19200000>;
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <32768>;
41 #address-cells = <1>;
42 #size-cells = <0>;
45 compatible = "arm,cortex-a53";
47 enable-method = "spin-table";
49 next-level-cache = <&L2_1>;
52 cpu-idle-states = <&CPU_SLEEP_0>;
54 #cooling-cells = <2>;
55 L2_1: l2-cache {
57 cache-level = <2>;
58 cache-unified;
63 compatible = "arm,cortex-a53";
65 enable-method = "spin-table";
67 next-level-cache = <&L2_1>;
70 cpu-idle-states = <&CPU_SLEEP_0>;
72 #cooling-cells = <2>;
76 compatible = "arm,cortex-a53";
78 enable-method = "spin-table";
80 next-level-cache = <&L2_1>;
83 cpu-idle-states = <&CPU_SLEEP_0>;
85 #cooling-cells = <2>;
89 compatible = "arm,cortex-a53";
91 enable-method = "spin-table";
93 next-level-cache = <&L2_1>;
96 cpu-idle-states = <&CPU_SLEEP_0>;
98 #cooling-cells = <2>;
102 compatible = "arm,cortex-a53";
104 enable-method = "spin-table";
108 cpu-idle-states = <&CPU_SLEEP_0>;
110 #cooling-cells = <2>;
111 next-level-cache = <&L2_0>;
112 L2_0: l2-cache {
114 cache-level = <2>;
115 cache-unified;
120 compatible = "arm,cortex-a53";
122 enable-method = "spin-table";
124 next-level-cache = <&L2_0>;
127 cpu-idle-states = <&CPU_SLEEP_0>;
129 #cooling-cells = <2>;
133 compatible = "arm,cortex-a53";
135 enable-method = "spin-table";
137 next-level-cache = <&L2_0>;
140 cpu-idle-states = <&CPU_SLEEP_0>;
142 #cooling-cells = <2>;
146 compatible = "arm,cortex-a53";
148 enable-method = "spin-table";
150 next-level-cache = <&L2_0>;
153 cpu-idle-states = <&CPU_SLEEP_0>;
155 #cooling-cells = <2>;
158 idle-states {
159 CPU_SLEEP_0: cpu-sleep-0 {
160 compatible = "arm,idle-state";
161 entry-latency-us = <130>;
162 exit-latency-us = <150>;
163 min-residency-us = <2000>;
164 local-timer-stop;
171 * consisting of two clusters of four ARM Cortex-A53s each. The
172 * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs
173 * at 1.5-1.7GHz.
175 * The enable method used here is spin-table which presupposes use
177 * spin-table, the downstream non-psci/non-spin-table method that
180 cpu-map {
223 compatible = "qcom,scm-msm8916", "qcom,scm";
227 clock-names = "core", "bus", "iface";
228 #reset-cells = <1>;
230 qcom,dload-mode = <&tcsr 0x6100>;
241 compatible = "arm,cortex-a53-pmu";
246 compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc";
248 smd-edge {
251 qcom,smd-edge = <15>;
253 rpm_requests: rpm-requests {
254 compatible = "qcom,rpm-msm8936";
255 qcom,smd-channels = "rpm_requests";
257 rpmcc: clock-controller {
258 compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
259 #clock-cells = <1>;
260 clock-names = "xo";
264 rpmpd: power-controller {
265 compatible = "qcom,msm8939-rpmpd";
266 #power-domain-cells = <1>;
267 operating-points-v2 = <&rpmpd_opp_table>;
269 rpmpd_opp_table: opp-table {
270 compatible = "operating-points-v2";
273 opp-level = <1>;
277 opp-level = <2>;
281 opp-level = <3>;
285 opp-level = <4>;
289 opp-level = <5>;
293 opp-level = <6>;
301 reserved-memory {
302 #address-cells = <2>;
303 #size-cells = <2>;
306 tz-apps@86000000 {
308 no-map;
314 no-map;
317 qcom,rpm-msg-ram = <&rpm_msg_ram>;
322 no-map;
327 no-map;
332 no-map;
336 compatible = "qcom,rmtfs-mem";
338 no-map;
340 qcom,client-id = <1>;
345 no-map;
350 no-map;
355 no-map;
360 no-map;
365 no-map;
369 smp2p-hexagon {
377 qcom,local-pid = <0>;
378 qcom,remote-pid = <1>;
380 hexagon_smp2p_out: master-kernel {
381 qcom,entry-name = "master-kernel";
383 #qcom,smem-state-cells = <1>;
386 hexagon_smp2p_in: slave-kernel {
387 qcom,entry-name = "slave-kernel";
389 interrupt-controller;
390 #interrupt-cells = <2>;
394 smp2p-wcnss {
402 qcom,local-pid = <0>;
403 qcom,remote-pid = <4>;
405 wcnss_smp2p_in: slave-kernel {
406 qcom,entry-name = "slave-kernel";
408 interrupt-controller;
409 #interrupt-cells = <2>;
412 wcnss_smp2p_out: master-kernel {
413 qcom,entry-name = "master-kernel";
415 #qcom,smem-state-cells = <1>;
422 #address-cells = <1>;
423 #size-cells = <0>;
425 qcom,ipc-1 = <&apcs1_mbox 8 13>;
426 qcom,ipc-3 = <&apcs1_mbox 8 19>;
431 #qcom,smem-state-cells = <1>;
438 interrupt-controller;
439 #interrupt-cells = <2>;
446 interrupt-controller;
447 #interrupt-cells = <2>;
452 compatible = "simple-bus";
453 #address-cells = <1>;
454 #size-cells = <1>;
461 clock-names = "core";
465 compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
467 #address-cells = <1>;
468 #size-cells = <1>;
475 tsens_s6_p1: s6-p1@a1 {
480 tsens_s6_p2: s6-p2@a1 {
485 tsens_s7_p1: s7-p1@a2 {
490 tsens_s7_p2: s7-p2@a3 {
495 tsens_s8_p1: s8-p1@a4 {
500 tsens_s8_p2: s8-p2@a4 {
505 tsens_s9_p1: s9-p1@a5 {
510 tsens_s9_p2: s9-p2@a6 {
525 tsens_s0_p1: s0-p1@d0 {
530 tsens_s0_p2: s0-p1@d1 {
535 tsens_s1_p1: s1-p1@d1 {
540 tsens_s1_p2: s1-p2@d2 {
545 tsens_s2_p1: s2-p1@d3 {
550 tsens_s2_p2: s2-p2@d4 {
555 tsens_s3_p1: s3-p1@d4 {
560 tsens_s3_p2: s3-p2@d5 {
565 tsens_s5_p1: s5-p1@d6 {
570 tsens_s5_p2: s5-p2@d7 {
577 compatible = "qcom,rpm-msg-ram";
582 compatible = "qcom,msm8939-bimc";
584 clock-names = "bus", "bus_a";
587 #interconnect-cells = <1>;
590 tsens: thermal-sensor@4a9000 { label
591 compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1";
594 nvmem-cells = <&tsens_mode>,
605 nvmem-cell-names = "mode",
618 interrupt-names = "uplow";
619 #thermal-sensor-cells = <1>;
628 compatible = "qcom,msm8939-pcnoc";
630 clock-names = "bus", "bus_a";
633 #interconnect-cells = <1>;
637 compatible = "qcom,msm8939-snoc";
639 clock-names = "bus", "bus_a";
642 #interconnect-cells = <1>;
644 snoc_mm: interconnect-snoc {
645 compatible = "qcom,msm8939-snoc-mm";
646 clock-names = "bus", "bus_a";
649 #interconnect-cells = <1>;
654 compatible = "qcom,msm8916-pinctrl";
657 gpio-controller;
658 gpio-ranges = <&tlmm 0 0 122>;
659 #gpio-cells = <2>;
660 interrupt-controller;
661 #interrupt-cells = <2>;
663 blsp_i2c1_default: blsp-i2c1-default-state {
666 drive-strength = <2>;
667 bias-disable;
670 blsp_i2c1_sleep: blsp-i2c1-sleep-state {
673 drive-strength = <2>;
674 bias-disable;
677 blsp_i2c2_default: blsp-i2c2-default-state {
680 drive-strength = <2>;
681 bias-disable;
684 blsp_i2c2_sleep: blsp-i2c2-sleep-state {
687 drive-strength = <2>;
688 bias-disable;
691 blsp_i2c3_default: blsp-i2c3-default-state {
694 drive-strength = <2>;
695 bias-disable;
698 blsp_i2c3_sleep: blsp-i2c3-sleep-state {
701 drive-strength = <2>;
702 bias-disable;
705 blsp_i2c4_default: blsp-i2c4-default-state {
708 drive-strength = <2>;
709 bias-disable;
712 blsp_i2c4_sleep: blsp-i2c4-sleep-state {
715 drive-strength = <2>;
716 bias-disable;
719 blsp_i2c5_default: blsp-i2c5-default-state {
722 drive-strength = <2>;
723 bias-disable;
726 blsp_i2c5_sleep: blsp-i2c5-sleep-state {
729 drive-strength = <2>;
730 bias-disable;
733 blsp_i2c6_default: blsp-i2c6-default-state {
736 drive-strength = <2>;
737 bias-disable;
740 blsp_i2c6_sleep: blsp-i2c6-sleep-state {
743 drive-strength = <2>;
744 bias-disable;
747 blsp_spi1_default: blsp-spi1-default-state {
748 spi-pins {
751 drive-strength = <12>;
752 bias-disable;
755 cs-pins {
758 drive-strength = <16>;
759 bias-disable;
760 output-high;
764 blsp_spi1_sleep: blsp-spi1-sleep-state {
767 drive-strength = <2>;
768 bias-pull-down;
771 blsp_spi2_default: blsp-spi2-default-state {
772 spi-pins {
775 drive-strength = <12>;
776 bias-disable;
779 cs-pins {
782 drive-strength = <16>;
783 bias-disable;
784 output-high;
788 blsp_spi2_sleep: blsp-spi2-sleep-state {
791 drive-strength = <2>;
792 bias-pull-down;
795 blsp_spi3_default: blsp-spi3-default-state {
796 spi-pins {
799 drive-strength = <12>;
800 bias-disable;
803 cs-pins {
806 drive-strength = <16>;
807 bias-disable;
808 output-high;
812 blsp_spi3_sleep: blsp-spi3-sleep-state {
815 drive-strength = <2>;
816 bias-pull-down;
819 blsp_spi4_default: blsp-spi4-default-state {
820 spi-pins {
823 drive-strength = <12>;
824 bias-disable;
827 cs-pins {
830 drive-strength = <16>;
831 bias-disable;
832 output-high;
836 blsp_spi4_sleep: blsp-spi4-sleep-state {
839 drive-strength = <2>;
840 bias-pull-down;
843 blsp_spi5_default: blsp-spi5-default-state {
844 spi-pins {
847 drive-strength = <12>;
848 bias-disable;
851 cs-pins {
854 drive-strength = <16>;
855 bias-disable;
856 output-high;
860 blsp_spi5_sleep: blsp-spi5-sleep-state {
863 drive-strength = <2>;
864 bias-pull-down;
867 blsp_spi6_default: blsp-spi6-default-state {
868 spi-pins {
871 drive-strength = <12>;
872 bias-disable;
875 cs-pins {
878 drive-strength = <16>;
879 bias-disable;
880 output-high;
884 blsp_spi6_sleep: blsp-spi6-sleep-state {
887 drive-strength = <2>;
888 bias-pull-down;
891 blsp_uart1_default: blsp-uart1-default-state {
894 drive-strength = <16>;
895 bias-disable;
898 blsp_uart1_sleep: blsp-uart1-sleep-state {
901 drive-strength = <2>;
902 bias-pull-down;
905 blsp_uart2_default: blsp-uart2-default-state {
908 drive-strength = <16>;
909 bias-disable;
912 blsp_uart2_sleep: blsp-uart2-sleep-state {
915 drive-strength = <2>;
916 bias-pull-down;
919 camera_front_default: camera-front-default-state {
920 pwdn-pins {
923 drive-strength = <16>;
924 bias-disable;
927 rst-pins {
930 drive-strength = <16>;
931 bias-disable;
934 mclk1-pins {
937 drive-strength = <16>;
938 bias-disable;
942 camera_rear_default: camera-rear-default-state {
943 pwdn-pins {
946 drive-strength = <16>;
947 bias-disable;
950 rst-pins {
953 drive-strength = <16>;
954 bias-disable;
957 mclk0-pins {
960 drive-strength = <16>;
961 bias-disable;
965 cci0_default: cci0-default-state {
968 drive-strength = <16>;
969 bias-disable;
972 cdc_dmic_default: cdc-dmic-default-state {
973 clk-pins {
976 drive-strength = <8>;
979 data-pins {
982 drive-strength = <8>;
986 cdc_dmic_sleep: cdc-dmic-sleep-state {
987 clk-pins {
990 drive-strength = <2>;
991 bias-disable;
994 data-pins {
997 drive-strength = <2>;
998 bias-disable;
1002 cdc_pdm_default: cdc-pdm-default-state {
1006 drive-strength = <8>;
1007 bias-disable;
1010 cdc_pdm_sleep: cdc-pdm-sleep-state {
1014 drive-strength = <2>;
1015 bias-pull-down;
1018 pri_mi2s_default: mi2s-pri-default-state {
1021 drive-strength = <8>;
1022 bias-disable;
1025 pri_mi2s_sleep: mi2s-pri-sleep-state {
1028 drive-strength = <2>;
1029 bias-disable;
1032 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1035 drive-strength = <8>;
1036 bias-disable;
1039 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1042 drive-strength = <2>;
1043 bias-disable;
1046 pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1049 drive-strength = <8>;
1050 bias-disable;
1053 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1056 drive-strength = <2>;
1057 bias-disable;
1060 sec_mi2s_default: mi2s-sec-default-state {
1063 drive-strength = <8>;
1064 bias-disable;
1067 sec_mi2s_sleep: mi2s-sec-sleep-state {
1070 drive-strength = <2>;
1071 bias-disable;
1074 sdc1_default: sdc1-default-state {
1075 clk-pins {
1077 bias-disable;
1078 drive-strength = <16>;
1081 cmd-pins {
1083 bias-pull-up;
1084 drive-strength = <10>;
1087 data-pins {
1089 bias-pull-up;
1090 drive-strength = <10>;
1094 sdc1_sleep: sdc1-sleep-state {
1095 clk-pins {
1097 bias-disable;
1098 drive-strength = <2>;
1101 cmd-pins {
1103 bias-pull-up;
1104 drive-strength = <2>;
1107 data-pins {
1109 bias-pull-up;
1110 drive-strength = <2>;
1114 sdc2_default: sdc2-default-state {
1115 clk-pins {
1117 bias-disable;
1118 drive-strength = <16>;
1121 cmd-pins {
1123 bias-pull-up;
1124 drive-strength = <10>;
1127 data-pins {
1129 bias-pull-up;
1130 drive-strength = <10>;
1134 sdc2_sleep: sdc2-sleep-state {
1135 clk-pins {
1137 bias-disable;
1138 drive-strength = <2>;
1141 cmd-pins {
1143 bias-pull-up;
1144 drive-strength = <2>;
1147 data-pins {
1149 bias-pull-up;
1150 drive-strength = <2>;
1154 wcss_wlan_default: wcss-wlan-default-state {
1157 drive-strength = <6>;
1158 bias-pull-up;
1162 gcc: clock-controller@1800000 {
1163 compatible = "qcom,gcc-msm8939";
1172 clock-names = "xo",
1179 #clock-cells = <1>;
1180 #reset-cells = <1>;
1181 #power-domain-cells = <1>;
1185 compatible = "qcom,tcsr-mutex";
1187 #hwlock-cells = <1>;
1191 compatible = "qcom,tcsr-msm8916", "syscon";
1195 mdss: display-subsystem@1a00000 {
1199 reg-names = "mdss_phys", "vbif_phys";
1202 interrupt-controller;
1207 clock-names = "iface",
1211 power-domains = <&gcc MDSS_GDSC>;
1213 #address-cells = <1>;
1214 #size-cells = <1>;
1215 #interrupt-cells = <1>;
1220 mdss_mdp: display-controller@1a01000 {
1223 reg-names = "mdp_phys";
1225 interrupt-parent = <&mdss>;
1232 clock-names = "iface",
1241 interconnect-names = "mdp0-mem", "mdp1-mem";
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1250 remote-endpoint = <&mdss_dsi0_in>;
1257 remote-endpoint = <&mdss_dsi1_in>;
1264 compatible = "qcom,msm8916-dsi-ctrl",
1265 "qcom,mdss-dsi-ctrl";
1267 reg-names = "dsi_ctrl";
1269 interrupt-parent = <&mdss>;
1278 clock-names = "mdp_core",
1284 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1286 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1296 #address-cells = <1>;
1297 #size-cells = <0>;
1302 remote-endpoint = <&mdss_mdp_intf1_out>;
1315 compatible = "qcom,dsi-phy-28nm-lp";
1319 reg-names = "dsi_pll",
1325 clock-names = "iface", "ref";
1327 #clock-cells = <1>;
1328 #phy-cells = <0>;
1333 compatible = "qcom,msm8916-dsi-ctrl",
1334 "qcom,mdss-dsi-ctrl";
1336 reg-names = "dsi_ctrl";
1338 interrupt-parent = <&mdss>;
1347 clock-names = "mdp_core",
1353 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
1355 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1361 #address-cells = <1>;
1362 #size-cells = <0>;
1367 remote-endpoint = <&mdss_mdp_intf2_out>;
1380 compatible = "qcom,dsi-phy-28nm-lp";
1384 reg-names = "dsi_pll",
1390 clock-names = "iface", "ref";
1392 #clock-cells = <1>;
1393 #phy-cells = <0>;
1399 compatible = "qcom,adreno-405.0", "qcom,adreno";
1401 reg-names = "kgsl_3d0_reg_memory";
1403 interrupt-names = "kgsl_3d0_irq";
1404 clock-names = "core",
1418 power-domains = <&gcc OXILI_GDSC>;
1419 operating-points-v2 = <&opp_table>;
1422 opp_table: opp-table {
1423 compatible = "operating-points-v2";
1425 opp-550000000 {
1426 opp-hz = /bits/ 64 <550000000>;
1429 opp-465000000 {
1430 opp-hz = /bits/ 64 <465000000>;
1433 opp-400000000 {
1434 opp-hz = /bits/ 64 <400000000>;
1437 opp-220000000 {
1438 opp-hz = /bits/ 64 <220000000>;
1441 opp-19200000 {
1442 opp-hz = /bits/ 64 <19200000>;
1448 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1453 clock-names = "iface", "bus";
1454 #address-cells = <1>;
1455 #size-cells = <1>;
1456 #iommu-cells = <1>;
1457 qcom,iommu-secure-id = <17>;
1460 iommu-ctx@4000 {
1461 compatible = "qcom,msm-iommu-v1-ns";
1467 iommu-ctx@5000 {
1468 compatible = "qcom,msm-iommu-v1-sec";
1475 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1480 clock-names = "iface", "bus", "tbu";
1481 #address-cells = <1>;
1482 #size-cells = <1>;
1483 #iommu-cells = <1>;
1484 qcom,iommu-secure-id = <18>;
1487 iommu-ctx@1000 {
1488 compatible = "qcom,msm-iommu-v1-ns";
1494 iommu-ctx@2000 {
1495 compatible = "qcom,msm-iommu-v1-ns";
1502 compatible = "qcom,spmi-pmic-arb";
1508 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1509 interrupt-names = "periph_irq";
1513 #address-cells = <2>;
1514 #size-cells = <0>;
1515 interrupt-controller;
1516 #interrupt-cells = <4>;
1520 compatible = "qcom,msm8916-mss-pil";
1522 reg-names = "qdsp6", "rmb";
1523 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1528 interrupt-names = "wdog",
1532 "stop-ack";
1537 clock-names = "iface",
1541 power-domains = <&rpmpd MSM8939_VDDMDCX>,
1543 power-domain-names = "cx", "mx";
1544 qcom,smem-states = <&hexagon_smp2p_out 0>;
1545 qcom,smem-state-names = "stop";
1547 reset-names = "mss_restart";
1548 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1552 memory-region = <&mba_mem>;
1556 memory-region = <&mpss_mem>;
1559 smd-edge {
1562 qcom,smd-edge = <0>;
1564 qcom,remote-pid = <1>;
1571 compatible = "qcom,apq8016-sbc-sndcard";
1574 reg-names = "mic-iomux", "spkr-iomux";
1578 lpass: audio-controller@7708000 {
1579 compatible = "qcom,apq8016-lpass-cpu";
1581 reg-names = "lpass-lpaif";
1583 interrupt-names = "lpass-irq-lpaif";
1591 clock-names = "ahbix-clk",
1592 "mi2s-bit-clk0",
1593 "mi2s-bit-clk1",
1594 "mi2s-bit-clk2",
1595 "mi2s-bit-clk3",
1596 "pcnoc-mport-clk",
1597 "pcnoc-sway-clk";
1598 #sound-dai-cells = <1>;
1599 #address-cells = <1>;
1600 #size-cells = <0>;
1604 lpass_codec: audio-codec@771c000 {
1605 compatible = "qcom,msm8916-wcd-digital-codec";
1609 clock-names = "ahbix-clk", "mclk";
1610 #sound-dai-cells = <1>;
1615 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1617 reg-names = "hc", "core";
1621 interrupt-names = "hc_irq", "pwr_irq";
1625 clock-names = "iface", "core", "xo";
1627 pinctrl-0 = <&sdc1_default>;
1628 pinctrl-1 = <&sdc1_sleep>;
1629 pinctrl-names = "default", "sleep";
1630 mmc-ddr-1_8v;
1631 bus-width = <8>;
1632 non-removable;
1637 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1639 reg-names = "hc", "core";
1643 interrupt-names = "hc_irq", "pwr_irq";
1647 clock-names = "iface", "core", "xo";
1649 pinctrl-0 = <&sdc2_default>;
1650 pinctrl-1 = <&sdc2_sleep>;
1651 pinctrl-names = "default", "sleep";
1652 bus-width = <4>;
1656 blsp_dma: dma-controller@7884000 {
1657 compatible = "qcom,bam-v1.7.0";
1661 clock-names = "bam_clk";
1662 #dma-cells = <1>;
1664 qcom,controlled-remotely;
1668 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1672 clock-names = "core", "iface";
1674 dma-names = "tx", "rx";
1675 pinctrl-0 = <&blsp_uart1_default>;
1676 pinctrl-1 = <&blsp_uart1_sleep>;
1677 pinctrl-names = "default", "sleep";
1682 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1686 clock-names = "core", "iface";
1688 dma-names = "tx", "rx";
1689 pinctrl-0 = <&blsp_uart2_default>;
1690 pinctrl-1 = <&blsp_uart2_sleep>;
1691 pinctrl-names = "default", "sleep";
1696 compatible = "qcom,i2c-qup-v2.2.1";
1701 clock-names = "core", "iface";
1703 dma-names = "tx", "rx";
1704 pinctrl-0 = <&blsp_i2c1_default>;
1705 pinctrl-1 = <&blsp_i2c1_sleep>;
1706 pinctrl-names = "default", "sleep";
1707 #address-cells = <1>;
1708 #size-cells = <0>;
1713 compatible = "qcom,spi-qup-v2.2.1";
1718 clock-names = "core", "iface";
1720 dma-names = "tx", "rx";
1721 pinctrl-0 = <&blsp_spi1_default>;
1722 pinctrl-1 = <&blsp_spi1_sleep>;
1723 pinctrl-names = "default", "sleep";
1724 #address-cells = <1>;
1725 #size-cells = <0>;
1730 compatible = "qcom,i2c-qup-v2.2.1";
1735 clock-names = "core", "iface";
1737 dma-names = "tx", "rx";
1738 pinctrl-0 = <&blsp_i2c2_default>;
1739 pinctrl-1 = <&blsp_i2c2_sleep>;
1740 pinctrl-names = "default", "sleep";
1741 #address-cells = <1>;
1742 #size-cells = <0>;
1747 compatible = "qcom,spi-qup-v2.2.1";
1752 clock-names = "core", "iface";
1754 dma-names = "tx", "rx";
1755 pinctrl-0 = <&blsp_spi2_default>;
1756 pinctrl-1 = <&blsp_spi2_sleep>;
1757 pinctrl-names = "default", "sleep";
1758 #address-cells = <1>;
1759 #size-cells = <0>;
1764 compatible = "qcom,i2c-qup-v2.2.1";
1769 clock-names = "core", "iface";
1771 dma-names = "tx", "rx";
1772 pinctrl-0 = <&blsp_i2c3_default>;
1773 pinctrl-1 = <&blsp_i2c3_sleep>;
1774 pinctrl-names = "default", "sleep";
1775 #address-cells = <1>;
1776 #size-cells = <0>;
1781 compatible = "qcom,spi-qup-v2.2.1";
1786 clock-names = "core", "iface";
1788 dma-names = "tx", "rx";
1789 pinctrl-0 = <&blsp_spi3_default>;
1790 pinctrl-1 = <&blsp_spi3_sleep>;
1791 pinctrl-names = "default", "sleep";
1792 #address-cells = <1>;
1793 #size-cells = <0>;
1798 compatible = "qcom,i2c-qup-v2.2.1";
1803 clock-names = "core", "iface";
1805 dma-names = "tx", "rx";
1806 pinctrl-0 = <&blsp_i2c4_default>;
1807 pinctrl-1 = <&blsp_i2c4_sleep>;
1808 pinctrl-names = "default", "sleep";
1809 #address-cells = <1>;
1810 #size-cells = <0>;
1815 compatible = "qcom,spi-qup-v2.2.1";
1820 clock-names = "core", "iface";
1822 dma-names = "tx", "rx";
1823 pinctrl-0 = <&blsp_spi4_default>;
1824 pinctrl-1 = <&blsp_spi4_sleep>;
1825 pinctrl-names = "default", "sleep";
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1832 compatible = "qcom,i2c-qup-v2.2.1";
1837 clock-names = "core", "iface";
1839 dma-names = "tx", "rx";
1840 pinctrl-0 = <&blsp_i2c5_default>;
1841 pinctrl-1 = <&blsp_i2c5_sleep>;
1842 pinctrl-names = "default", "sleep";
1843 #address-cells = <1>;
1844 #size-cells = <0>;
1849 compatible = "qcom,spi-qup-v2.2.1";
1854 clock-names = "core", "iface";
1856 dma-names = "tx", "rx";
1857 pinctrl-0 = <&blsp_spi5_default>;
1858 pinctrl-1 = <&blsp_spi5_sleep>;
1859 pinctrl-names = "default", "sleep";
1860 #address-cells = <1>;
1861 #size-cells = <0>;
1866 compatible = "qcom,i2c-qup-v2.2.1";
1871 clock-names = "core", "iface";
1873 dma-names = "tx", "rx";
1874 pinctrl-0 = <&blsp_i2c6_default>;
1875 pinctrl-1 = <&blsp_i2c6_sleep>;
1876 pinctrl-names = "default", "sleep";
1877 #address-cells = <1>;
1878 #size-cells = <0>;
1883 compatible = "qcom,spi-qup-v2.2.1";
1888 clock-names = "core", "iface";
1890 dma-names = "tx", "rx";
1891 pinctrl-0 = <&blsp_spi6_default>;
1892 pinctrl-1 = <&blsp_spi6_sleep>;
1893 pinctrl-names = "default", "sleep";
1894 #address-cells = <1>;
1895 #size-cells = <0>;
1900 compatible = "qcom,ci-hdrc";
1907 clock-names = "iface", "core";
1908 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1909 assigned-clock-rates = <80000000>;
1911 reset-names = "core";
1912 #reset-cells = <1>;
1915 adp-disable;
1916 hnp-disable;
1917 srp-disable;
1918 ahb-burst-config = <0>;
1919 phy-names = "usb-phy";
1925 compatible = "qcom,usb-hs-phy-msm8916",
1926 "qcom,usb-hs-phy";
1929 clock-names = "ref", "sleep";
1931 reset-names = "phy", "por";
1932 #phy-cells = <0>;
1933 qcom,init-seq = /bits/ 8 <0x0 0x44>,
1942 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1943 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1948 interrupt-names = "wdog",
1952 "stop-ack";
1956 reg-names = "ccu", "dxe", "pmu";
1958 memory-region = <&wcnss_mem>;
1960 power-domains = <&rpmpd MSM8939_VDDCX>,
1962 power-domain-names = "cx", "mx";
1964 qcom,smem-states = <&wcnss_smp2p_out 0>;
1965 qcom,smem-state-names = "stop";
1967 pinctrl-names = "default";
1968 pinctrl-0 = <&wcss_wlan_default>;
1973 /* Separate chip, compatible is board-specific */
1975 clock-names = "xo";
1978 smd-edge {
1981 qcom,smd-edge = <6>;
1982 qcom,remote-pid = <4>;
1988 qcom,smd-channels = "WCNSS_CTRL";
1993 compatible = "qcom,wcnss-bt";
1997 compatible = "qcom,wcnss-wlan";
2001 interrupt-names = "tx", "rx";
2003 qcom,smem-states = <&apps_smsm 10>,
2005 qcom,smem-state-names = "tx-enable",
2006 "tx-rings-empty";
2012 intc: interrupt-controller@b000000 {
2013 compatible = "qcom,msm-qgic2";
2016 interrupt-controller;
2017 #interrupt-cells = <3>;
2022 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2025 clock-names = "pll", "aux", "ref";
2026 #clock-cells = <0>;
2027 assigned-clocks = <&apcs2>;
2028 assigned-clock-rates = <297600000>;
2029 #mbox-cells = <1>;
2033 compatible = "qcom,msm8939-a53pll";
2035 #clock-cells = <0>;
2038 acc0: clock-controller@b088000 {
2039 compatible = "qcom,kpss-acc-v2";
2043 saw0: power-manager@b089000 {
2044 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2048 acc1: clock-controller@b098000 {
2049 compatible = "qcom,kpss-acc-v2";
2053 saw1: power-manager@b099000 {
2054 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2058 acc2: clock-controller@b0a8000 {
2059 compatible = "qcom,kpss-acc-v2";
2063 saw2: power-manager@b0a9000 {
2064 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2068 acc3: clock-controller@b0b8000 {
2069 compatible = "qcom,kpss-acc-v2";
2073 saw3: power-manager@b0b9000 {
2074 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2079 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2082 clock-names = "pll", "aux", "ref";
2083 #clock-cells = <0>;
2084 #mbox-cells = <1>;
2088 compatible = "qcom,msm8939-a53pll";
2090 #clock-cells = <0>;
2094 compatible = "arm,armv7-timer-mem";
2096 #address-cells = <1>;
2097 #size-cells = <1>;
2105 frame-number = <0>;
2111 frame-number = <1>;
2118 frame-number = <2>;
2125 frame-number = <3>;
2132 frame-number = <4>;
2139 frame-number = <5>;
2146 frame-number = <6>;
2151 acc4: clock-controller@b188000 {
2152 compatible = "qcom,kpss-acc-v2";
2156 saw4: power-manager@b189000 {
2157 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2161 acc5: clock-controller@b198000 {
2162 compatible = "qcom,kpss-acc-v2";
2166 saw5: power-manager@b199000 {
2167 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2171 acc6: clock-controller@b1a8000 {
2172 compatible = "qcom,kpss-acc-v2";
2176 saw6: power-manager@b1a9000 {
2177 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2181 acc7: clock-controller@b1b8000 {
2182 compatible = "qcom,kpss-acc-v2";
2186 saw7: power-manager@b1b9000 {
2187 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2192 compatible = "qcom,msm8939-a53pll";
2194 #clock-cells = <0>;
2198 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2201 clock-names = "pll", "aux", "ref";
2202 #clock-cells = <0>;
2203 #mbox-cells = <1>;
2207 thermal_zones: thermal-zones {
2208 cpu0-thermal {
2209 polling-delay-passive = <250>;
2210 polling-delay = <1000>;
2212 thermal-sensors = <&tsens 5>;
2228 cooling-maps {
2231 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2239 cpu1-thermal {
2240 polling-delay-passive = <250>;
2241 polling-delay = <1000>;
2243 thermal-sensors = <&tsens 6>;
2259 cooling-maps {
2262 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2270 cpu2-thermal {
2271 polling-delay-passive = <250>;
2272 polling-delay = <1000>;
2274 thermal-sensors = <&tsens 7>;
2290 cooling-maps {
2293 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2301 cpu3-thermal {
2302 polling-delay-passive = <250>;
2303 polling-delay = <1000>;
2305 thermal-sensors = <&tsens 8>;
2321 cooling-maps {
2324 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2332 cpu4567-thermal {
2333 polling-delay-passive = <250>;
2334 polling-delay = <1000>;
2336 thermal-sensors = <&tsens 9>;
2352 cooling-maps {
2355 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2363 gpu-thermal {
2364 polling-delay-passive = <250>;
2365 polling-delay = <1000>;
2367 thermal-sensors = <&tsens 3>;
2370 gpu_alert0: trip-point0 {
2384 modem1-thermal {
2385 polling-delay-passive = <250>;
2386 polling-delay = <1000>;
2388 thermal-sensors = <&tsens 0>;
2391 modem1_alert0: trip-point0 {
2399 modem2-thermal {
2400 polling-delay-passive = <250>;
2401 polling-delay = <1000>;
2403 thermal-sensors = <&tsens 2>;
2406 modem2_alert0: trip-point0 {
2414 camera-thermal {
2415 polling-delay-passive = <250>;
2416 polling-delay = <1000>;
2418 thermal-sensors = <&tsens 1>;
2421 cam_alert0: trip-point0 {
2431 compatible = "arm,armv8-timer";