Lines Matching +full:ipq8074 +full:- +full:tsens
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
13 model = "Qualcomm Technologies, Inc. IPQ8074";
14 compatible = "qcom,ipq8074";
15 interrupt-parent = <&intc>;
19 compatible = "fixed-clock";
20 clock-frequency = <32768>;
21 #clock-cells = <0>;
25 compatible = "fixed-clock";
26 clock-frequency = <19200000>;
27 #clock-cells = <0>;
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,cortex-a53";
39 next-level-cache = <&L2_0>;
40 enable-method = "psci";
45 compatible = "arm,cortex-a53";
46 enable-method = "psci";
48 next-level-cache = <&L2_0>;
53 compatible = "arm,cortex-a53";
54 enable-method = "psci";
56 next-level-cache = <&L2_0>;
61 compatible = "arm,cortex-a53";
62 enable-method = "psci";
64 next-level-cache = <&L2_0>;
67 L2_0: l2-cache {
69 cache-level = <2>;
70 cache-unified;
75 compatible = "arm,cortex-a53-pmu";
80 compatible = "arm,psci-1.0";
84 reserved-memory {
85 #address-cells = <2>;
86 #size-cells = <2>;
91 no-map;
96 no-map;
102 no-map;
109 no-map;
115 compatible = "qcom,scm-ipq8074", "qcom,scm";
116 qcom,dload-mode = <&tcsr 0x6100>;
121 #address-cells = <1>;
122 #size-cells = <1>;
124 compatible = "simple-bus";
127 compatible = "qcom,ipq8074-qmp-usb3-phy";
129 #address-cells = <1>;
130 #size-cells = <1>;
136 clock-names = "aux", "cfg_ahb", "ref";
140 reset-names = "phy","common";
148 #phy-cells = <0>;
149 #clock-cells = <0>;
151 clock-names = "pipe0";
152 clock-output-names = "usb3phy_1_cc_pipe_clk";
157 compatible = "qcom,ipq8074-qusb2-phy";
159 #phy-cells = <0>;
163 clock-names = "cfg_ahb", "ref";
170 compatible = "qcom,ipq8074-qmp-usb3-phy";
172 #address-cells = <1>;
173 #size-cells = <1>;
179 clock-names = "aux", "cfg_ahb", "ref";
183 reset-names = "phy","common";
191 #phy-cells = <0>;
192 #clock-cells = <0>;
194 clock-names = "pipe0";
195 clock-output-names = "usb3phy_0_cc_pipe_clk";
200 compatible = "qcom,ipq8074-qusb2-phy";
202 #phy-cells = <0>;
206 clock-names = "cfg_ahb", "ref";
213 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
215 #address-cells = <1>;
216 #size-cells = <1>;
221 clock-names = "aux", "cfg_ahb";
224 reset-names = "phy",
233 #phy-cells = <0>;
234 #clock-cells = <0>;
236 clock-names = "pipe0";
237 clock-output-names = "pcie20_phy0_pipe_clk";
242 compatible = "qcom,ipq8074-qmp-pcie-phy";
244 #address-cells = <1>;
245 #size-cells = <1>;
250 clock-names = "aux", "cfg_ahb";
253 reset-names = "phy",
261 #phy-cells = <0>;
262 #clock-cells = <0>;
264 clock-names = "pipe0";
265 clock-output-names = "pcie20_phy1_pipe_clk";
270 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio";
272 #address-cells = <1>;
273 #size-cells = <0>;
276 clock-names = "gcc_mdio_ahb_clk";
282 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
284 #address-cells = <1>;
285 #size-cells = <1>;
289 compatible = "qcom,prng-ee";
292 clock-names = "core";
296 tsens: thermal-sensor@4a9000 { label
297 compatible = "qcom,ipq8074-tsens";
301 interrupt-names = "combined";
303 #thermal-sensor-cells = <1>;
306 cryptobam: dma-controller@704000 {
307 compatible = "qcom,bam-v1.7.0";
311 clock-names = "bam_clk";
312 #dma-cells = <1>;
314 qcom,controlled-remotely;
319 compatible = "qcom,crypto-v5.1";
324 clock-names = "iface", "bus", "core";
326 dma-names = "rx", "tx";
331 compatible = "qcom,ipq8074-pinctrl";
334 gpio-controller;
335 gpio-ranges = <&tlmm 0 0 70>;
336 #gpio-cells = <2>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
340 serial_4_pins: serial4-state {
343 drive-strength = <8>;
344 bias-disable;
347 i2c_0_pins: i2c-0-state {
350 drive-strength = <8>;
351 bias-disable;
354 spi_0_pins: spi-0-state {
357 drive-strength = <8>;
358 bias-disable;
361 hsuart_pins: hsuart-state {
364 drive-strength = <8>;
365 bias-disable;
368 qpic_pins: qpic-state {
375 drive-strength = <8>;
376 bias-disable;
381 compatible = "qcom,gcc-ipq8074";
384 clock-names = "xo", "sleep_clk";
385 #clock-cells = <1>;
386 #power-domain-cells = <1>;
387 #reset-cells = <1>;
391 compatible = "qcom,tcsr-mutex";
393 #hwlock-cells = <1>;
397 compatible = "qcom,tcsr-ipq8074", "syscon";
402 compatible = "qcom,spmi-pmic-arb";
408 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
410 interrupt-names = "periph_irq";
413 #address-cells = <2>;
414 #size-cells = <0>;
415 interrupt-controller;
416 #interrupt-cells = <4>;
420 compatible = "qcom,sdhci-msm-v4";
422 reg-names = "hc", "core";
426 interrupt-names = "hc_irq", "pwr_irq";
431 clock-names = "iface", "core", "xo";
433 max-frequency = <384000000>;
434 mmc-ddr-1_8v;
435 mmc-hs200-1_8v;
436 mmc-hs400-1_8v;
437 bus-width = <8>;
442 blsp_dma: dma-controller@7884000 {
443 compatible = "qcom,bam-v1.7.0";
447 clock-names = "bam_clk";
448 #dma-cells = <1>;
453 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
458 clock-names = "core", "iface";
463 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
468 clock-names = "core", "iface";
471 dma-names = "tx", "rx";
472 pinctrl-0 = <&hsuart_pins>;
473 pinctrl-names = "default";
478 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
483 clock-names = "core", "iface";
484 pinctrl-0 = <&serial_4_pins>;
485 pinctrl-names = "default";
490 compatible = "qcom,spi-qup-v2.2.1";
491 #address-cells = <1>;
492 #size-cells = <0>;
497 clock-names = "core", "iface";
499 dma-names = "tx", "rx";
500 pinctrl-0 = <&spi_0_pins>;
501 pinctrl-names = "default";
506 compatible = "qcom,i2c-qup-v2.2.1";
507 #address-cells = <1>;
508 #size-cells = <0>;
513 clock-names = "core", "iface";
514 clock-frequency = <400000>;
516 dma-names = "tx", "rx";
517 pinctrl-0 = <&i2c_0_pins>;
518 pinctrl-names = "default";
523 compatible = "qcom,i2c-qup-v2.2.1";
524 #address-cells = <1>;
525 #size-cells = <0>;
530 clock-names = "core", "iface";
531 clock-frequency = <100000>;
533 dma-names = "tx", "rx";
538 compatible = "qcom,i2c-qup-v2.2.1";
539 #address-cells = <1>;
540 #size-cells = <0>;
545 clock-names = "core", "iface";
546 clock-frequency = <400000>;
548 dma-names = "tx", "rx";
553 compatible = "qcom,spi-qup-v2.2.1";
554 #address-cells = <1>;
555 #size-cells = <0>;
560 clock-names = "core", "iface";
562 dma-names = "tx", "rx";
567 compatible = "qcom,i2c-qup-v2.2.1";
568 #address-cells = <1>;
569 #size-cells = <0>;
574 clock-names = "core", "iface";
575 clock-frequency = <100000>;
577 dma-names = "tx", "rx";
581 qpic_bam: dma-controller@7984000 {
582 compatible = "qcom,bam-v1.7.0";
586 clock-names = "bam_clk";
587 #dma-cells = <1>;
592 qpic_nand: nand-controller@79b0000 {
593 compatible = "qcom,ipq8074-nand";
595 #address-cells = <1>;
596 #size-cells = <0>;
599 clock-names = "core", "aon";
604 dma-names = "tx", "rx", "cmd";
605 pinctrl-0 = <&qpic_pins>;
606 pinctrl-names = "default";
611 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
613 #address-cells = <1>;
614 #size-cells = <1>;
621 clock-names = "cfg_noc",
626 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
629 assigned-clock-rates = <133330000>,
633 power-domains = <&gcc USB0_GDSC>;
643 phy-names = "usb2-phy", "usb3-phy";
644 snps,parkmode-disable-ss-quirk;
645 snps,is-utmi-l1-suspend;
646 snps,hird-threshold = /bits/ 8 <0x0>;
654 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
656 #address-cells = <1>;
657 #size-cells = <1>;
664 clock-names = "cfg_noc",
669 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
672 assigned-clock-rates = <133330000>,
676 power-domains = <&gcc USB1_GDSC>;
686 phy-names = "usb2-phy", "usb3-phy";
687 snps,parkmode-disable-ss-quirk;
688 snps,is-utmi-l1-suspend;
689 snps,hird-threshold = /bits/ 8 <0x0>;
696 intc: interrupt-controller@b000000 {
697 compatible = "qcom,msm-qgic2";
698 #address-cells = <1>;
699 #size-cells = <1>;
700 interrupt-controller;
701 #interrupt-cells = <3>;
706 compatible = "arm,gic-v2m-frame";
707 msi-controller;
713 compatible = "qcom,kpss-wdt";
717 timeout-sec = <30>;
721 compatible = "qcom,ipq8074-apcs-apps-global",
722 "qcom,ipq6018-apcs-apps-global";
725 clock-names = "pll", "xo";
727 #clock-cells = <1>;
728 #mbox-cells = <1>;
732 compatible = "qcom,ipq8074-a53pll";
734 #clock-cells = <0>;
736 clock-names = "xo";
740 #address-cells = <1>;
741 #size-cells = <1>;
743 compatible = "arm,armv7-timer-mem";
747 frame-number = <0>;
755 frame-number = <1>;
762 frame-number = <2>;
769 frame-number = <3>;
776 frame-number = <4>;
783 frame-number = <5>;
790 frame-number = <6>;
798 compatible = "qcom,pcie-ipq8074";
803 reg-names = "dbi", "elbi", "parf", "config";
805 linux,pci-domain = <1>;
806 bus-range = <0x00 0xff>;
807 num-lanes = <1>;
808 max-link-speed = <2>;
809 #address-cells = <3>;
810 #size-cells = <2>;
813 phy-names = "pciephy";
819 interrupt-names = "msi";
820 #interrupt-cells = <1>;
821 interrupt-map-mask = <0 0 0 0x7>;
822 interrupt-map = <0 0 0 1 &intc 0 0 142
836 clock-names = "iface",
848 reset-names = "pipe",
859 compatible = "qcom,pcie-ipq8074-gen3";
865 reg-names = "dbi", "elbi", "atu", "parf", "config";
867 linux,pci-domain = <0>;
868 bus-range = <0x00 0xff>;
869 num-lanes = <1>;
870 max-link-speed = <3>;
871 #address-cells = <3>;
872 #size-cells = <2>;
875 phy-names = "pciephy";
881 interrupt-names = "msi";
882 #interrupt-cells = <1>;
883 interrupt-map-mask = <0 0 0 0x7>;
884 interrupt-map = <0 0 0 1 &intc 0 0 75
898 clock-names = "iface",
912 reset-names = "pipe",
925 compatible = "arm,armv8-timer";
932 thermal-zones {
933 nss-top-thermal {
934 polling-delay-passive = <250>;
935 polling-delay = <1000>;
937 thermal-sensors = <&tsens 4>;
940 nss-top-crit {
948 nss0-thermal {
949 polling-delay-passive = <250>;
950 polling-delay = <1000>;
952 thermal-sensors = <&tsens 5>;
955 nss-0-crit {
963 nss1-thermal {
964 polling-delay-passive = <250>;
965 polling-delay = <1000>;
967 thermal-sensors = <&tsens 6>;
970 nss-1-crit {
978 wcss-phya0-thermal {
979 polling-delay-passive = <250>;
980 polling-delay = <1000>;
982 thermal-sensors = <&tsens 7>;
985 wcss-phya0-crit {
993 wcss-phya1-thermal {
994 polling-delay-passive = <250>;
995 polling-delay = <1000>;
997 thermal-sensors = <&tsens 8>;
1000 wcss-phya1-crit {
1008 cpu0_thermal: cpu0-thermal {
1009 polling-delay-passive = <250>;
1010 polling-delay = <1000>;
1012 thermal-sensors = <&tsens 9>;
1015 cpu0-crit {
1023 cpu1_thermal: cpu1-thermal {
1024 polling-delay-passive = <250>;
1025 polling-delay = <1000>;
1027 thermal-sensors = <&tsens 10>;
1030 cpu1-crit {
1038 cpu2_thermal: cpu2-thermal {
1039 polling-delay-passive = <250>;
1040 polling-delay = <1000>;
1042 thermal-sensors = <&tsens 11>;
1045 cpu2-crit {
1053 cpu3_thermal: cpu3-thermal {
1054 polling-delay-passive = <250>;
1055 polling-delay = <1000>;
1057 thermal-sensors = <&tsens 12>;
1060 cpu3-crit {
1068 cluster_thermal: cluster-thermal {
1069 polling-delay-passive = <250>;
1070 polling-delay = <1000>;
1072 thermal-sensors = <&tsens 13>;
1075 cluster-crit {
1083 wcss-phyb0-thermal {
1084 polling-delay-passive = <250>;
1085 polling-delay = <1000>;
1087 thermal-sensors = <&tsens 14>;
1090 wcss-phyb0-crit {
1098 wcss-phyb1-thermal {
1099 polling-delay-passive = <250>;
1100 polling-delay = <1000>;
1102 thermal-sensors = <&tsens 15>;
1105 wcss-phyb1-crit {