dts/qcom/ipq5332.dtsi

1 // SPDX-License-Identifier: BSD-3-Clause
5  * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 #include <dt-bindings/clock/qcom,apss-ipq.h>
9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 	interrupt-parent = <&intc>;
14 	#address-cells = <2>;
15 	#size-cells = <2>;
18 		sleep_clk: sleep-clk {
19 			compatible = "fixed-clock";
20 			#clock-cells = <0>;
23 		xo_board: xo-board-clk {
24 			compatible = "fixed-clock";
25 			#clock-cells = <0>;
30 		#address-cells = <1>;
31 		#size-cells = <0>;
35 			compatible = "arm,cortex-a53";
37 			enable-method = "psci";
38 			next-level-cache = <&L2_0>;
40 			operating-points-v2 = <&cpu_opp_table>;
45 			compatible = "arm,cortex-a53";
47 			enable-method = "psci";
48 			next-level-cache = <&L2_0>;
50 			operating-points-v2 = <&cpu_opp_table>;
55 			compatible = "arm,cortex-a53";
57 			enable-method = "psci";
58 			next-level-cache = <&L2_0>;
60 			operating-points-v2 = <&cpu_opp_table>;
65 			compatible = "arm,cortex-a53";
67 			enable-method = "psci";
68 			next-level-cache = <&L2_0>;
70 			operating-points-v2 = <&cpu_opp_table>;
73 		L2_0: l2-cache {
75 			cache-level = <2>;
76 			cache-unified;
82 			compatible = "qcom,scm-ipq5332", "qcom,scm";
83 			qcom,dload-mode = <&tcsr 0x6100>;
93 	cpu_opp_table: opp-table-cpu {
94 		compatible = "operating-points-v2";
95 		opp-shared;
97 		opp-1488000000 {
98 			opp-hz = /bits/ 64 <1488000000>;
99 			clock-latency-ns = <200000>;
104 		compatible = "arm,cortex-a53-pmu";
109 		compatible = "arm,psci-1.0";
113 	reserved-memory {
114 		#address-cells = <2>;
115 		#size-cells = <2>;
120 			no-map;
125 			no-map;
130 			no-map;
136 			no-map;
143 		compatible = "simple-bus";
144 		#address-cells = <1>;
145 		#size-cells = <1>;
149 			compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
151 			#address-cells = <1>;
152 			#size-cells = <1>;
156 			compatible = "qcom,prng-ee";
159 			clock-names = "core";
163 			compatible = "qcom,ipq5332-tlmm";
166 			gpio-controller;
167 			#gpio-cells = <2>;
168 			gpio-ranges = <&tlmm 0 0 53>;
169 			interrupt-controller;
170 			#interrupt-cells = <2>;
172 			serial_0_pins: serial0-state {
175 				drive-strength = <8>;
176 				bias-pull-up;
180 		gcc: clock-controller@1800000 {
181 			compatible = "qcom,ipq5332-gcc";
183 			#clock-cells = <1>;
184 			#reset-cells = <1>;
185 			#power-domain-cells = <1>;
194 			compatible = "qcom,tcsr-mutex";
196 			#hwlock-cells = <1>;
200 			compatible = "qcom,tcsr-ipq5332", "syscon";
205 			compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
210 			interrupt-names = "hc_irq", "pwr_irq";
215 			clock-names = "iface", "core", "xo";
219 		blsp_dma: dma-controller@7884000 {
220 			compatible = "qcom,bam-v1.7.0";
224 			clock-names = "bam_clk";
225 			#dma-cells = <1>;
230 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
235 			clock-names = "core", "iface";
240 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
245 			clock-names = "core", "iface";
247 			dma-names = "tx", "rx";
252 			compatible = "qcom,spi-qup-v2.2.1";
254 			#address-cells = <1>;
255 			#size-cells = <0>;
259 			clock-names = "core", "iface";
261 			dma-names = "tx", "rx";
266 			compatible = "qcom,i2c-qup-v2.2.1";
268 			#address-cells = <1>;
269 			#size-cells = <0>;
273 			clock-names = "core", "iface";
275 			dma-names = "tx", "rx";
280 			compatible = "qcom,spi-qup-v2.2.1";
282 			#address-cells = <1>;
283 			#size-cells = <0>;
287 			clock-names = "core", "iface";
289 			dma-names = "tx", "rx";
293 		intc: interrupt-controller@b000000 {
294 			compatible = "qcom,msm-qgic2";
300 			interrupt-controller;
301 			#interrupt-cells = <3>;
302 			#address-cells = <1>;
303 			#size-cells = <1>;
307 				compatible = "arm,gic-v2m-frame";
309 				msi-controller;
313 				compatible = "arm,gic-v2m-frame";
315 				msi-controller;
319 				compatible = "arm,gic-v2m-frame";
321 				msi-controller;
326 			compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt";
330 			timeout-sec = <30>;
334 			compatible = "qcom,ipq5332-apcs-apps-global",
335 				     "qcom,ipq6018-apcs-apps-global";
337 			#clock-cells = <1>;
339 			clock-names = "pll", "xo";
340 			#mbox-cells = <1>;
344 			compatible = "qcom,ipq5332-a53pll";
346 			#clock-cells = <0>;
348 			clock-names = "xo";
352 			compatible = "arm,armv7-timer-mem";
354 			#address-cells = <1>;
355 			#size-cells = <1>;
363 				frame-number = <0>;
369 				frame-number = <1>;
376 				frame-number = <2>;
383 				frame-number = <3>;
390 				frame-number = <4>;
397 				frame-number = <5>;
404 				frame-number = <6>;
411 		compatible = "arm,armv8-timer";