Lines Matching refs:TEGRA234_CLK_PLLP_OUT0
183 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
709 &bpmp TEGRA234_CLK_PLLP_OUT0>;
711 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
728 &bpmp TEGRA234_CLK_PLLP_OUT0>;
730 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
747 &bpmp TEGRA234_CLK_PLLP_OUT0>;
749 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
766 &bpmp TEGRA234_CLK_PLLP_OUT0>;
768 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
785 &bpmp TEGRA234_CLK_PLLP_OUT0>;
787 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
811 &bpmp TEGRA234_CLK_PLLP_OUT0>;
813 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
829 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
850 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1755 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1758 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1774 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1777 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1794 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;