Lines Matching +full:tegra194 +full:- +full:pinmux
1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 compatible = "simple-bus";
22 #address-cells = <2>;
23 #size-cells = <2>;
27 compatible = "nvidia,tegra234-misc";
34 compatible = "nvidia,tegra234-timer";
56 compatible = "nvidia,tegra234-gpio";
57 reg-names = "security", "gpio";
108 #interrupt-cells = <2>;
109 interrupt-controller;
110 #gpio-cells = <2>;
111 gpio-controller;
112 gpio-ranges = <&pinmux 0 0 164>;
115 pinmux: pinmux@2430000 { label
116 compatible = "nvidia,tegra234-pinmux";
120 gpcdma: dma-controller@2600000 {
121 compatible = "nvidia,tegra234-gpcdma",
122 "nvidia,tegra186-gpcdma";
125 reset-names = "gpcdma";
158 #dma-cells = <1>;
160 dma-channel-mask = <0xfffffffe>;
161 dma-coherent;
165 compatible = "nvidia,tegra234-aconnect",
166 "nvidia,tegra210-aconnect";
169 clock-names = "ape", "apb2ape";
170 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
173 #address-cells = <2>;
174 #size-cells = <2>;
178 compatible = "nvidia,tegra234-ahub";
181 clock-names = "ahub";
182 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
183 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
184 assigned-clock-rates = <81600000>;
187 #address-cells = <2>;
188 #size-cells = <2>;
192 compatible = "nvidia,tegra234-i2s",
193 "nvidia,tegra210-i2s";
197 clock-names = "i2s", "sync_input";
198 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
199 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
200 assigned-clock-rates = <1536000>;
201 sound-name-prefix = "I2S1";
206 compatible = "nvidia,tegra234-i2s",
207 "nvidia,tegra210-i2s";
211 clock-names = "i2s", "sync_input";
212 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
213 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
214 assigned-clock-rates = <1536000>;
215 sound-name-prefix = "I2S2";
220 compatible = "nvidia,tegra234-i2s",
221 "nvidia,tegra210-i2s";
225 clock-names = "i2s", "sync_input";
226 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
227 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
228 assigned-clock-rates = <1536000>;
229 sound-name-prefix = "I2S3";
234 compatible = "nvidia,tegra234-i2s",
235 "nvidia,tegra210-i2s";
239 clock-names = "i2s", "sync_input";
240 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
241 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
242 assigned-clock-rates = <1536000>;
243 sound-name-prefix = "I2S4";
248 compatible = "nvidia,tegra234-i2s",
249 "nvidia,tegra210-i2s";
253 clock-names = "i2s", "sync_input";
254 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
255 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
256 assigned-clock-rates = <1536000>;
257 sound-name-prefix = "I2S5";
262 compatible = "nvidia,tegra234-i2s",
263 "nvidia,tegra210-i2s";
267 clock-names = "i2s", "sync_input";
268 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
269 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
270 assigned-clock-rates = <1536000>;
271 sound-name-prefix = "I2S6";
276 compatible = "nvidia,tegra234-sfc",
277 "nvidia,tegra210-sfc";
279 sound-name-prefix = "SFC1";
284 compatible = "nvidia,tegra234-sfc",
285 "nvidia,tegra210-sfc";
287 sound-name-prefix = "SFC2";
292 compatible = "nvidia,tegra234-sfc",
293 "nvidia,tegra210-sfc";
295 sound-name-prefix = "SFC3";
300 compatible = "nvidia,tegra234-sfc",
301 "nvidia,tegra210-sfc";
303 sound-name-prefix = "SFC4";
308 compatible = "nvidia,tegra234-amx",
309 "nvidia,tegra194-amx";
311 sound-name-prefix = "AMX1";
316 compatible = "nvidia,tegra234-amx",
317 "nvidia,tegra194-amx";
319 sound-name-prefix = "AMX2";
324 compatible = "nvidia,tegra234-amx",
325 "nvidia,tegra194-amx";
327 sound-name-prefix = "AMX3";
332 compatible = "nvidia,tegra234-amx",
333 "nvidia,tegra194-amx";
335 sound-name-prefix = "AMX4";
340 compatible = "nvidia,tegra234-adx",
341 "nvidia,tegra210-adx";
343 sound-name-prefix = "ADX1";
348 compatible = "nvidia,tegra234-adx",
349 "nvidia,tegra210-adx";
351 sound-name-prefix = "ADX2";
356 compatible = "nvidia,tegra234-adx",
357 "nvidia,tegra210-adx";
359 sound-name-prefix = "ADX3";
364 compatible = "nvidia,tegra234-adx",
365 "nvidia,tegra210-adx";
367 sound-name-prefix = "ADX4";
373 compatible = "nvidia,tegra234-dmic",
374 "nvidia,tegra210-dmic";
377 clock-names = "dmic";
378 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
379 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
380 assigned-clock-rates = <3072000>;
381 sound-name-prefix = "DMIC1";
386 compatible = "nvidia,tegra234-dmic",
387 "nvidia,tegra210-dmic";
390 clock-names = "dmic";
391 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
392 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
393 assigned-clock-rates = <3072000>;
394 sound-name-prefix = "DMIC2";
399 compatible = "nvidia,tegra234-dmic",
400 "nvidia,tegra210-dmic";
403 clock-names = "dmic";
404 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
405 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
406 assigned-clock-rates = <3072000>;
407 sound-name-prefix = "DMIC3";
412 compatible = "nvidia,tegra234-dmic",
413 "nvidia,tegra210-dmic";
416 clock-names = "dmic";
417 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
418 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
419 assigned-clock-rates = <3072000>;
420 sound-name-prefix = "DMIC4";
425 compatible = "nvidia,tegra234-dspk",
426 "nvidia,tegra186-dspk";
429 clock-names = "dspk";
430 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
431 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
432 assigned-clock-rates = <12288000>;
433 sound-name-prefix = "DSPK1";
438 compatible = "nvidia,tegra234-dspk",
439 "nvidia,tegra186-dspk";
442 clock-names = "dspk";
443 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
444 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
445 assigned-clock-rates = <12288000>;
446 sound-name-prefix = "DSPK2";
450 tegra_ope1: processing-engine@2908000 {
451 compatible = "nvidia,tegra234-ope",
452 "nvidia,tegra210-ope";
454 sound-name-prefix = "OPE1";
457 #address-cells = <2>;
458 #size-cells = <2>;
462 compatible = "nvidia,tegra234-peq",
463 "nvidia,tegra210-peq";
467 dynamic-range-compressor@2908200 {
468 compatible = "nvidia,tegra234-mbdrc",
469 "nvidia,tegra210-mbdrc";
475 compatible = "nvidia,tegra234-mvc",
476 "nvidia,tegra210-mvc";
478 sound-name-prefix = "MVC1";
483 compatible = "nvidia,tegra234-mvc",
484 "nvidia,tegra210-mvc";
486 sound-name-prefix = "MVC2";
491 compatible = "nvidia,tegra234-amixer",
492 "nvidia,tegra210-amixer";
494 sound-name-prefix = "MIXER1";
499 compatible = "nvidia,tegra234-admaif",
500 "nvidia,tegra186-admaif";
522 dma-names = "rx1", "tx1",
544 interconnect-names = "dma-mem", "write";
550 compatible = "nvidia,tegra234-asrc",
551 "nvidia,tegra186-asrc";
553 sound-name-prefix = "ASRC1";
558 adma: dma-controller@2930000 {
559 compatible = "nvidia,tegra234-adma",
560 "nvidia,tegra186-adma";
562 interrupt-parent = <&agic>;
595 #dma-cells = <1>;
597 clock-names = "d_audio";
601 agic: interrupt-controller@2a40000 {
602 compatible = "nvidia,tegra234-agic",
603 "nvidia,tegra210-agic";
604 #interrupt-cells = <3>;
605 interrupt-controller;
612 clock-names = "clk";
617 mc: memory-controller@2c00000 {
618 compatible = "nvidia,tegra234-mc";
619 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
637 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
641 #interconnect-cells = <1>;
644 #address-cells = <2>;
645 #size-cells = <2>;
665 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
667 emc: external-memory-controller@2c60000 {
668 compatible = "nvidia,tegra234-emc";
673 clock-names = "emc";
676 #interconnect-cells = <0>;
683 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
692 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
701 compatible = "nvidia,tegra194-i2c";
705 #address-cells = <1>;
706 #size-cells = <0>;
707 clock-frequency = <400000>;
710 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
711 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
712 clock-names = "div-clk", "parent";
714 reset-names = "i2c";
716 dma-names = "rx", "tx";
720 compatible = "nvidia,tegra194-i2c";
723 #address-cells = <1>;
724 #size-cells = <0>;
726 clock-frequency = <400000>;
729 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
730 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
731 clock-names = "div-clk", "parent";
733 reset-names = "i2c";
735 dma-names = "rx", "tx";
739 compatible = "nvidia,tegra194-i2c";
742 #address-cells = <1>;
743 #size-cells = <0>;
745 clock-frequency = <100000>;
748 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
749 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
750 clock-names = "div-clk", "parent";
752 reset-names = "i2c";
754 dma-names = "rx", "tx";
758 compatible = "nvidia,tegra194-i2c";
761 #address-cells = <1>;
762 #size-cells = <0>;
764 clock-frequency = <100000>;
767 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
768 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
769 clock-names = "div-clk", "parent";
771 reset-names = "i2c";
773 dma-names = "rx", "tx";
777 compatible = "nvidia,tegra194-i2c";
780 #address-cells = <1>;
781 #size-cells = <0>;
783 clock-frequency = <100000>;
786 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
787 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
788 clock-names = "div-clk", "parent";
790 reset-names = "i2c";
792 dma-names = "rx", "tx";
796 compatible = "arm,sbsa-uart";
803 compatible = "nvidia,tegra194-i2c";
806 #address-cells = <1>;
807 #size-cells = <0>;
809 clock-frequency = <100000>;
812 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
813 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
814 clock-names = "div-clk", "parent";
816 reset-names = "i2c";
818 dma-names = "rx", "tx";
822 compatible = "nvidia,tegra210-spi";
825 #address-cells = <1>;
826 #size-cells = <0>;
828 assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>;
829 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
830 clock-names = "spi";
833 reset-names = "spi";
835 dma-names = "rx", "tx";
836 dma-coherent;
841 compatible = "nvidia,tegra210-spi";
844 #address-cells = <1>;
845 #size-cells = <0>;
847 clock-names = "spi";
849 assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>;
850 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
852 reset-names = "spi";
854 dma-names = "rx", "tx";
855 dma-coherent;
860 compatible = "nvidia,tegra234-qspi";
863 #address-cells = <1>;
864 #size-cells = <0>;
867 clock-names = "qspi", "qspi_out";
873 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
877 reset-names = "pwm";
879 #pwm-cells = <2>;
883 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
887 reset-names = "pwm";
889 #pwm-cells = <2>;
893 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
897 reset-names = "pwm";
899 #pwm-cells = <2>;
903 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
907 reset-names = "pwm";
909 #pwm-cells = <2>;
913 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
917 reset-names = "pwm";
919 #pwm-cells = <2>;
923 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
927 reset-names = "pwm";
929 #pwm-cells = <2>;
933 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
937 reset-names = "pwm";
939 #pwm-cells = <2>;
943 compatible = "nvidia,tegra234-qspi";
946 #address-cells = <1>;
947 #size-cells = <0>;
950 clock-names = "qspi", "qspi_out";
956 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
961 clock-names = "sdhci", "tmclk";
962 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
964 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
967 reset-names = "sdhci";
970 interconnect-names = "dma-mem", "write";
972 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
973 pinctrl-0 = <&sdmmc1_3v3>;
974 pinctrl-1 = <&sdmmc1_1v8>;
975 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
976 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
977 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
978 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
979 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
980 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
981 nvidia,default-tap = <14>;
982 nvidia,default-trim = <0x8>;
983 sd-uhs-sdr25;
984 sd-uhs-sdr50;
985 sd-uhs-ddr50;
986 sd-uhs-sdr104;
991 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
996 clock-names = "sdhci", "tmclk";
997 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
999 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
1001 reset-names = "sdhci";
1004 interconnect-names = "dma-mem", "write";
1006 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1007 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1008 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1009 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
1010 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1011 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
1012 nvidia,default-tap = <0x8>;
1013 nvidia,default-trim = <0x14>;
1014 nvidia,dqs-trim = <40>;
1015 supports-cqe;
1020 compatible = "nvidia,tegra234-hda";
1025 clock-names = "hda", "hda2codec_2x";
1028 reset-names = "hda", "hda2codec_2x";
1029 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
1032 interconnect-names = "dma-mem", "write";
1038 compatible = "nvidia,tegra234-xusb-padctl";
1041 reg-names = "padctl", "ao";
1045 reset-names = "padctl";
1052 clock-names = "trk";
1055 usb2-0 {
1058 #phy-cells = <0>;
1061 usb2-1 {
1064 #phy-cells = <0>;
1067 usb2-2 {
1070 #phy-cells = <0>;
1073 usb2-3 {
1076 #phy-cells = <0>;
1083 usb3-0 {
1086 #phy-cells = <0>;
1089 usb3-1 {
1092 #phy-cells = <0>;
1095 usb3-2 {
1098 #phy-cells = <0>;
1101 usb3-3 {
1104 #phy-cells = <0>;
1111 usb2-0 {
1115 usb2-1 {
1119 usb2-2 {
1123 usb2-3 {
1127 usb3-0 {
1131 usb3-1 {
1135 usb3-2 {
1139 usb3-3 {
1146 compatible = "nvidia,tegra234-xudc";
1149 reg-names = "base", "fpci";
1155 clock-names = "dev", "ss", "ss_src", "fs_src";
1158 interconnect-names = "dma-mem", "write";
1160 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>,
1162 power-domain-names = "dev", "ss";
1163 nvidia,xusb-padctl = <&xusb_padctl>;
1164 dma-coherent;
1169 compatible = "nvidia,tegra234-xusb";
1173 reg-names = "hcd", "fpci", "bar2";
1187 clock-names = "xusb_host", "xusb_falcon_src",
1193 interconnect-names = "dma-mem", "write";
1196 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
1198 power-domain-names = "xusb_host", "xusb_ss";
1200 nvidia,xusb-padctl = <&xusb_padctl>;
1201 dma-coherent;
1206 compatible = "nvidia,tegra234-efuse";
1209 clock-names = "fuse";
1212 hte_lic: hardware-timestamp@3aa0000 {
1213 compatible = "nvidia,tegra234-gte-lic";
1216 nvidia,int-threshold = <1>;
1217 #timestamp-cells = <1>;
1221 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
1232 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1235 #mbox-cells = <2>;
1239 compatible = "nvidia,tegra234-p2u";
1241 reg-names = "ctl";
1243 #phy-cells = <0>;
1247 compatible = "nvidia,tegra234-p2u";
1249 reg-names = "ctl";
1251 #phy-cells = <0>;
1255 compatible = "nvidia,tegra234-p2u";
1257 reg-names = "ctl";
1259 #phy-cells = <0>;
1263 compatible = "nvidia,tegra234-p2u";
1265 reg-names = "ctl";
1267 #phy-cells = <0>;
1271 compatible = "nvidia,tegra234-p2u";
1273 reg-names = "ctl";
1275 #phy-cells = <0>;
1279 compatible = "nvidia,tegra234-p2u";
1281 reg-names = "ctl";
1283 #phy-cells = <0>;
1287 compatible = "nvidia,tegra234-p2u";
1289 reg-names = "ctl";
1291 #phy-cells = <0>;
1295 compatible = "nvidia,tegra234-p2u";
1297 reg-names = "ctl";
1299 #phy-cells = <0>;
1303 compatible = "nvidia,tegra234-p2u";
1305 reg-names = "ctl";
1307 #phy-cells = <0>;
1311 compatible = "nvidia,tegra234-p2u";
1313 reg-names = "ctl";
1315 #phy-cells = <0>;
1319 compatible = "nvidia,tegra234-p2u";
1321 reg-names = "ctl";
1323 #phy-cells = <0>;
1327 compatible = "nvidia,tegra234-p2u";
1329 reg-names = "ctl";
1331 #phy-cells = <0>;
1335 compatible = "nvidia,tegra234-p2u";
1337 reg-names = "ctl";
1339 #phy-cells = <0>;
1343 compatible = "nvidia,tegra234-p2u";
1345 reg-names = "ctl";
1347 #phy-cells = <0>;
1351 compatible = "nvidia,tegra234-p2u";
1353 reg-names = "ctl";
1355 #phy-cells = <0>;
1359 compatible = "nvidia,tegra234-p2u";
1361 reg-names = "ctl";
1363 #phy-cells = <0>;
1367 compatible = "nvidia,tegra234-p2u";
1369 reg-names = "ctl";
1371 #phy-cells = <0>;
1375 compatible = "nvidia,tegra234-p2u";
1377 reg-names = "ctl";
1379 #phy-cells = <0>;
1383 compatible = "nvidia,tegra234-p2u";
1385 reg-names = "ctl";
1387 #phy-cells = <0>;
1391 compatible = "nvidia,tegra234-p2u";
1393 reg-names = "ctl";
1395 #phy-cells = <0>;
1399 compatible = "nvidia,tegra234-p2u";
1401 reg-names = "ctl";
1403 #phy-cells = <0>;
1407 compatible = "nvidia,tegra234-p2u";
1409 reg-names = "ctl";
1411 #phy-cells = <0>;
1415 compatible = "nvidia,tegra234-p2u";
1417 reg-names = "ctl";
1419 #phy-cells = <0>;
1423 compatible = "nvidia,tegra234-p2u";
1425 reg-names = "ctl";
1427 #phy-cells = <0>;
1431 compatible = "nvidia,tegra234-mgbe";
1435 reg-names = "hypervisor", "mac", "xpcs";
1437 interrupt-names = "common";
1450 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1451 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1452 "rx-pcs", "tx-pcs";
1455 reset-names = "mac", "pcs";
1458 interconnect-names = "dma-mem", "write";
1460 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
1465 compatible = "nvidia,tegra234-mgbe";
1469 reg-names = "hypervisor", "mac", "xpcs";
1471 interrupt-names = "common";
1484 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1485 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1486 "rx-pcs", "tx-pcs";
1489 reset-names = "mac", "pcs";
1492 interconnect-names = "dma-mem", "write";
1494 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
1499 compatible = "nvidia,tegra234-mgbe";
1503 reg-names = "hypervisor", "mac", "xpcs";
1505 interrupt-names = "common";
1518 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1519 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1520 "rx-pcs", "tx-pcs";
1523 reset-names = "mac", "pcs";
1526 interconnect-names = "dma-mem", "write";
1528 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
1533 compatible = "nvidia,tegra234-mgbe";
1537 reg-names = "hypervisor", "mac", "xpcs";
1539 interrupt-names = "common";
1552 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1553 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1554 "rx-pcs", "tx-pcs";
1557 reset-names = "mac", "pcs";
1560 interconnect-names = "dma-mem", "write";
1562 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
1567 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
1700 stream-match-mask = <0x7f80>;
1701 #global-interrupts = <2>;
1702 #iommu-cells = <1>;
1704 nvidia,memory-controller = <&mc>;
1708 sce-fabric@b600000 {
1709 compatible = "nvidia,tegra234-sce-fabric";
1715 rce-fabric@be00000 {
1716 compatible = "nvidia,tegra234-rce-fabric";
1723 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
1733 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1734 #mbox-cells = <2>;
1737 hte_aon: hardware-timestamp@c1e0000 {
1738 compatible = "nvidia,tegra234-gte-aon";
1741 nvidia,int-threshold = <1>;
1742 nvidia,gpio-controller = <&gpio_aon>;
1743 #timestamp-cells = <1>;
1747 compatible = "nvidia,tegra194-i2c";
1750 #address-cells = <1>;
1751 #size-cells = <0>;
1753 clock-frequency = <100000>;
1756 clock-names = "div-clk", "parent";
1757 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
1758 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1760 reset-names = "i2c";
1762 dma-names = "rx", "tx";
1766 compatible = "nvidia,tegra194-i2c";
1769 #address-cells = <1>;
1770 #size-cells = <0>;
1772 clock-frequency = <400000>;
1775 clock-names = "div-clk", "parent";
1776 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
1777 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1779 reset-names = "i2c";
1781 dma-names = "rx", "tx";
1785 compatible = "nvidia,tegra210-spi";
1788 #address-cells = <1>;
1789 #size-cells = <0>;
1791 clock-names = "spi";
1793 assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>;
1794 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1796 reset-names = "spi";
1798 dma-names = "rx", "tx";
1799 dma-coherent;
1804 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
1806 interrupt-parent = <&pmc>;
1809 clock-names = "rtc";
1814 compatible = "nvidia,tegra234-gpio-aon";
1815 reg-names = "security", "gpio";
1822 #interrupt-cells = <2>;
1823 interrupt-controller;
1824 #gpio-cells = <2>;
1825 gpio-controller;
1826 gpio-ranges = <&pinmux_aon 0 0 32>;
1829 pinmux_aon: pinmux@c300000 {
1830 compatible = "nvidia,tegra234-pinmux-aon";
1835 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
1839 reset-names = "pwm";
1841 #pwm-cells = <2>;
1845 compatible = "nvidia,tegra234-pmc";
1851 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1853 #interrupt-cells = <2>;
1854 interrupt-controller;
1856 sdmmc1_1v8: sdmmc1-1v8 {
1857 pins = "sdmmc1-hv";
1858 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1861 sdmmc1_3v3: sdmmc1-3v3 {
1862 pins = "sdmmc1-hv";
1863 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1866 sdmmc3_1v8: sdmmc3-1v8 {
1867 pins = "sdmmc3-hv";
1868 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1871 sdmmc3_3v3: sdmmc3-3v3 {
1872 pins = "sdmmc3-hv";
1873 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1877 aon-fabric@c600000 {
1878 compatible = "nvidia,tegra234-aon-fabric";
1884 bpmp-fabric@d600000 {
1885 compatible = "nvidia,tegra234-bpmp-fabric";
1891 dce-fabric@de00000 {
1892 compatible = "nvidia,tegra234-sce-fabric";
1899 compatible = "nvidia,tegra234-ccplex-cluster";
1905 gic: interrupt-controller@f400000 {
1906 compatible = "arm,gic-v3";
1909 interrupt-parent = <&gic>;
1912 #redistributor-regions = <1>;
1913 #interrupt-cells = <3>;
1914 interrupt-controller;
1918 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2049 stream-match-mask = <0x7f80>;
2050 #global-interrupts = <1>;
2051 #iommu-cells = <1>;
2053 nvidia,memory-controller = <&mc>;
2058 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2191 stream-match-mask = <0x7f80>;
2192 #global-interrupts = <2>;
2193 #iommu-cells = <1>;
2195 nvidia,memory-controller = <&mc>;
2199 cbb-fabric@13a00000 {
2200 compatible = "nvidia,tegra234-cbb-fabric";
2207 compatible = "nvidia,tegra234-host1x";
2211 reg-names = "common", "hypervisor", "vm";
2221 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",
2224 clock-names = "host1x";
2226 #address-cells = <2>;
2227 #size-cells = <2>;
2231 interconnect-names = "dma-mem";
2233 dma-coherent;
2236 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
2254 compatible = "nvidia,tegra234-vic";
2258 clock-names = "vic";
2260 reset-names = "vic";
2262 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
2265 interconnect-names = "dma-mem", "write";
2267 dma-coherent;
2271 compatible = "nvidia,tegra234-nvdec";
2276 clock-names = "nvdec", "fuse", "tsec_pka";
2278 reset-names = "nvdec";
2279 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
2282 interconnect-names = "dma-mem", "write";
2284 dma-coherent;
2286 nvidia,memory-controller = <&mc>;
2292 nvidia,bl-manifest-offset = <0>;
2293 nvidia,bl-data-offset = <0>;
2294 nvidia,bl-code-offset = <0>;
2295 nvidia,os-manifest-offset = <0>;
2296 nvidia,os-data-offset = <0>;
2297 nvidia,os-code-offset = <0>;
2308 compatible = "nvidia,tegra234-pcie";
2309 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
2315 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2317 #address-cells = <3>;
2318 #size-cells = <2>;
2320 num-lanes = <4>;
2321 num-viewport = <8>;
2322 linux,pci-domain = <8>;
2325 clock-names = "core";
2329 reset-names = "apb", "core";
2333 interrupt-names = "intr", "msi";
2335 #interrupt-cells = <1>;
2336 interrupt-map-mask = <0 0 0 0>;
2337 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
2341 nvidia,aspm-cmrt-us = <60>;
2342 nvidia,aspm-pwr-on-t-us = <20>;
2343 nvidia,aspm-l0s-entrance-latency-us = <3>;
2345 bus-range = <0x0 0xff>;
2348 …<0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2353 interconnect-names = "dma-mem", "write";
2354 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
2355 iommu-map-mask = <0x0>;
2356 dma-coherent;
2362 compatible = "nvidia,tegra234-pcie";
2363 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
2369 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2371 #address-cells = <3>;
2372 #size-cells = <2>;
2374 num-lanes = <4>;
2375 num-viewport = <8>;
2376 linux,pci-domain = <9>;
2379 clock-names = "core";
2383 reset-names = "apb", "core";
2387 interrupt-names = "intr", "msi";
2389 #interrupt-cells = <1>;
2390 interrupt-map-mask = <0 0 0 0>;
2391 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2395 nvidia,aspm-cmrt-us = <60>;
2396 nvidia,aspm-pwr-on-t-us = <20>;
2397 nvidia,aspm-l0s-entrance-latency-us = <3>;
2399 bus-range = <0x0 0xff>;
2402 …<0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2407 interconnect-names = "dma-mem", "write";
2408 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
2409 iommu-map-mask = <0x0>;
2410 dma-coherent;
2416 compatible = "nvidia,tegra234-pcie";
2417 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2423 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2425 #address-cells = <3>;
2426 #size-cells = <2>;
2428 num-lanes = <4>;
2429 num-viewport = <8>;
2430 linux,pci-domain = <10>;
2433 clock-names = "core";
2437 reset-names = "apb", "core";
2441 interrupt-names = "intr", "msi";
2443 #interrupt-cells = <1>;
2444 interrupt-map-mask = <0 0 0 0>;
2445 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2449 nvidia,aspm-cmrt-us = <60>;
2450 nvidia,aspm-pwr-on-t-us = <20>;
2451 nvidia,aspm-l0s-entrance-latency-us = <3>;
2453 bus-range = <0x0 0xff>;
2456 …<0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2461 interconnect-names = "dma-mem", "write";
2462 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2463 iommu-map-mask = <0x0>;
2464 dma-coherent;
2469 pcie-ep@140e0000 {
2470 compatible = "nvidia,tegra234-pcie-ep";
2471 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2476 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2478 num-lanes = <4>;
2481 clock-names = "core";
2485 reset-names = "apb", "core";
2488 interrupt-names = "intr";
2492 nvidia,enable-ext-refclk;
2493 nvidia,aspm-cmrt-us = <60>;
2494 nvidia,aspm-pwr-on-t-us = <20>;
2495 nvidia,aspm-l0s-entrance-latency-us = <3>;
2499 interconnect-names = "dma-mem", "write";
2500 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2501 iommu-map-mask = <0x0>;
2502 dma-coherent;
2508 compatible = "nvidia,tegra234-pcie";
2509 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2515 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2517 #address-cells = <3>;
2518 #size-cells = <2>;
2520 num-lanes = <1>;
2521 num-viewport = <8>;
2522 linux,pci-domain = <1>;
2525 clock-names = "core";
2529 reset-names = "apb", "core";
2533 interrupt-names = "intr", "msi";
2535 #interrupt-cells = <1>;
2536 interrupt-map-mask = <0 0 0 0>;
2537 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2541 nvidia,aspm-cmrt-us = <60>;
2542 nvidia,aspm-pwr-on-t-us = <20>;
2543 nvidia,aspm-l0s-entrance-latency-us = <3>;
2545 bus-range = <0x0 0xff>;
2548 …<0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2553 interconnect-names = "dma-mem", "write";
2554 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
2555 iommu-map-mask = <0x0>;
2556 dma-coherent;
2562 compatible = "nvidia,tegra234-pcie";
2563 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2569 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2571 #address-cells = <3>;
2572 #size-cells = <2>;
2574 num-lanes = <1>;
2575 num-viewport = <8>;
2576 linux,pci-domain = <2>;
2579 clock-names = "core";
2583 reset-names = "apb", "core";
2587 interrupt-names = "intr", "msi";
2589 #interrupt-cells = <1>;
2590 interrupt-map-mask = <0 0 0 0>;
2591 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2595 nvidia,aspm-cmrt-us = <60>;
2596 nvidia,aspm-pwr-on-t-us = <20>;
2597 nvidia,aspm-l0s-entrance-latency-us = <3>;
2599 bus-range = <0x0 0xff>;
2602 …<0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2607 interconnect-names = "dma-mem", "write";
2608 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
2609 iommu-map-mask = <0x0>;
2610 dma-coherent;
2616 compatible = "nvidia,tegra234-pcie";
2617 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2623 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2625 #address-cells = <3>;
2626 #size-cells = <2>;
2628 num-lanes = <1>;
2629 num-viewport = <8>;
2630 linux,pci-domain = <3>;
2633 clock-names = "core";
2637 reset-names = "apb", "core";
2641 interrupt-names = "intr", "msi";
2643 #interrupt-cells = <1>;
2644 interrupt-map-mask = <0 0 0 0>;
2645 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2649 nvidia,aspm-cmrt-us = <60>;
2650 nvidia,aspm-pwr-on-t-us = <20>;
2651 nvidia,aspm-l0s-entrance-latency-us = <3>;
2653 bus-range = <0x0 0xff>;
2656 …<0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2661 interconnect-names = "dma-mem", "write";
2662 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
2663 iommu-map-mask = <0x0>;
2664 dma-coherent;
2670 compatible = "nvidia,tegra234-pcie";
2671 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
2677 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2679 #address-cells = <3>;
2680 #size-cells = <2>;
2682 num-lanes = <4>;
2683 num-viewport = <8>;
2684 linux,pci-domain = <4>;
2687 clock-names = "core";
2691 reset-names = "apb", "core";
2695 interrupt-names = "intr", "msi";
2697 #interrupt-cells = <1>;
2698 interrupt-map-mask = <0 0 0 0>;
2699 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2703 nvidia,aspm-cmrt-us = <60>;
2704 nvidia,aspm-pwr-on-t-us = <20>;
2705 nvidia,aspm-l0s-entrance-latency-us = <3>;
2707 bus-range = <0x0 0xff>;
2710 …<0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2715 interconnect-names = "dma-mem", "write";
2716 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
2717 iommu-map-mask = <0x0>;
2718 dma-coherent;
2724 compatible = "nvidia,tegra234-pcie";
2725 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
2731 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2733 #address-cells = <3>;
2734 #size-cells = <2>;
2736 num-lanes = <4>;
2737 num-viewport = <8>;
2738 linux,pci-domain = <0>;
2741 clock-names = "core";
2745 reset-names = "apb", "core";
2749 interrupt-names = "intr", "msi";
2751 #interrupt-cells = <1>;
2752 interrupt-map-mask = <0 0 0 0>;
2753 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2757 nvidia,aspm-cmrt-us = <60>;
2758 nvidia,aspm-pwr-on-t-us = <20>;
2759 nvidia,aspm-l0s-entrance-latency-us = <3>;
2761 bus-range = <0x0 0xff>;
2764 …<0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2769 interconnect-names = "dma-mem", "write";
2770 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
2771 iommu-map-mask = <0x0>;
2772 dma-coherent;
2778 compatible = "nvidia,tegra234-pcie";
2779 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2785 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2787 #address-cells = <3>;
2788 #size-cells = <2>;
2790 num-lanes = <8>;
2791 num-viewport = <8>;
2792 linux,pci-domain = <5>;
2795 clock-names = "core";
2799 reset-names = "apb", "core";
2803 interrupt-names = "intr", "msi";
2805 #interrupt-cells = <1>;
2806 interrupt-map-mask = <0 0 0 0>;
2807 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2811 nvidia,aspm-cmrt-us = <60>;
2812 nvidia,aspm-pwr-on-t-us = <20>;
2813 nvidia,aspm-l0s-entrance-latency-us = <3>;
2815 bus-range = <0x0 0xff>;
2818 …<0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2823 interconnect-names = "dma-mem", "write";
2824 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2825 iommu-map-mask = <0x0>;
2826 dma-coherent;
2831 pcie-ep@141a0000 {
2832 compatible = "nvidia,tegra234-pcie-ep";
2833 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2838 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2840 num-lanes = <8>;
2843 clock-names = "core";
2847 reset-names = "apb", "core";
2850 interrupt-names = "intr";
2854 nvidia,enable-ext-refclk;
2855 nvidia,aspm-cmrt-us = <60>;
2856 nvidia,aspm-pwr-on-t-us = <20>;
2857 nvidia,aspm-l0s-entrance-latency-us = <3>;
2861 interconnect-names = "dma-mem", "write";
2862 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2863 iommu-map-mask = <0x0>;
2864 dma-coherent;
2870 compatible = "nvidia,tegra234-pcie";
2871 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2877 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2879 #address-cells = <3>;
2880 #size-cells = <2>;
2882 num-lanes = <4>;
2883 num-viewport = <8>;
2884 linux,pci-domain = <6>;
2887 clock-names = "core";
2891 reset-names = "apb", "core";
2895 interrupt-names = "intr", "msi";
2897 #interrupt-cells = <1>;
2898 interrupt-map-mask = <0 0 0 0>;
2899 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
2903 nvidia,aspm-cmrt-us = <60>;
2904 nvidia,aspm-pwr-on-t-us = <20>;
2905 nvidia,aspm-l0s-entrance-latency-us = <3>;
2907 bus-range = <0x0 0xff>;
2910 …<0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2915 interconnect-names = "dma-mem", "write";
2916 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2917 iommu-map-mask = <0x0>;
2918 dma-coherent;
2923 pcie-ep@141c0000 {
2924 compatible = "nvidia,tegra234-pcie-ep";
2925 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2930 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2932 num-lanes = <4>;
2935 clock-names = "core";
2939 reset-names = "apb", "core";
2942 interrupt-names = "intr";
2946 nvidia,enable-ext-refclk;
2947 nvidia,aspm-cmrt-us = <60>;
2948 nvidia,aspm-pwr-on-t-us = <20>;
2949 nvidia,aspm-l0s-entrance-latency-us = <3>;
2953 interconnect-names = "dma-mem", "write";
2954 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2955 iommu-map-mask = <0x0>;
2956 dma-coherent;
2962 compatible = "nvidia,tegra234-pcie";
2963 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2969 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2971 #address-cells = <3>;
2972 #size-cells = <2>;
2974 num-lanes = <8>;
2975 num-viewport = <8>;
2976 linux,pci-domain = <7>;
2979 clock-names = "core";
2983 reset-names = "apb", "core";
2987 interrupt-names = "intr", "msi";
2989 #interrupt-cells = <1>;
2990 interrupt-map-mask = <0 0 0 0>;
2991 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
2995 nvidia,aspm-cmrt-us = <60>;
2996 nvidia,aspm-pwr-on-t-us = <20>;
2997 nvidia,aspm-l0s-entrance-latency-us = <3>;
2999 bus-range = <0x0 0xff>;
3002 …<0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
3007 interconnect-names = "dma-mem", "write";
3008 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
3009 iommu-map-mask = <0x0>;
3010 dma-coherent;
3015 pcie-ep@141e0000 {
3016 compatible = "nvidia,tegra234-pcie-ep";
3017 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
3022 reg-names = "appl", "atu_dma", "dbi", "addr_space";
3024 num-lanes = <8>;
3027 clock-names = "core";
3031 reset-names = "apb", "core";
3034 interrupt-names = "intr";
3038 nvidia,enable-ext-refclk;
3039 nvidia,aspm-cmrt-us = <60>;
3040 nvidia,aspm-pwr-on-t-us = <20>;
3041 nvidia,aspm-l0s-entrance-latency-us = <3>;
3045 interconnect-names = "dma-mem", "write";
3046 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
3047 iommu-map-mask = <0x0>;
3048 dma-coherent;
3055 compatible = "nvidia,tegra234-sysram", "mmio-sram";
3058 #address-cells = <1>;
3059 #size-cells = <1>;
3062 no-memory-wc;
3066 label = "cpu-bpmp-tx";
3072 label = "cpu-bpmp-rx";
3078 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
3082 #clock-cells = <1>;
3083 #reset-cells = <1>;
3084 #power-domain-cells = <1>;
3089 interconnect-names = "read", "write", "dma-mem", "dma-write";
3093 compatible = "nvidia,tegra186-bpmp-i2c";
3094 nvidia,bpmp-bus-id = <5>;
3095 #address-cells = <1>;
3096 #size-cells = <0>;
3100 compatible = "nvidia,tegra186-bpmp-thermal";
3101 #thermal-sensor-cells = <1>;
3106 #address-cells = <1>;
3107 #size-cells = <0>;
3110 compatible = "arm,cortex-a78";
3114 enable-method = "psci";
3116 operating-points-v2 = <&cl0_opp_tbl>;
3119 i-cache-size = <65536>;
3120 i-cache-line-size = <64>;
3121 i-cache-sets = <256>;
3122 d-cache-size = <65536>;
3123 d-cache-line-size = <64>;
3124 d-cache-sets = <256>;
3125 next-level-cache = <&l2c0_0>;
3129 compatible = "arm,cortex-a78";
3133 enable-method = "psci";
3135 operating-points-v2 = <&cl0_opp_tbl>;
3138 i-cache-size = <65536>;
3139 i-cache-line-size = <64>;
3140 i-cache-sets = <256>;
3141 d-cache-size = <65536>;
3142 d-cache-line-size = <64>;
3143 d-cache-sets = <256>;
3144 next-level-cache = <&l2c0_1>;
3148 compatible = "arm,cortex-a78";
3152 enable-method = "psci";
3154 operating-points-v2 = <&cl0_opp_tbl>;
3157 i-cache-size = <65536>;
3158 i-cache-line-size = <64>;
3159 i-cache-sets = <256>;
3160 d-cache-size = <65536>;
3161 d-cache-line-size = <64>;
3162 d-cache-sets = <256>;
3163 next-level-cache = <&l2c0_2>;
3167 compatible = "arm,cortex-a78";
3171 enable-method = "psci";
3173 operating-points-v2 = <&cl0_opp_tbl>;
3176 i-cache-size = <65536>;
3177 i-cache-line-size = <64>;
3178 i-cache-sets = <256>;
3179 d-cache-size = <65536>;
3180 d-cache-line-size = <64>;
3181 d-cache-sets = <256>;
3182 next-level-cache = <&l2c0_3>;
3186 compatible = "arm,cortex-a78";
3190 enable-method = "psci";
3192 operating-points-v2 = <&cl1_opp_tbl>;
3195 i-cache-size = <65536>;
3196 i-cache-line-size = <64>;
3197 i-cache-sets = <256>;
3198 d-cache-size = <65536>;
3199 d-cache-line-size = <64>;
3200 d-cache-sets = <256>;
3201 next-level-cache = <&l2c1_0>;
3205 compatible = "arm,cortex-a78";
3209 enable-method = "psci";
3211 operating-points-v2 = <&cl1_opp_tbl>;
3214 i-cache-size = <65536>;
3215 i-cache-line-size = <64>;
3216 i-cache-sets = <256>;
3217 d-cache-size = <65536>;
3218 d-cache-line-size = <64>;
3219 d-cache-sets = <256>;
3220 next-level-cache = <&l2c1_1>;
3224 compatible = "arm,cortex-a78";
3228 enable-method = "psci";
3230 operating-points-v2 = <&cl1_opp_tbl>;
3233 i-cache-size = <65536>;
3234 i-cache-line-size = <64>;
3235 i-cache-sets = <256>;
3236 d-cache-size = <65536>;
3237 d-cache-line-size = <64>;
3238 d-cache-sets = <256>;
3239 next-level-cache = <&l2c1_2>;
3243 compatible = "arm,cortex-a78";
3247 enable-method = "psci";
3249 operating-points-v2 = <&cl1_opp_tbl>;
3252 i-cache-size = <65536>;
3253 i-cache-line-size = <64>;
3254 i-cache-sets = <256>;
3255 d-cache-size = <65536>;
3256 d-cache-line-size = <64>;
3257 d-cache-sets = <256>;
3258 next-level-cache = <&l2c1_3>;
3262 compatible = "arm,cortex-a78";
3266 enable-method = "psci";
3268 operating-points-v2 = <&cl2_opp_tbl>;
3271 i-cache-size = <65536>;
3272 i-cache-line-size = <64>;
3273 i-cache-sets = <256>;
3274 d-cache-size = <65536>;
3275 d-cache-line-size = <64>;
3276 d-cache-sets = <256>;
3277 next-level-cache = <&l2c2_0>;
3281 compatible = "arm,cortex-a78";
3285 enable-method = "psci";
3287 operating-points-v2 = <&cl2_opp_tbl>;
3290 i-cache-size = <65536>;
3291 i-cache-line-size = <64>;
3292 i-cache-sets = <256>;
3293 d-cache-size = <65536>;
3294 d-cache-line-size = <64>;
3295 d-cache-sets = <256>;
3296 next-level-cache = <&l2c2_1>;
3300 compatible = "arm,cortex-a78";
3304 enable-method = "psci";
3306 operating-points-v2 = <&cl2_opp_tbl>;
3309 i-cache-size = <65536>;
3310 i-cache-line-size = <64>;
3311 i-cache-sets = <256>;
3312 d-cache-size = <65536>;
3313 d-cache-line-size = <64>;
3314 d-cache-sets = <256>;
3315 next-level-cache = <&l2c2_2>;
3319 compatible = "arm,cortex-a78";
3323 enable-method = "psci";
3325 operating-points-v2 = <&cl2_opp_tbl>;
3328 i-cache-size = <65536>;
3329 i-cache-line-size = <64>;
3330 i-cache-sets = <256>;
3331 d-cache-size = <65536>;
3332 d-cache-line-size = <64>;
3333 d-cache-sets = <256>;
3334 next-level-cache = <&l2c2_3>;
3337 cpu-map {
3393 l2c0_0: l2-cache00 {
3395 cache-size = <262144>;
3396 cache-line-size = <64>;
3397 cache-sets = <512>;
3398 cache-unified;
3399 cache-level = <2>;
3400 next-level-cache = <&l3c0>;
3403 l2c0_1: l2-cache01 {
3405 cache-size = <262144>;
3406 cache-line-size = <64>;
3407 cache-sets = <512>;
3408 cache-unified;
3409 cache-level = <2>;
3410 next-level-cache = <&l3c0>;
3413 l2c0_2: l2-cache02 {
3415 cache-size = <262144>;
3416 cache-line-size = <64>;
3417 cache-sets = <512>;
3418 cache-unified;
3419 cache-level = <2>;
3420 next-level-cache = <&l3c0>;
3423 l2c0_3: l2-cache03 {
3425 cache-size = <262144>;
3426 cache-line-size = <64>;
3427 cache-sets = <512>;
3428 cache-unified;
3429 cache-level = <2>;
3430 next-level-cache = <&l3c0>;
3433 l2c1_0: l2-cache10 {
3435 cache-size = <262144>;
3436 cache-line-size = <64>;
3437 cache-sets = <512>;
3438 cache-unified;
3439 cache-level = <2>;
3440 next-level-cache = <&l3c1>;
3443 l2c1_1: l2-cache11 {
3445 cache-size = <262144>;
3446 cache-line-size = <64>;
3447 cache-sets = <512>;
3448 cache-unified;
3449 cache-level = <2>;
3450 next-level-cache = <&l3c1>;
3453 l2c1_2: l2-cache12 {
3455 cache-size = <262144>;
3456 cache-line-size = <64>;
3457 cache-sets = <512>;
3458 cache-unified;
3459 cache-level = <2>;
3460 next-level-cache = <&l3c1>;
3463 l2c1_3: l2-cache13 {
3465 cache-size = <262144>;
3466 cache-line-size = <64>;
3467 cache-sets = <512>;
3468 cache-unified;
3469 cache-level = <2>;
3470 next-level-cache = <&l3c1>;
3473 l2c2_0: l2-cache20 {
3475 cache-size = <262144>;
3476 cache-line-size = <64>;
3477 cache-sets = <512>;
3478 cache-unified;
3479 cache-level = <2>;
3480 next-level-cache = <&l3c2>;
3483 l2c2_1: l2-cache21 {
3485 cache-size = <262144>;
3486 cache-line-size = <64>;
3487 cache-sets = <512>;
3488 cache-unified;
3489 cache-level = <2>;
3490 next-level-cache = <&l3c2>;
3493 l2c2_2: l2-cache22 {
3495 cache-size = <262144>;
3496 cache-line-size = <64>;
3497 cache-sets = <512>;
3498 cache-unified;
3499 cache-level = <2>;
3500 next-level-cache = <&l3c2>;
3503 l2c2_3: l2-cache23 {
3505 cache-size = <262144>;
3506 cache-line-size = <64>;
3507 cache-sets = <512>;
3508 cache-unified;
3509 cache-level = <2>;
3510 next-level-cache = <&l3c2>;
3513 l3c0: l3-cache0 {
3515 cache-unified;
3516 cache-size = <2097152>;
3517 cache-line-size = <64>;
3518 cache-sets = <2048>;
3519 cache-level = <3>;
3522 l3c1: l3-cache1 {
3524 cache-unified;
3525 cache-size = <2097152>;
3526 cache-line-size = <64>;
3527 cache-sets = <2048>;
3528 cache-level = <3>;
3531 l3c2: l3-cache2 {
3533 cache-unified;
3534 cache-size = <2097152>;
3535 cache-line-size = <64>;
3536 cache-sets = <2048>;
3537 cache-level = <3>;
3541 dsu-pmu0 {
3542 compatible = "arm,dsu-pmu";
3547 dsu-pmu1 {
3548 compatible = "arm,dsu-pmu";
3553 dsu-pmu2 {
3554 compatible = "arm,dsu-pmu";
3560 compatible = "arm,cortex-a78-pmu";
3566 compatible = "arm,psci-1.0";
3572 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
3575 mbox-names = "rx", "tx";
3584 clock-names = "pll_a", "plla_out0";
3585 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
3588 assigned-clock-parents = <0>,
3593 thermal-zones {
3594 cpu-thermal {
3595 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>;
3599 gpu-thermal {
3600 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>;
3604 cv0-thermal {
3605 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>;
3609 cv1-thermal {
3610 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>;
3614 cv2-thermal {
3615 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>;
3619 soc0-thermal {
3620 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>;
3624 soc1-thermal {
3625 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>;
3629 soc2-thermal {
3630 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>;
3634 tj-thermal {
3635 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>;
3641 compatible = "arm,armv8-timer";
3646 interrupt-parent = <&gic>;
3647 always-on;
3650 cl0_opp_tbl: opp-table-cluster0 {
3651 compatible = "operating-points-v2";
3652 opp-shared;
3654 cl0_ch1_opp1: opp-115200000 {
3655 opp-hz = /bits/ 64 <115200000>;
3656 opp-peak-kBps = <816000>;
3659 cl0_ch1_opp2: opp-192000000 {
3660 opp-hz = /bits/ 64 <192000000>;
3661 opp-peak-kBps = <816000>;
3664 cl0_ch1_opp3: opp-268800000 {
3665 opp-hz = /bits/ 64 <268800000>;
3666 opp-peak-kBps = <816000>;
3669 cl0_ch1_opp4: opp-345600000 {
3670 opp-hz = /bits/ 64 <345600000>;
3671 opp-peak-kBps = <816000>;
3674 cl0_ch1_opp5: opp-422400000 {
3675 opp-hz = /bits/ 64 <422400000>;
3676 opp-peak-kBps = <816000>;
3679 cl0_ch1_opp6: opp-499200000 {
3680 opp-hz = /bits/ 64 <499200000>;
3681 opp-peak-kBps = <816000>;
3684 cl0_ch1_opp7: opp-576000000 {
3685 opp-hz = /bits/ 64 <576000000>;
3686 opp-peak-kBps = <816000>;
3689 cl0_ch1_opp8: opp-652800000 {
3690 opp-hz = /bits/ 64 <652800000>;
3691 opp-peak-kBps = <816000>;
3694 cl0_ch1_opp9: opp-729600000 {
3695 opp-hz = /bits/ 64 <729600000>;
3696 opp-peak-kBps = <816000>;
3699 cl0_ch1_opp10: opp-806400000 {
3700 opp-hz = /bits/ 64 <806400000>;
3701 opp-peak-kBps = <816000>;
3704 cl0_ch1_opp11: opp-883200000 {
3705 opp-hz = /bits/ 64 <883200000>;
3706 opp-peak-kBps = <816000>;
3709 cl0_ch1_opp12: opp-960000000 {
3710 opp-hz = /bits/ 64 <960000000>;
3711 opp-peak-kBps = <816000>;
3714 cl0_ch1_opp13: opp-1036800000 {
3715 opp-hz = /bits/ 64 <1036800000>;
3716 opp-peak-kBps = <816000>;
3719 cl0_ch1_opp14: opp-1113600000 {
3720 opp-hz = /bits/ 64 <1113600000>;
3721 opp-peak-kBps = <1632000>;
3724 cl0_ch1_opp15: opp-1190400000 {
3725 opp-hz = /bits/ 64 <1190400000>;
3726 opp-peak-kBps = <1632000>;
3729 cl0_ch1_opp16: opp-1267200000 {
3730 opp-hz = /bits/ 64 <1267200000>;
3731 opp-peak-kBps = <1632000>;
3734 cl0_ch1_opp17: opp-1344000000 {
3735 opp-hz = /bits/ 64 <1344000000>;
3736 opp-peak-kBps = <1632000>;
3739 cl0_ch1_opp18: opp-1420800000 {
3740 opp-hz = /bits/ 64 <1420800000>;
3741 opp-peak-kBps = <1632000>;
3744 cl0_ch1_opp19: opp-1497600000 {
3745 opp-hz = /bits/ 64 <1497600000>;
3746 opp-peak-kBps = <3200000>;
3749 cl0_ch1_opp20: opp-1574400000 {
3750 opp-hz = /bits/ 64 <1574400000>;
3751 opp-peak-kBps = <3200000>;
3754 cl0_ch1_opp21: opp-1651200000 {
3755 opp-hz = /bits/ 64 <1651200000>;
3756 opp-peak-kBps = <3200000>;
3759 cl0_ch1_opp22: opp-1728000000 {
3760 opp-hz = /bits/ 64 <1728000000>;
3761 opp-peak-kBps = <3200000>;
3764 cl0_ch1_opp23: opp-1804800000 {
3765 opp-hz = /bits/ 64 <1804800000>;
3766 opp-peak-kBps = <3200000>;
3769 cl0_ch1_opp24: opp-1881600000 {
3770 opp-hz = /bits/ 64 <1881600000>;
3771 opp-peak-kBps = <3200000>;
3774 cl0_ch1_opp25: opp-1958400000 {
3775 opp-hz = /bits/ 64 <1958400000>;
3776 opp-peak-kBps = <3200000>;
3779 cl0_ch1_opp26: opp-2035200000 {
3780 opp-hz = /bits/ 64 <2035200000>;
3781 opp-peak-kBps = <3200000>;
3784 cl0_ch1_opp27: opp-2112000000 {
3785 opp-hz = /bits/ 64 <2112000000>;
3786 opp-peak-kBps = <6400000>;
3789 cl0_ch1_opp28: opp-2188800000 {
3790 opp-hz = /bits/ 64 <2188800000>;
3791 opp-peak-kBps = <6400000>;
3794 cl0_ch1_opp29: opp-2201600000 {
3795 opp-hz = /bits/ 64 <2201600000>;
3796 opp-peak-kBps = <6400000>;
3800 cl1_opp_tbl: opp-table-cluster1 {
3801 compatible = "operating-points-v2";
3802 opp-shared;
3804 cl1_ch1_opp1: opp-115200000 {
3805 opp-hz = /bits/ 64 <115200000>;
3806 opp-peak-kBps = <816000>;
3809 cl1_ch1_opp2: opp-192000000 {
3810 opp-hz = /bits/ 64 <192000000>;
3811 opp-peak-kBps = <816000>;
3814 cl1_ch1_opp3: opp-268800000 {
3815 opp-hz = /bits/ 64 <268800000>;
3816 opp-peak-kBps = <816000>;
3819 cl1_ch1_opp4: opp-345600000 {
3820 opp-hz = /bits/ 64 <345600000>;
3821 opp-peak-kBps = <816000>;
3824 cl1_ch1_opp5: opp-422400000 {
3825 opp-hz = /bits/ 64 <422400000>;
3826 opp-peak-kBps = <816000>;
3829 cl1_ch1_opp6: opp-499200000 {
3830 opp-hz = /bits/ 64 <499200000>;
3831 opp-peak-kBps = <816000>;
3834 cl1_ch1_opp7: opp-576000000 {
3835 opp-hz = /bits/ 64 <576000000>;
3836 opp-peak-kBps = <816000>;
3839 cl1_ch1_opp8: opp-652800000 {
3840 opp-hz = /bits/ 64 <652800000>;
3841 opp-peak-kBps = <816000>;
3844 cl1_ch1_opp9: opp-729600000 {
3845 opp-hz = /bits/ 64 <729600000>;
3846 opp-peak-kBps = <816000>;
3849 cl1_ch1_opp10: opp-806400000 {
3850 opp-hz = /bits/ 64 <806400000>;
3851 opp-peak-kBps = <816000>;
3854 cl1_ch1_opp11: opp-883200000 {
3855 opp-hz = /bits/ 64 <883200000>;
3856 opp-peak-kBps = <816000>;
3859 cl1_ch1_opp12: opp-960000000 {
3860 opp-hz = /bits/ 64 <960000000>;
3861 opp-peak-kBps = <816000>;
3864 cl1_ch1_opp13: opp-1036800000 {
3865 opp-hz = /bits/ 64 <1036800000>;
3866 opp-peak-kBps = <816000>;
3869 cl1_ch1_opp14: opp-1113600000 {
3870 opp-hz = /bits/ 64 <1113600000>;
3871 opp-peak-kBps = <1632000>;
3874 cl1_ch1_opp15: opp-1190400000 {
3875 opp-hz = /bits/ 64 <1190400000>;
3876 opp-peak-kBps = <1632000>;
3879 cl1_ch1_opp16: opp-1267200000 {
3880 opp-hz = /bits/ 64 <1267200000>;
3881 opp-peak-kBps = <1632000>;
3884 cl1_ch1_opp17: opp-1344000000 {
3885 opp-hz = /bits/ 64 <1344000000>;
3886 opp-peak-kBps = <1632000>;
3889 cl1_ch1_opp18: opp-1420800000 {
3890 opp-hz = /bits/ 64 <1420800000>;
3891 opp-peak-kBps = <1632000>;
3894 cl1_ch1_opp19: opp-1497600000 {
3895 opp-hz = /bits/ 64 <1497600000>;
3896 opp-peak-kBps = <3200000>;
3899 cl1_ch1_opp20: opp-1574400000 {
3900 opp-hz = /bits/ 64 <1574400000>;
3901 opp-peak-kBps = <3200000>;
3904 cl1_ch1_opp21: opp-1651200000 {
3905 opp-hz = /bits/ 64 <1651200000>;
3906 opp-peak-kBps = <3200000>;
3909 cl1_ch1_opp22: opp-1728000000 {
3910 opp-hz = /bits/ 64 <1728000000>;
3911 opp-peak-kBps = <3200000>;
3914 cl1_ch1_opp23: opp-1804800000 {
3915 opp-hz = /bits/ 64 <1804800000>;
3916 opp-peak-kBps = <3200000>;
3919 cl1_ch1_opp24: opp-1881600000 {
3920 opp-hz = /bits/ 64 <1881600000>;
3921 opp-peak-kBps = <3200000>;
3924 cl1_ch1_opp25: opp-1958400000 {
3925 opp-hz = /bits/ 64 <1958400000>;
3926 opp-peak-kBps = <3200000>;
3929 cl1_ch1_opp26: opp-2035200000 {
3930 opp-hz = /bits/ 64 <2035200000>;
3931 opp-peak-kBps = <3200000>;
3934 cl1_ch1_opp27: opp-2112000000 {
3935 opp-hz = /bits/ 64 <2112000000>;
3936 opp-peak-kBps = <6400000>;
3939 cl1_ch1_opp28: opp-2188800000 {
3940 opp-hz = /bits/ 64 <2188800000>;
3941 opp-peak-kBps = <6400000>;
3944 cl1_ch1_opp29: opp-2201600000 {
3945 opp-hz = /bits/ 64 <2201600000>;
3946 opp-peak-kBps = <6400000>;
3950 cl2_opp_tbl: opp-table-cluster2 {
3951 compatible = "operating-points-v2";
3952 opp-shared;
3954 cl2_ch1_opp1: opp-115200000 {
3955 opp-hz = /bits/ 64 <115200000>;
3956 opp-peak-kBps = <816000>;
3959 cl2_ch1_opp2: opp-192000000 {
3960 opp-hz = /bits/ 64 <192000000>;
3961 opp-peak-kBps = <816000>;
3964 cl2_ch1_opp3: opp-268800000 {
3965 opp-hz = /bits/ 64 <268800000>;
3966 opp-peak-kBps = <816000>;
3969 cl2_ch1_opp4: opp-345600000 {
3970 opp-hz = /bits/ 64 <345600000>;
3971 opp-peak-kBps = <816000>;
3974 cl2_ch1_opp5: opp-422400000 {
3975 opp-hz = /bits/ 64 <422400000>;
3976 opp-peak-kBps = <816000>;
3979 cl2_ch1_opp6: opp-499200000 {
3980 opp-hz = /bits/ 64 <499200000>;
3981 opp-peak-kBps = <816000>;
3984 cl2_ch1_opp7: opp-576000000 {
3985 opp-hz = /bits/ 64 <576000000>;
3986 opp-peak-kBps = <816000>;
3989 cl2_ch1_opp8: opp-652800000 {
3990 opp-hz = /bits/ 64 <652800000>;
3991 opp-peak-kBps = <816000>;
3994 cl2_ch1_opp9: opp-729600000 {
3995 opp-hz = /bits/ 64 <729600000>;
3996 opp-peak-kBps = <816000>;
3999 cl2_ch1_opp10: opp-806400000 {
4000 opp-hz = /bits/ 64 <806400000>;
4001 opp-peak-kBps = <816000>;
4004 cl2_ch1_opp11: opp-883200000 {
4005 opp-hz = /bits/ 64 <883200000>;
4006 opp-peak-kBps = <816000>;
4009 cl2_ch1_opp12: opp-960000000 {
4010 opp-hz = /bits/ 64 <960000000>;
4011 opp-peak-kBps = <816000>;
4014 cl2_ch1_opp13: opp-1036800000 {
4015 opp-hz = /bits/ 64 <1036800000>;
4016 opp-peak-kBps = <816000>;
4019 cl2_ch1_opp14: opp-1113600000 {
4020 opp-hz = /bits/ 64 <1113600000>;
4021 opp-peak-kBps = <1632000>;
4024 cl2_ch1_opp15: opp-1190400000 {
4025 opp-hz = /bits/ 64 <1190400000>;
4026 opp-peak-kBps = <1632000>;
4029 cl2_ch1_opp16: opp-1267200000 {
4030 opp-hz = /bits/ 64 <1267200000>;
4031 opp-peak-kBps = <1632000>;
4034 cl2_ch1_opp17: opp-1344000000 {
4035 opp-hz = /bits/ 64 <1344000000>;
4036 opp-peak-kBps = <1632000>;
4039 cl2_ch1_opp18: opp-1420800000 {
4040 opp-hz = /bits/ 64 <1420800000>;
4041 opp-peak-kBps = <1632000>;
4044 cl2_ch1_opp19: opp-1497600000 {
4045 opp-hz = /bits/ 64 <1497600000>;
4046 opp-peak-kBps = <3200000>;
4049 cl2_ch1_opp20: opp-1574400000 {
4050 opp-hz = /bits/ 64 <1574400000>;
4051 opp-peak-kBps = <3200000>;
4054 cl2_ch1_opp21: opp-1651200000 {
4055 opp-hz = /bits/ 64 <1651200000>;
4056 opp-peak-kBps = <3200000>;
4059 cl2_ch1_opp22: opp-1728000000 {
4060 opp-hz = /bits/ 64 <1728000000>;
4061 opp-peak-kBps = <3200000>;
4064 cl2_ch1_opp23: opp-1804800000 {
4065 opp-hz = /bits/ 64 <1804800000>;
4066 opp-peak-kBps = <3200000>;
4069 cl2_ch1_opp24: opp-1881600000 {
4070 opp-hz = /bits/ 64 <1881600000>;
4071 opp-peak-kBps = <3200000>;
4074 cl2_ch1_opp25: opp-1958400000 {
4075 opp-hz = /bits/ 64 <1958400000>;
4076 opp-peak-kBps = <3200000>;
4079 cl2_ch1_opp26: opp-2035200000 {
4080 opp-hz = /bits/ 64 <2035200000>;
4081 opp-peak-kBps = <3200000>;
4084 cl2_ch1_opp27: opp-2112000000 {
4085 opp-hz = /bits/ 64 <2112000000>;
4086 opp-peak-kBps = <6400000>;
4089 cl2_ch1_opp28: opp-2188800000 {
4090 opp-hz = /bits/ 64 <2188800000>;
4091 opp-peak-kBps = <6400000>;
4094 cl2_ch1_opp29: opp-2201600000 {
4095 opp-hz = /bits/ 64 <2201600000>;
4096 opp-peak-kBps = <6400000>;