Lines Matching +full:cpu +full:- +full:bpmp +full:- +full:rx
1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 compatible = "simple-bus";
22 #address-cells = <2>;
23 #size-cells = <2>;
27 compatible = "nvidia,tegra234-misc";
34 compatible = "nvidia,tegra234-timer";
56 compatible = "nvidia,tegra234-gpio";
57 reg-names = "security", "gpio";
108 #interrupt-cells = <2>;
109 interrupt-controller;
110 #gpio-cells = <2>;
111 gpio-controller;
112 gpio-ranges = <&pinmux 0 0 164>;
116 compatible = "nvidia,tegra234-pinmux";
120 gpcdma: dma-controller@2600000 {
121 compatible = "nvidia,tegra234-gpcdma",
122 "nvidia,tegra186-gpcdma";
124 resets = <&bpmp TEGRA234_RESET_GPCDMA>;
125 reset-names = "gpcdma";
158 #dma-cells = <1>;
160 dma-channel-mask = <0xfffffffe>;
161 dma-coherent;
165 compatible = "nvidia,tegra234-aconnect",
166 "nvidia,tegra210-aconnect";
167 clocks = <&bpmp TEGRA234_CLK_APE>,
168 <&bpmp TEGRA234_CLK_APB2APE>;
169 clock-names = "ape", "apb2ape";
170 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
173 #address-cells = <2>;
174 #size-cells = <2>;
178 compatible = "nvidia,tegra234-ahub";
180 clocks = <&bpmp TEGRA234_CLK_AHUB>;
181 clock-names = "ahub";
182 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
183 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
184 assigned-clock-rates = <81600000>;
187 #address-cells = <2>;
188 #size-cells = <2>;
192 compatible = "nvidia,tegra234-i2s",
193 "nvidia,tegra210-i2s";
195 clocks = <&bpmp TEGRA234_CLK_I2S1>,
196 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
197 clock-names = "i2s", "sync_input";
198 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
199 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
200 assigned-clock-rates = <1536000>;
201 sound-name-prefix = "I2S1";
206 compatible = "nvidia,tegra234-i2s",
207 "nvidia,tegra210-i2s";
209 clocks = <&bpmp TEGRA234_CLK_I2S2>,
210 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
211 clock-names = "i2s", "sync_input";
212 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
213 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
214 assigned-clock-rates = <1536000>;
215 sound-name-prefix = "I2S2";
220 compatible = "nvidia,tegra234-i2s",
221 "nvidia,tegra210-i2s";
223 clocks = <&bpmp TEGRA234_CLK_I2S3>,
224 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
225 clock-names = "i2s", "sync_input";
226 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
227 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
228 assigned-clock-rates = <1536000>;
229 sound-name-prefix = "I2S3";
234 compatible = "nvidia,tegra234-i2s",
235 "nvidia,tegra210-i2s";
237 clocks = <&bpmp TEGRA234_CLK_I2S4>,
238 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
239 clock-names = "i2s", "sync_input";
240 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
241 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
242 assigned-clock-rates = <1536000>;
243 sound-name-prefix = "I2S4";
248 compatible = "nvidia,tegra234-i2s",
249 "nvidia,tegra210-i2s";
251 clocks = <&bpmp TEGRA234_CLK_I2S5>,
252 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
253 clock-names = "i2s", "sync_input";
254 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
255 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
256 assigned-clock-rates = <1536000>;
257 sound-name-prefix = "I2S5";
262 compatible = "nvidia,tegra234-i2s",
263 "nvidia,tegra210-i2s";
265 clocks = <&bpmp TEGRA234_CLK_I2S6>,
266 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
267 clock-names = "i2s", "sync_input";
268 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
269 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
270 assigned-clock-rates = <1536000>;
271 sound-name-prefix = "I2S6";
276 compatible = "nvidia,tegra234-sfc",
277 "nvidia,tegra210-sfc";
279 sound-name-prefix = "SFC1";
284 compatible = "nvidia,tegra234-sfc",
285 "nvidia,tegra210-sfc";
287 sound-name-prefix = "SFC2";
292 compatible = "nvidia,tegra234-sfc",
293 "nvidia,tegra210-sfc";
295 sound-name-prefix = "SFC3";
300 compatible = "nvidia,tegra234-sfc",
301 "nvidia,tegra210-sfc";
303 sound-name-prefix = "SFC4";
308 compatible = "nvidia,tegra234-amx",
309 "nvidia,tegra194-amx";
311 sound-name-prefix = "AMX1";
316 compatible = "nvidia,tegra234-amx",
317 "nvidia,tegra194-amx";
319 sound-name-prefix = "AMX2";
324 compatible = "nvidia,tegra234-amx",
325 "nvidia,tegra194-amx";
327 sound-name-prefix = "AMX3";
332 compatible = "nvidia,tegra234-amx",
333 "nvidia,tegra194-amx";
335 sound-name-prefix = "AMX4";
340 compatible = "nvidia,tegra234-adx",
341 "nvidia,tegra210-adx";
343 sound-name-prefix = "ADX1";
348 compatible = "nvidia,tegra234-adx",
349 "nvidia,tegra210-adx";
351 sound-name-prefix = "ADX2";
356 compatible = "nvidia,tegra234-adx",
357 "nvidia,tegra210-adx";
359 sound-name-prefix = "ADX3";
364 compatible = "nvidia,tegra234-adx",
365 "nvidia,tegra210-adx";
367 sound-name-prefix = "ADX4";
373 compatible = "nvidia,tegra234-dmic",
374 "nvidia,tegra210-dmic";
376 clocks = <&bpmp TEGRA234_CLK_DMIC1>;
377 clock-names = "dmic";
378 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
379 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
380 assigned-clock-rates = <3072000>;
381 sound-name-prefix = "DMIC1";
386 compatible = "nvidia,tegra234-dmic",
387 "nvidia,tegra210-dmic";
389 clocks = <&bpmp TEGRA234_CLK_DMIC2>;
390 clock-names = "dmic";
391 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
392 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
393 assigned-clock-rates = <3072000>;
394 sound-name-prefix = "DMIC2";
399 compatible = "nvidia,tegra234-dmic",
400 "nvidia,tegra210-dmic";
402 clocks = <&bpmp TEGRA234_CLK_DMIC3>;
403 clock-names = "dmic";
404 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
405 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
406 assigned-clock-rates = <3072000>;
407 sound-name-prefix = "DMIC3";
412 compatible = "nvidia,tegra234-dmic",
413 "nvidia,tegra210-dmic";
415 clocks = <&bpmp TEGRA234_CLK_DMIC4>;
416 clock-names = "dmic";
417 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
418 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
419 assigned-clock-rates = <3072000>;
420 sound-name-prefix = "DMIC4";
425 compatible = "nvidia,tegra234-dspk",
426 "nvidia,tegra186-dspk";
428 clocks = <&bpmp TEGRA234_CLK_DSPK1>;
429 clock-names = "dspk";
430 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
431 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
432 assigned-clock-rates = <12288000>;
433 sound-name-prefix = "DSPK1";
438 compatible = "nvidia,tegra234-dspk",
439 "nvidia,tegra186-dspk";
441 clocks = <&bpmp TEGRA234_CLK_DSPK2>;
442 clock-names = "dspk";
443 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
444 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
445 assigned-clock-rates = <12288000>;
446 sound-name-prefix = "DSPK2";
450 tegra_ope1: processing-engine@2908000 {
451 compatible = "nvidia,tegra234-ope",
452 "nvidia,tegra210-ope";
454 sound-name-prefix = "OPE1";
457 #address-cells = <2>;
458 #size-cells = <2>;
462 compatible = "nvidia,tegra234-peq",
463 "nvidia,tegra210-peq";
467 dynamic-range-compressor@2908200 {
468 compatible = "nvidia,tegra234-mbdrc",
469 "nvidia,tegra210-mbdrc";
475 compatible = "nvidia,tegra234-mvc",
476 "nvidia,tegra210-mvc";
478 sound-name-prefix = "MVC1";
483 compatible = "nvidia,tegra234-mvc",
484 "nvidia,tegra210-mvc";
486 sound-name-prefix = "MVC2";
491 compatible = "nvidia,tegra234-amixer",
492 "nvidia,tegra210-amixer";
494 sound-name-prefix = "MIXER1";
499 compatible = "nvidia,tegra234-admaif",
500 "nvidia,tegra186-admaif";
522 dma-names = "rx1", "tx1",
544 interconnect-names = "dma-mem", "write";
550 compatible = "nvidia,tegra234-asrc",
551 "nvidia,tegra186-asrc";
553 sound-name-prefix = "ASRC1";
558 adma: dma-controller@2930000 {
559 compatible = "nvidia,tegra234-adma",
560 "nvidia,tegra186-adma";
562 interrupt-parent = <&agic>;
595 #dma-cells = <1>;
596 clocks = <&bpmp TEGRA234_CLK_AHUB>;
597 clock-names = "d_audio";
601 agic: interrupt-controller@2a40000 {
602 compatible = "nvidia,tegra234-agic",
603 "nvidia,tegra210-agic";
604 #interrupt-cells = <3>;
605 interrupt-controller;
611 clocks = <&bpmp TEGRA234_CLK_APE>;
612 clock-names = "clk";
617 mc: memory-controller@2c00000 {
618 compatible = "nvidia,tegra234-mc";
619 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
637 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
641 #interconnect-cells = <1>;
644 #address-cells = <2>;
645 #size-cells = <2>;
665 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
667 emc: external-memory-controller@2c60000 {
668 compatible = "nvidia,tegra234-emc";
672 clocks = <&bpmp TEGRA234_CLK_EMC>;
673 clock-names = "emc";
676 #interconnect-cells = <0>;
678 nvidia,bpmp = <&bpmp>;
683 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
686 clocks = <&bpmp TEGRA234_CLK_UARTA>;
687 resets = <&bpmp TEGRA234_RESET_UARTA>;
692 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
695 clocks = <&bpmp TEGRA234_CLK_UARTE>;
696 resets = <&bpmp TEGRA234_RESET_UARTE>;
701 compatible = "nvidia,tegra194-i2c";
705 #address-cells = <1>;
706 #size-cells = <0>;
707 clock-frequency = <400000>;
708 clocks = <&bpmp TEGRA234_CLK_I2C1
709 &bpmp TEGRA234_CLK_PLLP_OUT0>;
710 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
711 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
712 clock-names = "div-clk", "parent";
713 resets = <&bpmp TEGRA234_RESET_I2C1>;
714 reset-names = "i2c";
716 dma-names = "rx", "tx";
720 compatible = "nvidia,tegra194-i2c";
723 #address-cells = <1>;
724 #size-cells = <0>;
726 clock-frequency = <400000>;
727 clocks = <&bpmp TEGRA234_CLK_I2C3
728 &bpmp TEGRA234_CLK_PLLP_OUT0>;
729 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
730 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
731 clock-names = "div-clk", "parent";
732 resets = <&bpmp TEGRA234_RESET_I2C3>;
733 reset-names = "i2c";
735 dma-names = "rx", "tx";
739 compatible = "nvidia,tegra194-i2c";
742 #address-cells = <1>;
743 #size-cells = <0>;
745 clock-frequency = <100000>;
746 clocks = <&bpmp TEGRA234_CLK_I2C4
747 &bpmp TEGRA234_CLK_PLLP_OUT0>;
748 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
749 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
750 clock-names = "div-clk", "parent";
751 resets = <&bpmp TEGRA234_RESET_I2C4>;
752 reset-names = "i2c";
754 dma-names = "rx", "tx";
758 compatible = "nvidia,tegra194-i2c";
761 #address-cells = <1>;
762 #size-cells = <0>;
764 clock-frequency = <100000>;
765 clocks = <&bpmp TEGRA234_CLK_I2C6
766 &bpmp TEGRA234_CLK_PLLP_OUT0>;
767 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
768 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
769 clock-names = "div-clk", "parent";
770 resets = <&bpmp TEGRA234_RESET_I2C6>;
771 reset-names = "i2c";
773 dma-names = "rx", "tx";
777 compatible = "nvidia,tegra194-i2c";
780 #address-cells = <1>;
781 #size-cells = <0>;
783 clock-frequency = <100000>;
784 clocks = <&bpmp TEGRA234_CLK_I2C7
785 &bpmp TEGRA234_CLK_PLLP_OUT0>;
786 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
787 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
788 clock-names = "div-clk", "parent";
789 resets = <&bpmp TEGRA234_RESET_I2C7>;
790 reset-names = "i2c";
792 dma-names = "rx", "tx";
796 compatible = "arm,sbsa-uart";
803 compatible = "nvidia,tegra194-i2c";
806 #address-cells = <1>;
807 #size-cells = <0>;
809 clock-frequency = <100000>;
810 clocks = <&bpmp TEGRA234_CLK_I2C9
811 &bpmp TEGRA234_CLK_PLLP_OUT0>;
812 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
813 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
814 clock-names = "div-clk", "parent";
815 resets = <&bpmp TEGRA234_RESET_I2C9>;
816 reset-names = "i2c";
818 dma-names = "rx", "tx";
822 compatible = "nvidia,tegra210-spi";
825 #address-cells = <1>;
826 #size-cells = <0>;
827 clocks = <&bpmp TEGRA234_CLK_SPI1>;
828 assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>;
829 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
830 clock-names = "spi";
832 resets = <&bpmp TEGRA234_RESET_SPI1>;
833 reset-names = "spi";
835 dma-names = "rx", "tx";
836 dma-coherent;
841 compatible = "nvidia,tegra210-spi";
844 #address-cells = <1>;
845 #size-cells = <0>;
846 clocks = <&bpmp TEGRA234_CLK_SPI3>;
847 clock-names = "spi";
849 assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>;
850 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
851 resets = <&bpmp TEGRA234_RESET_SPI3>;
852 reset-names = "spi";
854 dma-names = "rx", "tx";
855 dma-coherent;
860 compatible = "nvidia,tegra234-qspi";
863 #address-cells = <1>;
864 #size-cells = <0>;
865 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
866 <&bpmp TEGRA234_CLK_QSPI0_PM>;
867 clock-names = "qspi", "qspi_out";
868 resets = <&bpmp TEGRA234_RESET_QSPI0>;
873 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
875 clocks = <&bpmp TEGRA234_CLK_PWM1>;
876 resets = <&bpmp TEGRA234_RESET_PWM1>;
877 reset-names = "pwm";
879 #pwm-cells = <2>;
883 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
885 clocks = <&bpmp TEGRA234_CLK_PWM2>;
886 resets = <&bpmp TEGRA234_RESET_PWM2>;
887 reset-names = "pwm";
889 #pwm-cells = <2>;
893 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
895 clocks = <&bpmp TEGRA234_CLK_PWM3>;
896 resets = <&bpmp TEGRA234_RESET_PWM3>;
897 reset-names = "pwm";
899 #pwm-cells = <2>;
903 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
905 clocks = <&bpmp TEGRA234_CLK_PWM5>;
906 resets = <&bpmp TEGRA234_RESET_PWM5>;
907 reset-names = "pwm";
909 #pwm-cells = <2>;
913 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
915 clocks = <&bpmp TEGRA234_CLK_PWM6>;
916 resets = <&bpmp TEGRA234_RESET_PWM6>;
917 reset-names = "pwm";
919 #pwm-cells = <2>;
923 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
925 clocks = <&bpmp TEGRA234_CLK_PWM7>;
926 resets = <&bpmp TEGRA234_RESET_PWM7>;
927 reset-names = "pwm";
929 #pwm-cells = <2>;
933 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
935 clocks = <&bpmp TEGRA234_CLK_PWM8>;
936 resets = <&bpmp TEGRA234_RESET_PWM8>;
937 reset-names = "pwm";
939 #pwm-cells = <2>;
943 compatible = "nvidia,tegra234-qspi";
946 #address-cells = <1>;
947 #size-cells = <0>;
948 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
949 <&bpmp TEGRA234_CLK_QSPI1_PM>;
950 clock-names = "qspi", "qspi_out";
951 resets = <&bpmp TEGRA234_RESET_QSPI1>;
956 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
959 clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
960 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
961 clock-names = "sdhci", "tmclk";
962 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
963 <&bpmp TEGRA234_CLK_PLLC4_MUXED>;
964 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
965 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
966 resets = <&bpmp TEGRA234_RESET_SDMMC1>;
967 reset-names = "sdhci";
970 interconnect-names = "dma-mem", "write";
972 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
973 pinctrl-0 = <&sdmmc1_3v3>;
974 pinctrl-1 = <&sdmmc1_1v8>;
975 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
976 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
977 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
978 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
979 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
980 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
981 nvidia,default-tap = <14>;
982 nvidia,default-trim = <0x8>;
983 sd-uhs-sdr25;
984 sd-uhs-sdr50;
985 sd-uhs-ddr50;
986 sd-uhs-sdr104;
991 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
994 clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
995 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
996 clock-names = "sdhci", "tmclk";
997 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
998 <&bpmp TEGRA234_CLK_PLLC4>;
999 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
1000 resets = <&bpmp TEGRA234_RESET_SDMMC4>;
1001 reset-names = "sdhci";
1004 interconnect-names = "dma-mem", "write";
1006 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1007 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1008 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1009 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
1010 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1011 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
1012 nvidia,default-tap = <0x8>;
1013 nvidia,default-trim = <0x14>;
1014 nvidia,dqs-trim = <40>;
1015 supports-cqe;
1020 compatible = "nvidia,tegra234-hda";
1023 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
1024 <&bpmp TEGRA234_CLK_AZA_2XBIT>;
1025 clock-names = "hda", "hda2codec_2x";
1026 resets = <&bpmp TEGRA234_RESET_HDA>,
1027 <&bpmp TEGRA234_RESET_HDACODEC>;
1028 reset-names = "hda", "hda2codec_2x";
1029 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
1032 interconnect-names = "dma-mem", "write";
1038 compatible = "nvidia,tegra234-xusb-padctl";
1041 reg-names = "padctl", "ao";
1044 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>;
1045 reset-names = "padctl";
1051 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>;
1052 clock-names = "trk";
1055 usb2-0 {
1058 #phy-cells = <0>;
1061 usb2-1 {
1064 #phy-cells = <0>;
1067 usb2-2 {
1070 #phy-cells = <0>;
1073 usb2-3 {
1076 #phy-cells = <0>;
1083 usb3-0 {
1086 #phy-cells = <0>;
1089 usb3-1 {
1092 #phy-cells = <0>;
1095 usb3-2 {
1098 #phy-cells = <0>;
1101 usb3-3 {
1104 #phy-cells = <0>;
1111 usb2-0 {
1115 usb2-1 {
1119 usb2-2 {
1123 usb2-3 {
1127 usb3-0 {
1131 usb3-1 {
1135 usb3-2 {
1139 usb3-3 {
1146 compatible = "nvidia,tegra234-xudc";
1149 reg-names = "base", "fpci";
1151 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>,
1152 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
1153 <&bpmp TEGRA234_CLK_XUSB_SS>,
1154 <&bpmp TEGRA234_CLK_XUSB_FS>;
1155 clock-names = "dev", "ss", "ss_src", "fs_src";
1158 interconnect-names = "dma-mem", "write";
1160 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>,
1161 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
1162 power-domain-names = "dev", "ss";
1163 nvidia,xusb-padctl = <&xusb_padctl>;
1164 dma-coherent;
1169 compatible = "nvidia,tegra234-xusb";
1173 reg-names = "hcd", "fpci", "bar2";
1178 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
1179 <&bpmp TEGRA234_CLK_XUSB_FALCON>,
1180 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
1181 <&bpmp TEGRA234_CLK_XUSB_SS>,
1182 <&bpmp TEGRA234_CLK_CLK_M>,
1183 <&bpmp TEGRA234_CLK_XUSB_FS>,
1184 <&bpmp TEGRA234_CLK_UTMIP_PLL>,
1185 <&bpmp TEGRA234_CLK_CLK_M>,
1186 <&bpmp TEGRA234_CLK_PLLE>;
1187 clock-names = "xusb_host", "xusb_falcon_src",
1193 interconnect-names = "dma-mem", "write";
1196 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
1197 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
1198 power-domain-names = "xusb_host", "xusb_ss";
1200 nvidia,xusb-padctl = <&xusb_padctl>;
1201 dma-coherent;
1206 compatible = "nvidia,tegra234-efuse";
1208 clocks = <&bpmp TEGRA234_CLK_FUSE>;
1209 clock-names = "fuse";
1212 hte_lic: hardware-timestamp@3aa0000 {
1213 compatible = "nvidia,tegra234-gte-lic";
1216 nvidia,int-threshold = <1>;
1217 #timestamp-cells = <1>;
1221 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
1232 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1235 #mbox-cells = <2>;
1239 compatible = "nvidia,tegra234-p2u";
1241 reg-names = "ctl";
1243 #phy-cells = <0>;
1247 compatible = "nvidia,tegra234-p2u";
1249 reg-names = "ctl";
1251 #phy-cells = <0>;
1255 compatible = "nvidia,tegra234-p2u";
1257 reg-names = "ctl";
1259 #phy-cells = <0>;
1263 compatible = "nvidia,tegra234-p2u";
1265 reg-names = "ctl";
1267 #phy-cells = <0>;
1271 compatible = "nvidia,tegra234-p2u";
1273 reg-names = "ctl";
1275 #phy-cells = <0>;
1279 compatible = "nvidia,tegra234-p2u";
1281 reg-names = "ctl";
1283 #phy-cells = <0>;
1287 compatible = "nvidia,tegra234-p2u";
1289 reg-names = "ctl";
1291 #phy-cells = <0>;
1295 compatible = "nvidia,tegra234-p2u";
1297 reg-names = "ctl";
1299 #phy-cells = <0>;
1303 compatible = "nvidia,tegra234-p2u";
1305 reg-names = "ctl";
1307 #phy-cells = <0>;
1311 compatible = "nvidia,tegra234-p2u";
1313 reg-names = "ctl";
1315 #phy-cells = <0>;
1319 compatible = "nvidia,tegra234-p2u";
1321 reg-names = "ctl";
1323 #phy-cells = <0>;
1327 compatible = "nvidia,tegra234-p2u";
1329 reg-names = "ctl";
1331 #phy-cells = <0>;
1335 compatible = "nvidia,tegra234-p2u";
1337 reg-names = "ctl";
1339 #phy-cells = <0>;
1343 compatible = "nvidia,tegra234-p2u";
1345 reg-names = "ctl";
1347 #phy-cells = <0>;
1351 compatible = "nvidia,tegra234-p2u";
1353 reg-names = "ctl";
1355 #phy-cells = <0>;
1359 compatible = "nvidia,tegra234-p2u";
1361 reg-names = "ctl";
1363 #phy-cells = <0>;
1367 compatible = "nvidia,tegra234-p2u";
1369 reg-names = "ctl";
1371 #phy-cells = <0>;
1375 compatible = "nvidia,tegra234-p2u";
1377 reg-names = "ctl";
1379 #phy-cells = <0>;
1383 compatible = "nvidia,tegra234-p2u";
1385 reg-names = "ctl";
1387 #phy-cells = <0>;
1391 compatible = "nvidia,tegra234-p2u";
1393 reg-names = "ctl";
1395 #phy-cells = <0>;
1399 compatible = "nvidia,tegra234-p2u";
1401 reg-names = "ctl";
1403 #phy-cells = <0>;
1407 compatible = "nvidia,tegra234-p2u";
1409 reg-names = "ctl";
1411 #phy-cells = <0>;
1415 compatible = "nvidia,tegra234-p2u";
1417 reg-names = "ctl";
1419 #phy-cells = <0>;
1423 compatible = "nvidia,tegra234-p2u";
1425 reg-names = "ctl";
1427 #phy-cells = <0>;
1431 compatible = "nvidia,tegra234-mgbe";
1435 reg-names = "hypervisor", "mac", "xpcs";
1437 interrupt-names = "common";
1438 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
1439 <&bpmp TEGRA234_CLK_MGBE0_MAC>,
1440 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
1441 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
1442 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
1443 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
1444 <&bpmp TEGRA234_CLK_MGBE0_TX>,
1445 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
1446 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
1447 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
1448 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
1449 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
1450 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1451 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1452 "rx-pcs", "tx-pcs";
1453 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
1454 <&bpmp TEGRA234_RESET_MGBE0_PCS>;
1455 reset-names = "mac", "pcs";
1458 interconnect-names = "dma-mem", "write";
1460 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
1465 compatible = "nvidia,tegra234-mgbe";
1469 reg-names = "hypervisor", "mac", "xpcs";
1471 interrupt-names = "common";
1472 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
1473 <&bpmp TEGRA234_CLK_MGBE1_MAC>,
1474 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
1475 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
1476 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
1477 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
1478 <&bpmp TEGRA234_CLK_MGBE1_TX>,
1479 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
1480 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
1481 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
1482 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
1483 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
1484 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1485 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1486 "rx-pcs", "tx-pcs";
1487 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
1488 <&bpmp TEGRA234_RESET_MGBE1_PCS>;
1489 reset-names = "mac", "pcs";
1492 interconnect-names = "dma-mem", "write";
1494 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
1499 compatible = "nvidia,tegra234-mgbe";
1503 reg-names = "hypervisor", "mac", "xpcs";
1505 interrupt-names = "common";
1506 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
1507 <&bpmp TEGRA234_CLK_MGBE2_MAC>,
1508 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
1509 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
1510 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
1511 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
1512 <&bpmp TEGRA234_CLK_MGBE2_TX>,
1513 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
1514 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
1515 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
1516 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
1517 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
1518 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1519 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1520 "rx-pcs", "tx-pcs";
1521 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
1522 <&bpmp TEGRA234_RESET_MGBE2_PCS>;
1523 reset-names = "mac", "pcs";
1526 interconnect-names = "dma-mem", "write";
1528 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
1533 compatible = "nvidia,tegra234-mgbe";
1537 reg-names = "hypervisor", "mac", "xpcs";
1539 interrupt-names = "common";
1540 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
1541 <&bpmp TEGRA234_CLK_MGBE3_MAC>,
1542 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
1543 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
1544 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
1545 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
1546 <&bpmp TEGRA234_CLK_MGBE3_TX>,
1547 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
1548 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
1549 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
1550 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
1551 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
1552 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1553 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1554 "rx-pcs", "tx-pcs";
1555 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
1556 <&bpmp TEGRA234_RESET_MGBE3_PCS>;
1557 reset-names = "mac", "pcs";
1560 interconnect-names = "dma-mem", "write";
1562 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
1567 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
1700 stream-match-mask = <0x7f80>;
1701 #global-interrupts = <2>;
1702 #iommu-cells = <1>;
1704 nvidia,memory-controller = <&mc>;
1708 sce-fabric@b600000 {
1709 compatible = "nvidia,tegra234-sce-fabric";
1715 rce-fabric@be00000 {
1716 compatible = "nvidia,tegra234-rce-fabric";
1723 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
1733 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1734 #mbox-cells = <2>;
1737 hte_aon: hardware-timestamp@c1e0000 {
1738 compatible = "nvidia,tegra234-gte-aon";
1741 nvidia,int-threshold = <1>;
1742 nvidia,gpio-controller = <&gpio_aon>;
1743 #timestamp-cells = <1>;
1747 compatible = "nvidia,tegra194-i2c";
1750 #address-cells = <1>;
1751 #size-cells = <0>;
1753 clock-frequency = <100000>;
1754 clocks = <&bpmp TEGRA234_CLK_I2C2
1755 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1756 clock-names = "div-clk", "parent";
1757 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
1758 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1759 resets = <&bpmp TEGRA234_RESET_I2C2>;
1760 reset-names = "i2c";
1762 dma-names = "rx", "tx";
1766 compatible = "nvidia,tegra194-i2c";
1769 #address-cells = <1>;
1770 #size-cells = <0>;
1772 clock-frequency = <400000>;
1773 clocks = <&bpmp TEGRA234_CLK_I2C8
1774 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1775 clock-names = "div-clk", "parent";
1776 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
1777 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1778 resets = <&bpmp TEGRA234_RESET_I2C8>;
1779 reset-names = "i2c";
1781 dma-names = "rx", "tx";
1785 compatible = "nvidia,tegra210-spi";
1788 #address-cells = <1>;
1789 #size-cells = <0>;
1790 clocks = <&bpmp TEGRA234_CLK_SPI2>;
1791 clock-names = "spi";
1793 assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>;
1794 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1795 resets = <&bpmp TEGRA234_RESET_SPI2>;
1796 reset-names = "spi";
1798 dma-names = "rx", "tx";
1799 dma-coherent;
1804 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
1806 interrupt-parent = <&pmc>;
1808 clocks = <&bpmp TEGRA234_CLK_CLK_32K>;
1809 clock-names = "rtc";
1814 compatible = "nvidia,tegra234-gpio-aon";
1815 reg-names = "security", "gpio";
1822 #interrupt-cells = <2>;
1823 interrupt-controller;
1824 #gpio-cells = <2>;
1825 gpio-controller;
1826 gpio-ranges = <&pinmux_aon 0 0 32>;
1830 compatible = "nvidia,tegra234-pinmux-aon";
1835 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
1837 clocks = <&bpmp TEGRA234_CLK_PWM4>;
1838 resets = <&bpmp TEGRA234_RESET_PWM4>;
1839 reset-names = "pwm";
1841 #pwm-cells = <2>;
1845 compatible = "nvidia,tegra234-pmc";
1851 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1853 #interrupt-cells = <2>;
1854 interrupt-controller;
1856 sdmmc1_1v8: sdmmc1-1v8 {
1857 pins = "sdmmc1-hv";
1858 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1861 sdmmc1_3v3: sdmmc1-3v3 {
1862 pins = "sdmmc1-hv";
1863 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1866 sdmmc3_1v8: sdmmc3-1v8 {
1867 pins = "sdmmc3-hv";
1868 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1871 sdmmc3_3v3: sdmmc3-3v3 {
1872 pins = "sdmmc3-hv";
1873 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1877 aon-fabric@c600000 {
1878 compatible = "nvidia,tegra234-aon-fabric";
1884 bpmp-fabric@d600000 {
1885 compatible = "nvidia,tegra234-bpmp-fabric";
1891 dce-fabric@de00000 {
1892 compatible = "nvidia,tegra234-dce-fabric";
1899 compatible = "nvidia,tegra234-ccplex-cluster";
1901 nvidia,bpmp = <&bpmp>;
1905 gic: interrupt-controller@f400000 {
1906 compatible = "arm,gic-v3";
1909 interrupt-parent = <&gic>;
1912 #redistributor-regions = <1>;
1913 #interrupt-cells = <3>;
1914 interrupt-controller;
1916 #address-cells = <0>;
1920 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2051 stream-match-mask = <0x7f80>;
2052 #global-interrupts = <1>;
2053 #iommu-cells = <1>;
2055 nvidia,memory-controller = <&mc>;
2060 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2193 stream-match-mask = <0x7f80>;
2194 #global-interrupts = <2>;
2195 #iommu-cells = <1>;
2197 nvidia,memory-controller = <&mc>;
2201 cbb-fabric@13a00000 {
2202 compatible = "nvidia,tegra234-cbb-fabric";
2209 compatible = "nvidia,tegra234-host1x";
2213 reg-names = "common", "hypervisor", "vm";
2223 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",
2225 clocks = <&bpmp TEGRA234_CLK_HOST1X>;
2226 clock-names = "host1x";
2228 #address-cells = <2>;
2229 #size-cells = <2>;
2233 interconnect-names = "dma-mem";
2235 dma-coherent;
2238 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
2256 compatible = "nvidia,tegra234-vic";
2259 clocks = <&bpmp TEGRA234_CLK_VIC>;
2260 clock-names = "vic";
2261 resets = <&bpmp TEGRA234_RESET_VIC>;
2262 reset-names = "vic";
2264 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
2267 interconnect-names = "dma-mem", "write";
2269 dma-coherent;
2273 compatible = "nvidia,tegra234-nvdec";
2275 clocks = <&bpmp TEGRA234_CLK_NVDEC>,
2276 <&bpmp TEGRA234_CLK_FUSE>,
2277 <&bpmp TEGRA234_CLK_TSEC_PKA>;
2278 clock-names = "nvdec", "fuse", "tsec_pka";
2279 resets = <&bpmp TEGRA234_RESET_NVDEC>;
2280 reset-names = "nvdec";
2281 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
2284 interconnect-names = "dma-mem", "write";
2286 dma-coherent;
2288 nvidia,memory-controller = <&mc>;
2294 nvidia,bl-manifest-offset = <0>;
2295 nvidia,bl-data-offset = <0>;
2296 nvidia,bl-code-offset = <0>;
2297 nvidia,os-manifest-offset = <0>;
2298 nvidia,os-data-offset = <0>;
2299 nvidia,os-code-offset = <0>;
2310 compatible = "nvidia,tegra234-pcie";
2311 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
2317 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2319 #address-cells = <3>;
2320 #size-cells = <2>;
2322 num-lanes = <4>;
2323 num-viewport = <8>;
2324 linux,pci-domain = <8>;
2326 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>;
2327 clock-names = "core";
2329 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>,
2330 <&bpmp TEGRA234_RESET_PEX2_CORE_8>;
2331 reset-names = "apb", "core";
2335 interrupt-names = "intr", "msi";
2337 #interrupt-cells = <1>;
2338 interrupt-map-mask = <0 0 0 0>;
2339 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
2341 nvidia,bpmp = <&bpmp 8>;
2343 nvidia,aspm-cmrt-us = <60>;
2344 nvidia,aspm-pwr-on-t-us = <20>;
2345 nvidia,aspm-l0s-entrance-latency-us = <3>;
2347 bus-range = <0x0 0xff>;
2350 …<0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2355 interconnect-names = "dma-mem", "write";
2356 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
2357 iommu-map-mask = <0x0>;
2358 dma-coherent;
2364 compatible = "nvidia,tegra234-pcie";
2365 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
2371 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2373 #address-cells = <3>;
2374 #size-cells = <2>;
2376 num-lanes = <4>;
2377 num-viewport = <8>;
2378 linux,pci-domain = <9>;
2380 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>;
2381 clock-names = "core";
2383 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>,
2384 <&bpmp TEGRA234_RESET_PEX2_CORE_9>;
2385 reset-names = "apb", "core";
2389 interrupt-names = "intr", "msi";
2391 #interrupt-cells = <1>;
2392 interrupt-map-mask = <0 0 0 0>;
2393 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2395 nvidia,bpmp = <&bpmp 9>;
2397 nvidia,aspm-cmrt-us = <60>;
2398 nvidia,aspm-pwr-on-t-us = <20>;
2399 nvidia,aspm-l0s-entrance-latency-us = <3>;
2401 bus-range = <0x0 0xff>;
2404 …<0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2409 interconnect-names = "dma-mem", "write";
2410 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
2411 iommu-map-mask = <0x0>;
2412 dma-coherent;
2418 compatible = "nvidia,tegra234-pcie";
2419 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2425 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2427 #address-cells = <3>;
2428 #size-cells = <2>;
2430 num-lanes = <4>;
2431 num-viewport = <8>;
2432 linux,pci-domain = <10>;
2434 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2435 clock-names = "core";
2437 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2438 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2439 reset-names = "apb", "core";
2443 interrupt-names = "intr", "msi";
2445 #interrupt-cells = <1>;
2446 interrupt-map-mask = <0 0 0 0>;
2447 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2449 nvidia,bpmp = <&bpmp 10>;
2451 nvidia,aspm-cmrt-us = <60>;
2452 nvidia,aspm-pwr-on-t-us = <20>;
2453 nvidia,aspm-l0s-entrance-latency-us = <3>;
2455 bus-range = <0x0 0xff>;
2458 …<0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2463 interconnect-names = "dma-mem", "write";
2464 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2465 iommu-map-mask = <0x0>;
2466 dma-coherent;
2471 pcie-ep@140e0000 {
2472 compatible = "nvidia,tegra234-pcie-ep";
2473 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2478 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2480 num-lanes = <4>;
2482 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2483 clock-names = "core";
2485 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2486 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2487 reset-names = "apb", "core";
2490 interrupt-names = "intr";
2492 nvidia,bpmp = <&bpmp 10>;
2494 nvidia,enable-ext-refclk;
2495 nvidia,aspm-cmrt-us = <60>;
2496 nvidia,aspm-pwr-on-t-us = <20>;
2497 nvidia,aspm-l0s-entrance-latency-us = <3>;
2501 interconnect-names = "dma-mem", "write";
2502 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2503 iommu-map-mask = <0x0>;
2504 dma-coherent;
2510 compatible = "nvidia,tegra234-pcie";
2511 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2517 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2519 #address-cells = <3>;
2520 #size-cells = <2>;
2522 num-lanes = <1>;
2523 num-viewport = <8>;
2524 linux,pci-domain = <1>;
2526 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>;
2527 clock-names = "core";
2529 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>,
2530 <&bpmp TEGRA234_RESET_PEX0_CORE_1>;
2531 reset-names = "apb", "core";
2535 interrupt-names = "intr", "msi";
2537 #interrupt-cells = <1>;
2538 interrupt-map-mask = <0 0 0 0>;
2539 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2541 nvidia,bpmp = <&bpmp 1>;
2543 nvidia,aspm-cmrt-us = <60>;
2544 nvidia,aspm-pwr-on-t-us = <20>;
2545 nvidia,aspm-l0s-entrance-latency-us = <3>;
2547 bus-range = <0x0 0xff>;
2550 …<0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2555 interconnect-names = "dma-mem", "write";
2556 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
2557 iommu-map-mask = <0x0>;
2558 dma-coherent;
2564 compatible = "nvidia,tegra234-pcie";
2565 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2571 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2573 #address-cells = <3>;
2574 #size-cells = <2>;
2576 num-lanes = <1>;
2577 num-viewport = <8>;
2578 linux,pci-domain = <2>;
2580 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>;
2581 clock-names = "core";
2583 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>,
2584 <&bpmp TEGRA234_RESET_PEX0_CORE_2>;
2585 reset-names = "apb", "core";
2589 interrupt-names = "intr", "msi";
2591 #interrupt-cells = <1>;
2592 interrupt-map-mask = <0 0 0 0>;
2593 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2595 nvidia,bpmp = <&bpmp 2>;
2597 nvidia,aspm-cmrt-us = <60>;
2598 nvidia,aspm-pwr-on-t-us = <20>;
2599 nvidia,aspm-l0s-entrance-latency-us = <3>;
2601 bus-range = <0x0 0xff>;
2604 …<0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2609 interconnect-names = "dma-mem", "write";
2610 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
2611 iommu-map-mask = <0x0>;
2612 dma-coherent;
2618 compatible = "nvidia,tegra234-pcie";
2619 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2625 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2627 #address-cells = <3>;
2628 #size-cells = <2>;
2630 num-lanes = <1>;
2631 num-viewport = <8>;
2632 linux,pci-domain = <3>;
2634 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>;
2635 clock-names = "core";
2637 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>,
2638 <&bpmp TEGRA234_RESET_PEX0_CORE_3>;
2639 reset-names = "apb", "core";
2643 interrupt-names = "intr", "msi";
2645 #interrupt-cells = <1>;
2646 interrupt-map-mask = <0 0 0 0>;
2647 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2649 nvidia,bpmp = <&bpmp 3>;
2651 nvidia,aspm-cmrt-us = <60>;
2652 nvidia,aspm-pwr-on-t-us = <20>;
2653 nvidia,aspm-l0s-entrance-latency-us = <3>;
2655 bus-range = <0x0 0xff>;
2658 …<0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2663 interconnect-names = "dma-mem", "write";
2664 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
2665 iommu-map-mask = <0x0>;
2666 dma-coherent;
2672 compatible = "nvidia,tegra234-pcie";
2673 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
2679 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2681 #address-cells = <3>;
2682 #size-cells = <2>;
2684 num-lanes = <4>;
2685 num-viewport = <8>;
2686 linux,pci-domain = <4>;
2688 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
2689 clock-names = "core";
2691 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
2692 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
2693 reset-names = "apb", "core";
2697 interrupt-names = "intr", "msi";
2699 #interrupt-cells = <1>;
2700 interrupt-map-mask = <0 0 0 0>;
2701 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2703 nvidia,bpmp = <&bpmp 4>;
2705 nvidia,aspm-cmrt-us = <60>;
2706 nvidia,aspm-pwr-on-t-us = <20>;
2707 nvidia,aspm-l0s-entrance-latency-us = <3>;
2709 bus-range = <0x0 0xff>;
2712 …<0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2717 interconnect-names = "dma-mem", "write";
2718 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
2719 iommu-map-mask = <0x0>;
2720 dma-coherent;
2726 compatible = "nvidia,tegra234-pcie";
2727 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
2733 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2735 #address-cells = <3>;
2736 #size-cells = <2>;
2738 num-lanes = <4>;
2739 num-viewport = <8>;
2740 linux,pci-domain = <0>;
2742 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>;
2743 clock-names = "core";
2745 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>,
2746 <&bpmp TEGRA234_RESET_PEX0_CORE_0>;
2747 reset-names = "apb", "core";
2751 interrupt-names = "intr", "msi";
2753 #interrupt-cells = <1>;
2754 interrupt-map-mask = <0 0 0 0>;
2755 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2757 nvidia,bpmp = <&bpmp 0>;
2759 nvidia,aspm-cmrt-us = <60>;
2760 nvidia,aspm-pwr-on-t-us = <20>;
2761 nvidia,aspm-l0s-entrance-latency-us = <3>;
2763 bus-range = <0x0 0xff>;
2766 …<0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2771 interconnect-names = "dma-mem", "write";
2772 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
2773 iommu-map-mask = <0x0>;
2774 dma-coherent;
2780 compatible = "nvidia,tegra234-pcie";
2781 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2787 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2789 #address-cells = <3>;
2790 #size-cells = <2>;
2792 num-lanes = <8>;
2793 num-viewport = <8>;
2794 linux,pci-domain = <5>;
2796 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2797 clock-names = "core";
2799 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2800 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2801 reset-names = "apb", "core";
2805 interrupt-names = "intr", "msi";
2807 #interrupt-cells = <1>;
2808 interrupt-map-mask = <0 0 0 0>;
2809 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2811 nvidia,bpmp = <&bpmp 5>;
2813 nvidia,aspm-cmrt-us = <60>;
2814 nvidia,aspm-pwr-on-t-us = <20>;
2815 nvidia,aspm-l0s-entrance-latency-us = <3>;
2817 bus-range = <0x0 0xff>;
2820 …<0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2825 interconnect-names = "dma-mem", "write";
2826 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2827 iommu-map-mask = <0x0>;
2828 dma-coherent;
2833 pcie-ep@141a0000 {
2834 compatible = "nvidia,tegra234-pcie-ep";
2835 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2840 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2842 num-lanes = <8>;
2844 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2845 clock-names = "core";
2847 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2848 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2849 reset-names = "apb", "core";
2852 interrupt-names = "intr";
2854 nvidia,bpmp = <&bpmp 5>;
2856 nvidia,enable-ext-refclk;
2857 nvidia,aspm-cmrt-us = <60>;
2858 nvidia,aspm-pwr-on-t-us = <20>;
2859 nvidia,aspm-l0s-entrance-latency-us = <3>;
2863 interconnect-names = "dma-mem", "write";
2864 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2865 iommu-map-mask = <0x0>;
2866 dma-coherent;
2872 compatible = "nvidia,tegra234-pcie";
2873 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2879 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2881 #address-cells = <3>;
2882 #size-cells = <2>;
2884 num-lanes = <4>;
2885 num-viewport = <8>;
2886 linux,pci-domain = <6>;
2888 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2889 clock-names = "core";
2891 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2892 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2893 reset-names = "apb", "core";
2897 interrupt-names = "intr", "msi";
2899 #interrupt-cells = <1>;
2900 interrupt-map-mask = <0 0 0 0>;
2901 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
2903 nvidia,bpmp = <&bpmp 6>;
2905 nvidia,aspm-cmrt-us = <60>;
2906 nvidia,aspm-pwr-on-t-us = <20>;
2907 nvidia,aspm-l0s-entrance-latency-us = <3>;
2909 bus-range = <0x0 0xff>;
2912 …<0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2917 interconnect-names = "dma-mem", "write";
2918 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2919 iommu-map-mask = <0x0>;
2920 dma-coherent;
2925 pcie-ep@141c0000 {
2926 compatible = "nvidia,tegra234-pcie-ep";
2927 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2932 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2934 num-lanes = <4>;
2936 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2937 clock-names = "core";
2939 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2940 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2941 reset-names = "apb", "core";
2944 interrupt-names = "intr";
2946 nvidia,bpmp = <&bpmp 6>;
2948 nvidia,enable-ext-refclk;
2949 nvidia,aspm-cmrt-us = <60>;
2950 nvidia,aspm-pwr-on-t-us = <20>;
2951 nvidia,aspm-l0s-entrance-latency-us = <3>;
2955 interconnect-names = "dma-mem", "write";
2956 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2957 iommu-map-mask = <0x0>;
2958 dma-coherent;
2964 compatible = "nvidia,tegra234-pcie";
2965 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2971 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2973 #address-cells = <3>;
2974 #size-cells = <2>;
2976 num-lanes = <8>;
2977 num-viewport = <8>;
2978 linux,pci-domain = <7>;
2980 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2981 clock-names = "core";
2983 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2984 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2985 reset-names = "apb", "core";
2989 interrupt-names = "intr", "msi";
2991 #interrupt-cells = <1>;
2992 interrupt-map-mask = <0 0 0 0>;
2993 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
2995 nvidia,bpmp = <&bpmp 7>;
2997 nvidia,aspm-cmrt-us = <60>;
2998 nvidia,aspm-pwr-on-t-us = <20>;
2999 nvidia,aspm-l0s-entrance-latency-us = <3>;
3001 bus-range = <0x0 0xff>;
3004 …<0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
3009 interconnect-names = "dma-mem", "write";
3010 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
3011 iommu-map-mask = <0x0>;
3012 dma-coherent;
3017 pcie-ep@141e0000 {
3018 compatible = "nvidia,tegra234-pcie-ep";
3019 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
3024 reg-names = "appl", "atu_dma", "dbi", "addr_space";
3026 num-lanes = <8>;
3028 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
3029 clock-names = "core";
3031 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
3032 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
3033 reset-names = "apb", "core";
3036 interrupt-names = "intr";
3038 nvidia,bpmp = <&bpmp 7>;
3040 nvidia,enable-ext-refclk;
3041 nvidia,aspm-cmrt-us = <60>;
3042 nvidia,aspm-pwr-on-t-us = <20>;
3043 nvidia,aspm-l0s-entrance-latency-us = <3>;
3047 interconnect-names = "dma-mem", "write";
3048 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
3049 iommu-map-mask = <0x0>;
3050 dma-coherent;
3057 compatible = "nvidia,tegra234-sysram", "mmio-sram";
3060 #address-cells = <1>;
3061 #size-cells = <1>;
3064 no-memory-wc;
3068 label = "cpu-bpmp-tx";
3074 label = "cpu-bpmp-rx";
3079 bpmp: bpmp { label
3080 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
3084 #clock-cells = <1>;
3085 #reset-cells = <1>;
3086 #power-domain-cells = <1>;
3091 interconnect-names = "read", "write", "dma-mem", "dma-write";
3095 compatible = "nvidia,tegra186-bpmp-i2c";
3096 nvidia,bpmp-bus-id = <5>;
3097 #address-cells = <1>;
3098 #size-cells = <0>;
3102 compatible = "nvidia,tegra186-bpmp-thermal";
3103 #thermal-sensor-cells = <1>;
3108 #address-cells = <1>;
3109 #size-cells = <0>;
3111 cpu0_0: cpu@0 {
3112 compatible = "arm,cortex-a78";
3113 device_type = "cpu";
3116 enable-method = "psci";
3118 operating-points-v2 = <&cl0_opp_tbl>;
3121 i-cache-size = <65536>;
3122 i-cache-line-size = <64>;
3123 i-cache-sets = <256>;
3124 d-cache-size = <65536>;
3125 d-cache-line-size = <64>;
3126 d-cache-sets = <256>;
3127 next-level-cache = <&l2c0_0>;
3130 cpu0_1: cpu@100 {
3131 compatible = "arm,cortex-a78";
3132 device_type = "cpu";
3135 enable-method = "psci";
3137 operating-points-v2 = <&cl0_opp_tbl>;
3140 i-cache-size = <65536>;
3141 i-cache-line-size = <64>;
3142 i-cache-sets = <256>;
3143 d-cache-size = <65536>;
3144 d-cache-line-size = <64>;
3145 d-cache-sets = <256>;
3146 next-level-cache = <&l2c0_1>;
3149 cpu0_2: cpu@200 {
3150 compatible = "arm,cortex-a78";
3151 device_type = "cpu";
3154 enable-method = "psci";
3156 operating-points-v2 = <&cl0_opp_tbl>;
3159 i-cache-size = <65536>;
3160 i-cache-line-size = <64>;
3161 i-cache-sets = <256>;
3162 d-cache-size = <65536>;
3163 d-cache-line-size = <64>;
3164 d-cache-sets = <256>;
3165 next-level-cache = <&l2c0_2>;
3168 cpu0_3: cpu@300 {
3169 compatible = "arm,cortex-a78";
3170 device_type = "cpu";
3173 enable-method = "psci";
3175 operating-points-v2 = <&cl0_opp_tbl>;
3178 i-cache-size = <65536>;
3179 i-cache-line-size = <64>;
3180 i-cache-sets = <256>;
3181 d-cache-size = <65536>;
3182 d-cache-line-size = <64>;
3183 d-cache-sets = <256>;
3184 next-level-cache = <&l2c0_3>;
3187 cpu1_0: cpu@10000 {
3188 compatible = "arm,cortex-a78";
3189 device_type = "cpu";
3192 enable-method = "psci";
3194 operating-points-v2 = <&cl1_opp_tbl>;
3197 i-cache-size = <65536>;
3198 i-cache-line-size = <64>;
3199 i-cache-sets = <256>;
3200 d-cache-size = <65536>;
3201 d-cache-line-size = <64>;
3202 d-cache-sets = <256>;
3203 next-level-cache = <&l2c1_0>;
3206 cpu1_1: cpu@10100 {
3207 compatible = "arm,cortex-a78";
3208 device_type = "cpu";
3211 enable-method = "psci";
3213 operating-points-v2 = <&cl1_opp_tbl>;
3216 i-cache-size = <65536>;
3217 i-cache-line-size = <64>;
3218 i-cache-sets = <256>;
3219 d-cache-size = <65536>;
3220 d-cache-line-size = <64>;
3221 d-cache-sets = <256>;
3222 next-level-cache = <&l2c1_1>;
3225 cpu1_2: cpu@10200 {
3226 compatible = "arm,cortex-a78";
3227 device_type = "cpu";
3230 enable-method = "psci";
3232 operating-points-v2 = <&cl1_opp_tbl>;
3235 i-cache-size = <65536>;
3236 i-cache-line-size = <64>;
3237 i-cache-sets = <256>;
3238 d-cache-size = <65536>;
3239 d-cache-line-size = <64>;
3240 d-cache-sets = <256>;
3241 next-level-cache = <&l2c1_2>;
3244 cpu1_3: cpu@10300 {
3245 compatible = "arm,cortex-a78";
3246 device_type = "cpu";
3249 enable-method = "psci";
3251 operating-points-v2 = <&cl1_opp_tbl>;
3254 i-cache-size = <65536>;
3255 i-cache-line-size = <64>;
3256 i-cache-sets = <256>;
3257 d-cache-size = <65536>;
3258 d-cache-line-size = <64>;
3259 d-cache-sets = <256>;
3260 next-level-cache = <&l2c1_3>;
3263 cpu2_0: cpu@20000 {
3264 compatible = "arm,cortex-a78";
3265 device_type = "cpu";
3268 enable-method = "psci";
3270 operating-points-v2 = <&cl2_opp_tbl>;
3273 i-cache-size = <65536>;
3274 i-cache-line-size = <64>;
3275 i-cache-sets = <256>;
3276 d-cache-size = <65536>;
3277 d-cache-line-size = <64>;
3278 d-cache-sets = <256>;
3279 next-level-cache = <&l2c2_0>;
3282 cpu2_1: cpu@20100 {
3283 compatible = "arm,cortex-a78";
3284 device_type = "cpu";
3287 enable-method = "psci";
3289 operating-points-v2 = <&cl2_opp_tbl>;
3292 i-cache-size = <65536>;
3293 i-cache-line-size = <64>;
3294 i-cache-sets = <256>;
3295 d-cache-size = <65536>;
3296 d-cache-line-size = <64>;
3297 d-cache-sets = <256>;
3298 next-level-cache = <&l2c2_1>;
3301 cpu2_2: cpu@20200 {
3302 compatible = "arm,cortex-a78";
3303 device_type = "cpu";
3306 enable-method = "psci";
3308 operating-points-v2 = <&cl2_opp_tbl>;
3311 i-cache-size = <65536>;
3312 i-cache-line-size = <64>;
3313 i-cache-sets = <256>;
3314 d-cache-size = <65536>;
3315 d-cache-line-size = <64>;
3316 d-cache-sets = <256>;
3317 next-level-cache = <&l2c2_2>;
3320 cpu2_3: cpu@20300 {
3321 compatible = "arm,cortex-a78";
3322 device_type = "cpu";
3325 enable-method = "psci";
3327 operating-points-v2 = <&cl2_opp_tbl>;
3330 i-cache-size = <65536>;
3331 i-cache-line-size = <64>;
3332 i-cache-sets = <256>;
3333 d-cache-size = <65536>;
3334 d-cache-line-size = <64>;
3335 d-cache-sets = <256>;
3336 next-level-cache = <&l2c2_3>;
3339 cpu-map {
3342 cpu = <&cpu0_0>;
3346 cpu = <&cpu0_1>;
3350 cpu = <&cpu0_2>;
3354 cpu = <&cpu0_3>;
3360 cpu = <&cpu1_0>;
3364 cpu = <&cpu1_1>;
3368 cpu = <&cpu1_2>;
3372 cpu = <&cpu1_3>;
3378 cpu = <&cpu2_0>;
3382 cpu = <&cpu2_1>;
3386 cpu = <&cpu2_2>;
3390 cpu = <&cpu2_3>;
3395 l2c0_0: l2-cache00 {
3397 cache-size = <262144>;
3398 cache-line-size = <64>;
3399 cache-sets = <512>;
3400 cache-unified;
3401 cache-level = <2>;
3402 next-level-cache = <&l3c0>;
3405 l2c0_1: l2-cache01 {
3407 cache-size = <262144>;
3408 cache-line-size = <64>;
3409 cache-sets = <512>;
3410 cache-unified;
3411 cache-level = <2>;
3412 next-level-cache = <&l3c0>;
3415 l2c0_2: l2-cache02 {
3417 cache-size = <262144>;
3418 cache-line-size = <64>;
3419 cache-sets = <512>;
3420 cache-unified;
3421 cache-level = <2>;
3422 next-level-cache = <&l3c0>;
3425 l2c0_3: l2-cache03 {
3427 cache-size = <262144>;
3428 cache-line-size = <64>;
3429 cache-sets = <512>;
3430 cache-unified;
3431 cache-level = <2>;
3432 next-level-cache = <&l3c0>;
3435 l2c1_0: l2-cache10 {
3437 cache-size = <262144>;
3438 cache-line-size = <64>;
3439 cache-sets = <512>;
3440 cache-unified;
3441 cache-level = <2>;
3442 next-level-cache = <&l3c1>;
3445 l2c1_1: l2-cache11 {
3447 cache-size = <262144>;
3448 cache-line-size = <64>;
3449 cache-sets = <512>;
3450 cache-unified;
3451 cache-level = <2>;
3452 next-level-cache = <&l3c1>;
3455 l2c1_2: l2-cache12 {
3457 cache-size = <262144>;
3458 cache-line-size = <64>;
3459 cache-sets = <512>;
3460 cache-unified;
3461 cache-level = <2>;
3462 next-level-cache = <&l3c1>;
3465 l2c1_3: l2-cache13 {
3467 cache-size = <262144>;
3468 cache-line-size = <64>;
3469 cache-sets = <512>;
3470 cache-unified;
3471 cache-level = <2>;
3472 next-level-cache = <&l3c1>;
3475 l2c2_0: l2-cache20 {
3477 cache-size = <262144>;
3478 cache-line-size = <64>;
3479 cache-sets = <512>;
3480 cache-unified;
3481 cache-level = <2>;
3482 next-level-cache = <&l3c2>;
3485 l2c2_1: l2-cache21 {
3487 cache-size = <262144>;
3488 cache-line-size = <64>;
3489 cache-sets = <512>;
3490 cache-unified;
3491 cache-level = <2>;
3492 next-level-cache = <&l3c2>;
3495 l2c2_2: l2-cache22 {
3497 cache-size = <262144>;
3498 cache-line-size = <64>;
3499 cache-sets = <512>;
3500 cache-unified;
3501 cache-level = <2>;
3502 next-level-cache = <&l3c2>;
3505 l2c2_3: l2-cache23 {
3507 cache-size = <262144>;
3508 cache-line-size = <64>;
3509 cache-sets = <512>;
3510 cache-unified;
3511 cache-level = <2>;
3512 next-level-cache = <&l3c2>;
3515 l3c0: l3-cache0 {
3517 cache-unified;
3518 cache-size = <2097152>;
3519 cache-line-size = <64>;
3520 cache-sets = <2048>;
3521 cache-level = <3>;
3524 l3c1: l3-cache1 {
3526 cache-unified;
3527 cache-size = <2097152>;
3528 cache-line-size = <64>;
3529 cache-sets = <2048>;
3530 cache-level = <3>;
3533 l3c2: l3-cache2 {
3535 cache-unified;
3536 cache-size = <2097152>;
3537 cache-line-size = <64>;
3538 cache-sets = <2048>;
3539 cache-level = <3>;
3543 dsu-pmu0 {
3544 compatible = "arm,dsu-pmu";
3549 dsu-pmu1 {
3550 compatible = "arm,dsu-pmu";
3555 dsu-pmu2 {
3556 compatible = "arm,dsu-pmu";
3562 compatible = "arm,cortex-a78-pmu";
3568 compatible = "arm,psci-1.0";
3574 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
3577 mbox-names = "rx", "tx";
3584 clocks = <&bpmp TEGRA234_CLK_PLLA>,
3585 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3586 clock-names = "pll_a", "plla_out0";
3587 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
3588 <&bpmp TEGRA234_CLK_PLLA_OUT0>,
3589 <&bpmp TEGRA234_CLK_AUD_MCLK>;
3590 assigned-clock-parents = <0>,
3591 <&bpmp TEGRA234_CLK_PLLA>,
3592 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3595 thermal-zones {
3596 cpu-thermal {
3597 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>;
3601 gpu-thermal {
3602 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>;
3606 cv0-thermal {
3607 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>;
3611 cv1-thermal {
3612 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>;
3616 cv2-thermal {
3617 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>;
3621 soc0-thermal {
3622 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>;
3626 soc1-thermal {
3627 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>;
3631 soc2-thermal {
3632 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>;
3636 tj-thermal {
3637 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>;
3643 compatible = "arm,armv8-timer";
3648 interrupt-parent = <&gic>;
3649 always-on;
3652 cl0_opp_tbl: opp-table-cluster0 {
3653 compatible = "operating-points-v2";
3654 opp-shared;
3656 cl0_ch1_opp1: opp-115200000 {
3657 opp-hz = /bits/ 64 <115200000>;
3658 opp-peak-kBps = <816000>;
3661 cl0_ch1_opp2: opp-192000000 {
3662 opp-hz = /bits/ 64 <192000000>;
3663 opp-peak-kBps = <816000>;
3666 cl0_ch1_opp3: opp-268800000 {
3667 opp-hz = /bits/ 64 <268800000>;
3668 opp-peak-kBps = <816000>;
3671 cl0_ch1_opp4: opp-345600000 {
3672 opp-hz = /bits/ 64 <345600000>;
3673 opp-peak-kBps = <816000>;
3676 cl0_ch1_opp5: opp-422400000 {
3677 opp-hz = /bits/ 64 <422400000>;
3678 opp-peak-kBps = <816000>;
3681 cl0_ch1_opp6: opp-499200000 {
3682 opp-hz = /bits/ 64 <499200000>;
3683 opp-peak-kBps = <816000>;
3686 cl0_ch1_opp7: opp-576000000 {
3687 opp-hz = /bits/ 64 <576000000>;
3688 opp-peak-kBps = <816000>;
3691 cl0_ch1_opp8: opp-652800000 {
3692 opp-hz = /bits/ 64 <652800000>;
3693 opp-peak-kBps = <816000>;
3696 cl0_ch1_opp9: opp-729600000 {
3697 opp-hz = /bits/ 64 <729600000>;
3698 opp-peak-kBps = <816000>;
3701 cl0_ch1_opp10: opp-806400000 {
3702 opp-hz = /bits/ 64 <806400000>;
3703 opp-peak-kBps = <816000>;
3706 cl0_ch1_opp11: opp-883200000 {
3707 opp-hz = /bits/ 64 <883200000>;
3708 opp-peak-kBps = <816000>;
3711 cl0_ch1_opp12: opp-960000000 {
3712 opp-hz = /bits/ 64 <960000000>;
3713 opp-peak-kBps = <816000>;
3716 cl0_ch1_opp13: opp-1036800000 {
3717 opp-hz = /bits/ 64 <1036800000>;
3718 opp-peak-kBps = <816000>;
3721 cl0_ch1_opp14: opp-1113600000 {
3722 opp-hz = /bits/ 64 <1113600000>;
3723 opp-peak-kBps = <1632000>;
3726 cl0_ch1_opp15: opp-1190400000 {
3727 opp-hz = /bits/ 64 <1190400000>;
3728 opp-peak-kBps = <1632000>;
3731 cl0_ch1_opp16: opp-1267200000 {
3732 opp-hz = /bits/ 64 <1267200000>;
3733 opp-peak-kBps = <1632000>;
3736 cl0_ch1_opp17: opp-1344000000 {
3737 opp-hz = /bits/ 64 <1344000000>;
3738 opp-peak-kBps = <1632000>;
3741 cl0_ch1_opp18: opp-1420800000 {
3742 opp-hz = /bits/ 64 <1420800000>;
3743 opp-peak-kBps = <1632000>;
3746 cl0_ch1_opp19: opp-1497600000 {
3747 opp-hz = /bits/ 64 <1497600000>;
3748 opp-peak-kBps = <3200000>;
3751 cl0_ch1_opp20: opp-1574400000 {
3752 opp-hz = /bits/ 64 <1574400000>;
3753 opp-peak-kBps = <3200000>;
3756 cl0_ch1_opp21: opp-1651200000 {
3757 opp-hz = /bits/ 64 <1651200000>;
3758 opp-peak-kBps = <3200000>;
3761 cl0_ch1_opp22: opp-1728000000 {
3762 opp-hz = /bits/ 64 <1728000000>;
3763 opp-peak-kBps = <3200000>;
3766 cl0_ch1_opp23: opp-1804800000 {
3767 opp-hz = /bits/ 64 <1804800000>;
3768 opp-peak-kBps = <3200000>;
3771 cl0_ch1_opp24: opp-1881600000 {
3772 opp-hz = /bits/ 64 <1881600000>;
3773 opp-peak-kBps = <3200000>;
3776 cl0_ch1_opp25: opp-1958400000 {
3777 opp-hz = /bits/ 64 <1958400000>;
3778 opp-peak-kBps = <3200000>;
3781 cl0_ch1_opp26: opp-2035200000 {
3782 opp-hz = /bits/ 64 <2035200000>;
3783 opp-peak-kBps = <3200000>;
3786 cl0_ch1_opp27: opp-2112000000 {
3787 opp-hz = /bits/ 64 <2112000000>;
3788 opp-peak-kBps = <6400000>;
3791 cl0_ch1_opp28: opp-2188800000 {
3792 opp-hz = /bits/ 64 <2188800000>;
3793 opp-peak-kBps = <6400000>;
3796 cl0_ch1_opp29: opp-2201600000 {
3797 opp-hz = /bits/ 64 <2201600000>;
3798 opp-peak-kBps = <6400000>;
3802 cl1_opp_tbl: opp-table-cluster1 {
3803 compatible = "operating-points-v2";
3804 opp-shared;
3806 cl1_ch1_opp1: opp-115200000 {
3807 opp-hz = /bits/ 64 <115200000>;
3808 opp-peak-kBps = <816000>;
3811 cl1_ch1_opp2: opp-192000000 {
3812 opp-hz = /bits/ 64 <192000000>;
3813 opp-peak-kBps = <816000>;
3816 cl1_ch1_opp3: opp-268800000 {
3817 opp-hz = /bits/ 64 <268800000>;
3818 opp-peak-kBps = <816000>;
3821 cl1_ch1_opp4: opp-345600000 {
3822 opp-hz = /bits/ 64 <345600000>;
3823 opp-peak-kBps = <816000>;
3826 cl1_ch1_opp5: opp-422400000 {
3827 opp-hz = /bits/ 64 <422400000>;
3828 opp-peak-kBps = <816000>;
3831 cl1_ch1_opp6: opp-499200000 {
3832 opp-hz = /bits/ 64 <499200000>;
3833 opp-peak-kBps = <816000>;
3836 cl1_ch1_opp7: opp-576000000 {
3837 opp-hz = /bits/ 64 <576000000>;
3838 opp-peak-kBps = <816000>;
3841 cl1_ch1_opp8: opp-652800000 {
3842 opp-hz = /bits/ 64 <652800000>;
3843 opp-peak-kBps = <816000>;
3846 cl1_ch1_opp9: opp-729600000 {
3847 opp-hz = /bits/ 64 <729600000>;
3848 opp-peak-kBps = <816000>;
3851 cl1_ch1_opp10: opp-806400000 {
3852 opp-hz = /bits/ 64 <806400000>;
3853 opp-peak-kBps = <816000>;
3856 cl1_ch1_opp11: opp-883200000 {
3857 opp-hz = /bits/ 64 <883200000>;
3858 opp-peak-kBps = <816000>;
3861 cl1_ch1_opp12: opp-960000000 {
3862 opp-hz = /bits/ 64 <960000000>;
3863 opp-peak-kBps = <816000>;
3866 cl1_ch1_opp13: opp-1036800000 {
3867 opp-hz = /bits/ 64 <1036800000>;
3868 opp-peak-kBps = <816000>;
3871 cl1_ch1_opp14: opp-1113600000 {
3872 opp-hz = /bits/ 64 <1113600000>;
3873 opp-peak-kBps = <1632000>;
3876 cl1_ch1_opp15: opp-1190400000 {
3877 opp-hz = /bits/ 64 <1190400000>;
3878 opp-peak-kBps = <1632000>;
3881 cl1_ch1_opp16: opp-1267200000 {
3882 opp-hz = /bits/ 64 <1267200000>;
3883 opp-peak-kBps = <1632000>;
3886 cl1_ch1_opp17: opp-1344000000 {
3887 opp-hz = /bits/ 64 <1344000000>;
3888 opp-peak-kBps = <1632000>;
3891 cl1_ch1_opp18: opp-1420800000 {
3892 opp-hz = /bits/ 64 <1420800000>;
3893 opp-peak-kBps = <1632000>;
3896 cl1_ch1_opp19: opp-1497600000 {
3897 opp-hz = /bits/ 64 <1497600000>;
3898 opp-peak-kBps = <3200000>;
3901 cl1_ch1_opp20: opp-1574400000 {
3902 opp-hz = /bits/ 64 <1574400000>;
3903 opp-peak-kBps = <3200000>;
3906 cl1_ch1_opp21: opp-1651200000 {
3907 opp-hz = /bits/ 64 <1651200000>;
3908 opp-peak-kBps = <3200000>;
3911 cl1_ch1_opp22: opp-1728000000 {
3912 opp-hz = /bits/ 64 <1728000000>;
3913 opp-peak-kBps = <3200000>;
3916 cl1_ch1_opp23: opp-1804800000 {
3917 opp-hz = /bits/ 64 <1804800000>;
3918 opp-peak-kBps = <3200000>;
3921 cl1_ch1_opp24: opp-1881600000 {
3922 opp-hz = /bits/ 64 <1881600000>;
3923 opp-peak-kBps = <3200000>;
3926 cl1_ch1_opp25: opp-1958400000 {
3927 opp-hz = /bits/ 64 <1958400000>;
3928 opp-peak-kBps = <3200000>;
3931 cl1_ch1_opp26: opp-2035200000 {
3932 opp-hz = /bits/ 64 <2035200000>;
3933 opp-peak-kBps = <3200000>;
3936 cl1_ch1_opp27: opp-2112000000 {
3937 opp-hz = /bits/ 64 <2112000000>;
3938 opp-peak-kBps = <6400000>;
3941 cl1_ch1_opp28: opp-2188800000 {
3942 opp-hz = /bits/ 64 <2188800000>;
3943 opp-peak-kBps = <6400000>;
3946 cl1_ch1_opp29: opp-2201600000 {
3947 opp-hz = /bits/ 64 <2201600000>;
3948 opp-peak-kBps = <6400000>;
3952 cl2_opp_tbl: opp-table-cluster2 {
3953 compatible = "operating-points-v2";
3954 opp-shared;
3956 cl2_ch1_opp1: opp-115200000 {
3957 opp-hz = /bits/ 64 <115200000>;
3958 opp-peak-kBps = <816000>;
3961 cl2_ch1_opp2: opp-192000000 {
3962 opp-hz = /bits/ 64 <192000000>;
3963 opp-peak-kBps = <816000>;
3966 cl2_ch1_opp3: opp-268800000 {
3967 opp-hz = /bits/ 64 <268800000>;
3968 opp-peak-kBps = <816000>;
3971 cl2_ch1_opp4: opp-345600000 {
3972 opp-hz = /bits/ 64 <345600000>;
3973 opp-peak-kBps = <816000>;
3976 cl2_ch1_opp5: opp-422400000 {
3977 opp-hz = /bits/ 64 <422400000>;
3978 opp-peak-kBps = <816000>;
3981 cl2_ch1_opp6: opp-499200000 {
3982 opp-hz = /bits/ 64 <499200000>;
3983 opp-peak-kBps = <816000>;
3986 cl2_ch1_opp7: opp-576000000 {
3987 opp-hz = /bits/ 64 <576000000>;
3988 opp-peak-kBps = <816000>;
3991 cl2_ch1_opp8: opp-652800000 {
3992 opp-hz = /bits/ 64 <652800000>;
3993 opp-peak-kBps = <816000>;
3996 cl2_ch1_opp9: opp-729600000 {
3997 opp-hz = /bits/ 64 <729600000>;
3998 opp-peak-kBps = <816000>;
4001 cl2_ch1_opp10: opp-806400000 {
4002 opp-hz = /bits/ 64 <806400000>;
4003 opp-peak-kBps = <816000>;
4006 cl2_ch1_opp11: opp-883200000 {
4007 opp-hz = /bits/ 64 <883200000>;
4008 opp-peak-kBps = <816000>;
4011 cl2_ch1_opp12: opp-960000000 {
4012 opp-hz = /bits/ 64 <960000000>;
4013 opp-peak-kBps = <816000>;
4016 cl2_ch1_opp13: opp-1036800000 {
4017 opp-hz = /bits/ 64 <1036800000>;
4018 opp-peak-kBps = <816000>;
4021 cl2_ch1_opp14: opp-1113600000 {
4022 opp-hz = /bits/ 64 <1113600000>;
4023 opp-peak-kBps = <1632000>;
4026 cl2_ch1_opp15: opp-1190400000 {
4027 opp-hz = /bits/ 64 <1190400000>;
4028 opp-peak-kBps = <1632000>;
4031 cl2_ch1_opp16: opp-1267200000 {
4032 opp-hz = /bits/ 64 <1267200000>;
4033 opp-peak-kBps = <1632000>;
4036 cl2_ch1_opp17: opp-1344000000 {
4037 opp-hz = /bits/ 64 <1344000000>;
4038 opp-peak-kBps = <1632000>;
4041 cl2_ch1_opp18: opp-1420800000 {
4042 opp-hz = /bits/ 64 <1420800000>;
4043 opp-peak-kBps = <1632000>;
4046 cl2_ch1_opp19: opp-1497600000 {
4047 opp-hz = /bits/ 64 <1497600000>;
4048 opp-peak-kBps = <3200000>;
4051 cl2_ch1_opp20: opp-1574400000 {
4052 opp-hz = /bits/ 64 <1574400000>;
4053 opp-peak-kBps = <3200000>;
4056 cl2_ch1_opp21: opp-1651200000 {
4057 opp-hz = /bits/ 64 <1651200000>;
4058 opp-peak-kBps = <3200000>;
4061 cl2_ch1_opp22: opp-1728000000 {
4062 opp-hz = /bits/ 64 <1728000000>;
4063 opp-peak-kBps = <3200000>;
4066 cl2_ch1_opp23: opp-1804800000 {
4067 opp-hz = /bits/ 64 <1804800000>;
4068 opp-peak-kBps = <3200000>;
4071 cl2_ch1_opp24: opp-1881600000 {
4072 opp-hz = /bits/ 64 <1881600000>;
4073 opp-peak-kBps = <3200000>;
4076 cl2_ch1_opp25: opp-1958400000 {
4077 opp-hz = /bits/ 64 <1958400000>;
4078 opp-peak-kBps = <3200000>;
4081 cl2_ch1_opp26: opp-2035200000 {
4082 opp-hz = /bits/ 64 <2035200000>;
4083 opp-peak-kBps = <3200000>;
4086 cl2_ch1_opp27: opp-2112000000 {
4087 opp-hz = /bits/ 64 <2112000000>;
4088 opp-peak-kBps = <6400000>;
4091 cl2_ch1_opp28: opp-2188800000 {
4092 opp-hz = /bits/ 64 <2188800000>;
4093 opp-peak-kBps = <6400000>;
4096 cl2_ch1_opp29: opp-2201600000 {
4097 opp-hz = /bits/ 64 <2201600000>;
4098 opp-peak-kBps = <6400000>;