Lines Matching full:bpmp

11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
124 			resets = <&bpmp TEGRA234_RESET_GPCDMA>;
167 			clocks = <&bpmp TEGRA234_CLK_APE>,
168 				 <&bpmp TEGRA234_CLK_APB2APE>;
170 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
180 				clocks = <&bpmp TEGRA234_CLK_AHUB>;
182 				assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
183 				assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
195 					clocks = <&bpmp TEGRA234_CLK_I2S1>,
196 						 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
198 					assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
199 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
209 					clocks = <&bpmp TEGRA234_CLK_I2S2>,
210 						 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
212 					assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
213 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
223 					clocks = <&bpmp TEGRA234_CLK_I2S3>,
224 						 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
226 					assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
227 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
237 					clocks = <&bpmp TEGRA234_CLK_I2S4>,
238 						 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
240 					assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
241 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
251 					clocks = <&bpmp TEGRA234_CLK_I2S5>,
252 						 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
254 					assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
255 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
265 					clocks = <&bpmp TEGRA234_CLK_I2S6>,
266 						 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
268 					assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
269 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
376 					clocks = <&bpmp TEGRA234_CLK_DMIC1>;
378 					assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
379 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
389 					clocks = <&bpmp TEGRA234_CLK_DMIC2>;
391 					assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
392 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
402 					clocks = <&bpmp TEGRA234_CLK_DMIC3>;
404 					assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
405 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
415 					clocks = <&bpmp TEGRA234_CLK_DMIC4>;
417 					assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
418 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
428 					clocks = <&bpmp TEGRA234_CLK_DSPK1>;
430 					assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
431 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
441 					clocks = <&bpmp TEGRA234_CLK_DSPK2>;
443 					assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
444 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
596 				clocks = <&bpmp TEGRA234_CLK_AHUB>;
611 				clocks = <&bpmp TEGRA234_CLK_APE>;
672 				clocks = <&bpmp TEGRA234_CLK_EMC>;
678 				nvidia,bpmp = <&bpmp>;
686 			clocks = <&bpmp TEGRA234_CLK_UARTA>;
687 			resets = <&bpmp TEGRA234_RESET_UARTA>;
695 			clocks = <&bpmp TEGRA234_CLK_UARTE>;
696 			resets = <&bpmp TEGRA234_RESET_UARTE>;
708 			clocks = <&bpmp TEGRA234_CLK_I2C1
709 				  &bpmp TEGRA234_CLK_PLLP_OUT0>;
710 			assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
711 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
713 			resets = <&bpmp TEGRA234_RESET_I2C1>;
727 			clocks = <&bpmp TEGRA234_CLK_I2C3
728 				&bpmp TEGRA234_CLK_PLLP_OUT0>;
729 			assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
730 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
732 			resets = <&bpmp TEGRA234_RESET_I2C3>;
746 			clocks = <&bpmp TEGRA234_CLK_I2C4
747 				&bpmp TEGRA234_CLK_PLLP_OUT0>;
748 			assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
749 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
751 			resets = <&bpmp TEGRA234_RESET_I2C4>;
765 			clocks = <&bpmp TEGRA234_CLK_I2C6
766 				&bpmp TEGRA234_CLK_PLLP_OUT0>;
767 			assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
768 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
770 			resets = <&bpmp TEGRA234_RESET_I2C6>;
784 			clocks = <&bpmp TEGRA234_CLK_I2C7
785 				&bpmp TEGRA234_CLK_PLLP_OUT0>;
786 			assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
787 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
789 			resets = <&bpmp TEGRA234_RESET_I2C7>;
810 			clocks = <&bpmp TEGRA234_CLK_I2C9
811 				&bpmp TEGRA234_CLK_PLLP_OUT0>;
812 			assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
813 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
815 			resets = <&bpmp TEGRA234_RESET_I2C9>;
827 			clocks = <&bpmp TEGRA234_CLK_SPI1>;
828 			assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>;
829 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
832 			resets = <&bpmp TEGRA234_RESET_SPI1>;
846 			clocks = <&bpmp TEGRA234_CLK_SPI3>;
849 			assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>;
850 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
851 			resets = <&bpmp TEGRA234_RESET_SPI3>;
865 			clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
866 				 <&bpmp TEGRA234_CLK_QSPI0_PM>;
868 			resets = <&bpmp TEGRA234_RESET_QSPI0>;
875 			clocks = <&bpmp TEGRA234_CLK_PWM1>;
876 			resets = <&bpmp TEGRA234_RESET_PWM1>;
885 			clocks = <&bpmp TEGRA234_CLK_PWM2>;
886 			resets = <&bpmp TEGRA234_RESET_PWM2>;
895 			clocks = <&bpmp TEGRA234_CLK_PWM3>;
896 			resets = <&bpmp TEGRA234_RESET_PWM3>;
905 			clocks = <&bpmp TEGRA234_CLK_PWM5>;
906 			resets = <&bpmp TEGRA234_RESET_PWM5>;
915 			clocks = <&bpmp TEGRA234_CLK_PWM6>;
916 			resets = <&bpmp TEGRA234_RESET_PWM6>;
925 			clocks = <&bpmp TEGRA234_CLK_PWM7>;
926 			resets = <&bpmp TEGRA234_RESET_PWM7>;
935 			clocks = <&bpmp TEGRA234_CLK_PWM8>;
936 			resets = <&bpmp TEGRA234_RESET_PWM8>;
948 			clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
949 				 <&bpmp TEGRA234_CLK_QSPI1_PM>;
951 			resets = <&bpmp TEGRA234_RESET_QSPI1>;
959 			clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
960 				 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
962 			assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
963 					  <&bpmp TEGRA234_CLK_PLLC4_MUXED>;
964 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
965 						 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
966 			resets = <&bpmp TEGRA234_RESET_SDMMC1>;
994 			clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
995 				 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
997 			assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
998 					  <&bpmp TEGRA234_CLK_PLLC4>;
999 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
1000 			resets = <&bpmp TEGRA234_RESET_SDMMC4>;
1023 			clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
1024 				 <&bpmp TEGRA234_CLK_AZA_2XBIT>;
1026 			resets = <&bpmp TEGRA234_RESET_HDA>,
1027 				 <&bpmp TEGRA234_RESET_HDACODEC>;
1029 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
1044 			resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>;
1051 					clocks = <&bpmp TEGRA234_CLK_USB2_TRK>;
1151 			clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>,
1152 				 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
1153 				 <&bpmp TEGRA234_CLK_XUSB_SS>,
1154 				 <&bpmp TEGRA234_CLK_XUSB_FS>;
1160 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>,
1161 					<&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
1178 			clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
1179 				 <&bpmp TEGRA234_CLK_XUSB_FALCON>,
1180 				 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
1181 				 <&bpmp TEGRA234_CLK_XUSB_SS>,
1182 				 <&bpmp TEGRA234_CLK_CLK_M>,
1183 				 <&bpmp TEGRA234_CLK_XUSB_FS>,
1184 				 <&bpmp TEGRA234_CLK_UTMIP_PLL>,
1185 				 <&bpmp TEGRA234_CLK_CLK_M>,
1186 				 <&bpmp TEGRA234_CLK_PLLE>;
1196 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
1197 					<&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
1208 			clocks = <&bpmp TEGRA234_CLK_FUSE>;
1438 			clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
1439 				 <&bpmp TEGRA234_CLK_MGBE0_MAC>,
1440 				 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
1441 				 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
1442 				 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
1443 				 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
1444 				 <&bpmp TEGRA234_CLK_MGBE0_TX>,
1445 				 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
1446 				 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
1447 				 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
1448 				 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
1449 				 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
1453 			resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
1454 				 <&bpmp TEGRA234_RESET_MGBE0_PCS>;
1460 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
1472 			clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
1473 				 <&bpmp TEGRA234_CLK_MGBE1_MAC>,
1474 				 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
1475 				 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
1476 				 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
1477 				 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
1478 				 <&bpmp TEGRA234_CLK_MGBE1_TX>,
1479 				 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
1480 				 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
1481 				 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
1482 				 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
1483 				 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
1487 			resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
1488 				 <&bpmp TEGRA234_RESET_MGBE1_PCS>;
1494 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
1506 			clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
1507 				 <&bpmp TEGRA234_CLK_MGBE2_MAC>,
1508 				 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
1509 				 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
1510 				 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
1511 				 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
1512 				 <&bpmp TEGRA234_CLK_MGBE2_TX>,
1513 				 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
1514 				 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
1515 				 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
1516 				 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
1517 				 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
1521 			resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
1522 				 <&bpmp TEGRA234_RESET_MGBE2_PCS>;
1528 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
1540 			clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
1541 				 <&bpmp TEGRA234_CLK_MGBE3_MAC>,
1542 				 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
1543 				 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
1544 				 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
1545 				 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
1546 				 <&bpmp TEGRA234_CLK_MGBE3_TX>,
1547 				 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
1548 				 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
1549 				 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
1550 				 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
1551 				 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
1555 			resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
1556 				 <&bpmp TEGRA234_RESET_MGBE3_PCS>;
1562 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
1754 			clocks = <&bpmp TEGRA234_CLK_I2C2
1755 				&bpmp TEGRA234_CLK_PLLP_OUT0>;
1757 			assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
1758 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1759 			resets = <&bpmp TEGRA234_RESET_I2C2>;
1773 			clocks = <&bpmp TEGRA234_CLK_I2C8
1774 				&bpmp TEGRA234_CLK_PLLP_OUT0>;
1776 			assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
1777 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1778 			resets = <&bpmp TEGRA234_RESET_I2C8>;
1790 			clocks = <&bpmp TEGRA234_CLK_SPI2>;
1793 			assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>;
1794 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1795 			resets = <&bpmp TEGRA234_RESET_SPI2>;
1808 			clocks = <&bpmp TEGRA234_CLK_CLK_32K>;
1837 			clocks = <&bpmp TEGRA234_CLK_PWM4>;
1838 			resets = <&bpmp TEGRA234_RESET_PWM4>;
1884 		bpmp-fabric@d600000 {
1885 			compatible = "nvidia,tegra234-bpmp-fabric";
1901 			nvidia,bpmp = <&bpmp>;
2225 			clocks = <&bpmp TEGRA234_CLK_HOST1X>;
2259 				clocks = <&bpmp TEGRA234_CLK_VIC>;
2261 				resets = <&bpmp TEGRA234_RESET_VIC>;
2264 				power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
2275 				clocks = <&bpmp TEGRA234_CLK_NVDEC>,
2276 					 <&bpmp TEGRA234_CLK_FUSE>,
2277 					 <&bpmp TEGRA234_CLK_TSEC_PKA>;
2279 				resets = <&bpmp TEGRA234_RESET_NVDEC>;
2281 				power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
2311 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
2326 			clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>;
2329 			resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>,
2330 				 <&bpmp TEGRA234_RESET_PEX2_CORE_8>;
2341 			nvidia,bpmp = <&bpmp 8>;
2365 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
2380 			clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>;
2383 			resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>,
2384 				 <&bpmp TEGRA234_RESET_PEX2_CORE_9>;
2395 			nvidia,bpmp = <&bpmp 9>;
2419 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2434 			clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2437 			resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2438 				 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2449 			nvidia,bpmp = <&bpmp 10>;
2473 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2482 			clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2485 			resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2486 				 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2492 			nvidia,bpmp = <&bpmp 10>;
2511 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2526 			clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>;
2529 			resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>,
2530 				 <&bpmp TEGRA234_RESET_PEX0_CORE_1>;
2541 			nvidia,bpmp = <&bpmp 1>;
2565 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2580 			clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>;
2583 			resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>,
2584 				 <&bpmp TEGRA234_RESET_PEX0_CORE_2>;
2595 			nvidia,bpmp = <&bpmp 2>;
2619 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2634 			clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>;
2637 			resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>,
2638 				 <&bpmp TEGRA234_RESET_PEX0_CORE_3>;
2649 			nvidia,bpmp = <&bpmp 3>;
2673 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
2688 			clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
2691 			resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
2692 				 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
2703 			nvidia,bpmp = <&bpmp 4>;
2727 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
2742 			clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>;
2745 			resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>,
2746 				 <&bpmp TEGRA234_RESET_PEX0_CORE_0>;
2757 			nvidia,bpmp = <&bpmp 0>;
2781 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2796 			clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2799 			resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2800 				 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2811 			nvidia,bpmp = <&bpmp 5>;
2835 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2844 			clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2847 			resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2848 				 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2854 			nvidia,bpmp = <&bpmp 5>;
2873 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2888 			clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2891 			resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2892 				 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2903 			nvidia,bpmp = <&bpmp 6>;
2927 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2936 			clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2939 			resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2940 				 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2946 			nvidia,bpmp = <&bpmp 6>;
2965 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2980 			clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2983 			resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2984 				 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2995 			nvidia,bpmp = <&bpmp 7>;
3019 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
3028 			clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
3031 			resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
3032 				 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
3038 			nvidia,bpmp = <&bpmp 7>;
3068 			label = "cpu-bpmp-tx";
3074 			label = "cpu-bpmp-rx";
3079 	bpmp: bpmp {  label
3080 		compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
3095 			compatible = "nvidia,tegra186-bpmp-i2c";
3096 			nvidia,bpmp-bus-id = <5>;
3102 			compatible = "nvidia,tegra186-bpmp-thermal";
3584 		clocks = <&bpmp TEGRA234_CLK_PLLA>,
3585 			 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3587 		assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
3588 				  <&bpmp TEGRA234_CLK_PLLA_OUT0>,
3589 				  <&bpmp TEGRA234_CLK_AUD_MCLK>;
3591 					 <&bpmp TEGRA234_CLK_PLLA>,
3592 					 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3597 			thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>;
3602 			thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>;
3607 			thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>;
3612 			thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>;
3617 			thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>;
3622 			thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>;
3627 			thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>;
3632 			thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>;
3637 			thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>;