Lines Matching +full:1 +full:ee0000
37 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
158 #dma-cells = <1>;
502 dmas = <&adma 1>, <&adma 1>,
564 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
595 #dma-cells = <1>;
641 #interconnect-cells = <1>;
705 #address-cells = <1>;
723 #address-cells = <1>;
742 #address-cells = <1>;
761 #address-cells = <1>;
780 #address-cells = <1>;
806 #address-cells = <1>;
825 #address-cells = <1>;
844 #address-cells = <1>;
863 #address-cells = <1>;
946 #address-cells = <1>;
972 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
974 pinctrl-1 = <&sdmmc1_1v8>;
977 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
978 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
1008 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1009 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
1061 usb2-1 {
1089 usb3-1 {
1115 usb2-1 {
1131 usb3-1 {
1216 nvidia,int-threshold = <1>;
1217 #timestamp-cells = <1>;
1342 p2u_nvhs_5: phy@3ee0000 {
1702 #iommu-cells = <1>;
1741 nvidia,int-threshold = <1>;
1743 #timestamp-cells = <1>;
1750 #address-cells = <1>;
1769 #address-cells = <1>;
1788 #address-cells = <1>;
1856 sdmmc1_1v8: sdmmc1-1v8 {
1866 sdmmc3_1v8: sdmmc3-1v8 {
1912 #redistributor-regions = <1>;
2052 #global-interrupts = <1>;
2053 #iommu-cells = <1>;
2195 #iommu-cells = <1>;
2238 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
2239 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>,
2240 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>,
2241 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>,
2242 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>,
2243 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>,
2244 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>,
2245 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>,
2246 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>,
2247 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>,
2248 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>,
2249 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>,
2250 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>,
2251 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>,
2252 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>,
2253 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>;
2337 #interrupt-cells = <1>;
2351 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2391 #interrupt-cells = <1>;
2405 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2445 #interrupt-cells = <1>;
2459 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2522 num-lanes = <1>;
2524 linux,pci-domain = <1>;
2537 #interrupt-cells = <1>;
2541 nvidia,bpmp = <&bpmp 1>;
2551 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2576 num-lanes = <1>;
2591 #interrupt-cells = <1>;
2605 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2630 num-lanes = <1>;
2645 #interrupt-cells = <1>;
2659 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2699 #interrupt-cells = <1>;
2713 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2753 #interrupt-cells = <1>;
2767 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2807 #interrupt-cells = <1>;
2821 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2899 #interrupt-cells = <1>;
2913 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2991 #interrupt-cells = <1>;
3005 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
3060 #address-cells = <1>;
3061 #size-cells = <1>;
3084 #clock-cells = <1>;
3085 #reset-cells = <1>;
3086 #power-domain-cells = <1>;
3097 #address-cells = <1>;
3103 #thermal-sensor-cells = <1>;
3108 #address-cells = <1>;
3576 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;