dts/mediatek/mt8365.dtsi

1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/phy/phy.h>
15 	interrupt-parent = <&sysirq>;
16 	#address-cells = <2>;
17 	#size-cells = <2>;
20 		#address-cells = <1>;
21 		#size-cells = <0>;
23 	cluster0_opp: opp-table-0 {
24 		compatible = "operating-points-v2";
25 		opp-shared;
27 		opp-850000000 {
28 			opp-hz = /bits/ 64 <850000000>;
29 			opp-microvolt = <650000>;
32 		opp-918000000 {
33 			opp-hz = /bits/ 64 <918000000>;
34 			opp-microvolt = <668750>;
37 		opp-987000000 {
38 			opp-hz = /bits/ 64 <987000000>;
39 			opp-microvolt = <687500>;
42 		opp-1056000000 {
43 			opp-hz = /bits/ 64 <1056000000>;
44 			opp-microvolt = <706250>;
47 		opp-1125000000 {
48 			opp-hz = /bits/ 64 <1125000000>;
49 			opp-microvolt = <725000>;
52 		opp-1216000000 {
53 			opp-hz = /bits/ 64 <1216000000>;
54 			opp-microvolt = <750000>;
57 		opp-1308000000 {
58 			opp-hz = /bits/ 64 <1308000000>;
59 			opp-microvolt = <775000>;
62 		opp-1400000000 {
63 			opp-hz = /bits/ 64 <1400000000>;
64 			opp-microvolt = <800000>;
67 		opp-1466000000 {
68 			opp-hz = /bits/ 64 <1466000000>;
69 			opp-microvolt = <825000>;
72 		opp-1533000000 {
73 			opp-hz = /bits/ 64 <1533000000>;
74 			opp-microvolt = <850000>;
77 		opp-1633000000 {
78 			opp-hz = /bits/ 64 <1633000000>;
79 			opp-microvolt = <887500>;
82 		opp-1700000000 {
83 			opp-hz = /bits/ 64 <1700000000>;
84 			opp-microvolt = <912500>;
87 		opp-1767000000 {
88 			opp-hz = /bits/ 64 <1767000000>;
89 			opp-microvolt = <937500>;
92 		opp-1834000000 {
93 			opp-hz = /bits/ 64 <1834000000>;
94 			opp-microvolt = <962500>;
97 		opp-1917000000 {
98 			opp-hz = /bits/ 64 <1917000000>;
99 			opp-microvolt = <993750>;
102 		opp-2001000000 {
103 			opp-hz = /bits/ 64 <2001000000>;
104 			opp-microvolt = <1025000>;
108 		cpu-map {
127 			compatible = "arm,cortex-a53";
129 			#cooling-cells = <2>;
130 			enable-method = "psci";
131 			cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
132 			i-cache-size = <0x8000>;
133 			i-cache-line-size = <64>;
134 			i-cache-sets = <256>;
135 			d-cache-size = <0x8000>;
136 			d-cache-line-size = <64>;
137 			d-cache-sets = <256>;
138 			next-level-cache = <&l2>;
141 			clock-names = "cpu", "intermediate";
142 			operating-points-v2 = <&cluster0_opp>;
147 			compatible = "arm,cortex-a53";
149 			#cooling-cells = <2>;
150 			enable-method = "psci";
151 			cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
152 			i-cache-size = <0x8000>;
153 			i-cache-line-size = <64>;
154 			i-cache-sets = <256>;
155 			d-cache-size = <0x8000>;
156 			d-cache-line-size = <64>;
157 			d-cache-sets = <256>;
158 			next-level-cache = <&l2>;
161 			clock-names = "cpu", "intermediate", "armpll";
162 			operating-points-v2 = <&cluster0_opp>;
167 			compatible = "arm,cortex-a53";
169 			#cooling-cells = <2>;
170 			enable-method = "psci";
171 			cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
172 			i-cache-size = <0x8000>;
173 			i-cache-line-size = <64>;
174 			i-cache-sets = <256>;
175 			d-cache-size = <0x8000>;
176 			d-cache-line-size = <64>;
177 			d-cache-sets = <256>;
178 			next-level-cache = <&l2>;
181 			clock-names = "cpu", "intermediate", "armpll";
182 			operating-points-v2 = <&cluster0_opp>;
187 			compatible = "arm,cortex-a53";
189 			#cooling-cells = <2>;
190 			enable-method = "psci";
191 			cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
192 			i-cache-size = <0x8000>;
193 			i-cache-line-size = <64>;
194 			i-cache-sets = <256>;
195 			d-cache-size = <0x8000>;
196 			d-cache-line-size = <64>;
197 			d-cache-sets = <256>;
198 			next-level-cache = <&l2>;
201 			clock-names = "cpu", "intermediate", "armpll";
202 			operating-points-v2 = <&cluster0_opp>;
205 		idle-states {
206 			entry-method = "psci";
208 			CPU_MCDI: cpu-mcdi {
209 				compatible = "arm,idle-state";
210 				local-timer-stop;
211 				arm,psci-suspend-param = <0x00010001>;
212 				entry-latency-us = <300>;
213 				exit-latency-us = <200>;
214 				min-residency-us = <1000>;
217 			CLUSTER_MCDI: cluster-mcdi {
218 				compatible = "arm,idle-state";
219 				local-timer-stop;
220 				arm,psci-suspend-param = <0x01010001>;
221 				entry-latency-us = <350>;
222 				exit-latency-us = <250>;
223 				min-residency-us = <1200>;
226 			CLUSTER_DPIDLE: cluster-dpidle {
227 				compatible = "arm,idle-state";
228 				local-timer-stop;
229 				arm,psci-suspend-param = <0x01010004>;
230 				entry-latency-us = <300>;
231 				exit-latency-us = <800>;
232 				min-residency-us = <3300>;
236 		l2: l2-cache {
238 			cache-level = <2>;
239 			cache-size = <0x80000>;
240 			cache-line-size = <64>;
241 			cache-sets = <512>;
242 			cache-unified;
247 		compatible = "fixed-clock";
248 		#clock-cells = <0>;
249 		clock-frequency = <26000000>;
250 		clock-output-names = "clk26m";
254 		compatible = "arm,psci-1.0";
259 		#address-cells = <2>;
260 		#size-cells = <2>;
261 		compatible = "simple-bus";
264 		gic: interrupt-controller@c000000 {
265 			compatible = "arm,gic-v3";
266 			#interrupt-cells = <3>;
267 			interrupt-parent = <&gic>;
268 			interrupt-controller;
279 			compatible = "mediatek,mt8365-topckgen", "syscon";
281 			#clock-cells = <1>;
285 			compatible = "mediatek,mt8365-infracfg", "syscon";
287 			#clock-cells = <1>;
291 			compatible = "mediatek,mt8365-pericfg", "syscon";
293 			#clock-cells = <1>;
296 		syscfg_pctl: syscfg-pctl@10005000 {
297 			compatible = "mediatek,mt8365-syscfg", "syscon";
302 			compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt";
304 			#reset-cells = <1>;
308 			compatible = "mediatek,mt8365-pinctrl";
310 			mediatek,pctl-regmap = <&syscfg_pctl>;
311 			gpio-controller;
312 			#gpio-cells = <2>;
313 			interrupt-controller;
314 			#interrupt-cells = <2>;
319 			compatible = "mediatek,mt8365-apmixedsys", "syscon";
321 			#clock-cells = <1>;
325 			compatible = "mediatek,mt8365-pwrap";
327 			reg-names = "pwrap";
333 			clock-names = "spi", "wrap", "sys", "tmr";
337 			compatible = "mediatek,mt6779-keypad";
339 			wakeup-source;
342 			clock-names = "kpd";
347 			compatible = "mediatek,mt8365-mcucfg", "syscon";
349 			#clock-cells = <1>;
352 		sysirq: interrupt-controller@10200a80 {
353 			compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq";
354 			interrupt-controller;
355 			#interrupt-cells = <3>;
356 			interrupt-parent = <&gic>;
361 			compatible = "mediatek,mt8365-infracfg", "syscon";
363 			#clock-cells = <1>;
367 			compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng";
370 			clock-names = "rng";
373 		apdma: dma-controller@11000280 {
374 			compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma";
387 			dma-requests = <6>;
389 			clock-names = "apdma";
390 			#dma-cells = <1>;
394 			compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
398 			clock-names = "baud", "bus";
400 			dma-names = "tx", "rx";
405 			compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
409 			clock-names = "baud", "bus";
411 			dma-names = "tx", "rx";
416 			compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
420 			clock-names = "baud", "bus";
422 			dma-names = "tx", "rx";
427 			compatible = "mediatek,mt8365-pwm";
429 			#pwm-cells = <2>;
436 			clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
440 			compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
443 			clock-div = <1>;
445 			clock-names = "main", "dma";
446 			#address-cells = <1>;
447 			#size-cells = <0>;
452 			compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
455 			clock-div = <1>;
457 			clock-names = "main", "dma";
458 			#address-cells = <1>;
459 			#size-cells = <0>;
464 			compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
467 			clock-div = <1>;
469 			clock-names = "main", "dma";
470 			#address-cells = <1>;
471 			#size-cells = <0>;
476 			compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";
478 			#address-cells = <1>;
479 			#size-cells = <0>;
484 			clock-names = "parent-clk", "sel-clk", "spi-clk";
489 			compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
492 			clock-div = <1>;
494 			clock-names = "main", "dma";
495 			#address-cells = <1>;
496 			#size-cells = <0>;
501 			compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
503 			reg-names = "mac", "ippc";
511 			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
512 			#address-cells = <2>;
513 			#size-cells = <2>;
518 				compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci";
520 				reg-names = "mac";
527 				clock-names = "sys_ck", "ref_ck", "mcu_ck",
534 			compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
541 			clock-names = "source", "hclk", "source_cg";
546 			compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
553 			clock-names = "source", "hclk", "source_cg";
558 			compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
567 			clock-names = "source", "hclk", "source_cg",
573 			compatible = "mediatek,mt8365-eth";
580 			clock-names = "core", "reg", "trans";
584 		u3phy: t-phy@11cc0000 {
585 			compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
586 			#address-cells = <1>;
587 			#size-cells = <1>;
590 			u2port0: usb-phy@0 {
594 				clock-names = "ref", "da_ref";
595 				#phy-cells = <1>;
598 			u2port1: usb-phy@1000 {
602 				clock-names = "ref", "da_ref";
603 				#phy-cells = <1>;
609 		compatible = "arm,armv8-timer";
610 		interrupt-parent = <&gic>;
618 		compatible = "fixed-clock";
619 		clock-frequency = <13000000>;
620 		#clock-cells = <0>;
624 		compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
628 		clock-names = "clk13m";