Lines Matching full:vppsys0
588 <&vppsys0 CLK_VPP0_SMI_COMMON>,
589 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
590 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
591 <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
592 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
593 <&vppsys0 CLK_VPP0_GALS_INFRA>,
594 <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
595 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
596 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
597 <&vppsys0 CLK_VPP0_SMI_REORDER>,
598 <&vppsys0 CLK_VPP0_SMI_IOMMU>,
599 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
600 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
601 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
602 <&vppsys0 CLK_VPP0_SMI_RSI>,
603 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
604 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
605 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
606 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 "vppsys0-18";
1962 vppsys0: syscon@14000000 { label
1963 compatible = "mediatek,mt8195-vppsys0", "syscon";
1974 clocks = <&vppsys0 CLK_VPP0_MUTEX>;
1981 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1982 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1983 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
1992 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1993 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1994 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
2003 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2004 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2005 <&vppsys0 CLK_VPP0_SMI_RSI>,
2006 <&vppsys0 CLK_VPP0_SMI_RSI>;
2016 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2017 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
2030 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
2072 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2100 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
2112 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
2140 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2259 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2466 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2500 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2677 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
2793 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
2804 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
2805 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
2874 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;