Lines Matching +full:mt8195 +full:- +full:camsys
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
16 #include <dt-bindings/reset/mt8195-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
21 compatible = "mediatek,mt8195";
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
39 vdo1-rdma0 = &vdo1_rdma0;
40 vdo1-rdma1 = &vdo1_rdma1;
41 vdo1-rdma2 = &vdo1_rdma2;
42 vdo1-rdma3 = &vdo1_rdma3;
43 vdo1-rdma4 = &vdo1_rdma4;
44 vdo1-rdma5 = &vdo1_rdma5;
45 vdo1-rdma6 = &vdo1_rdma6;
46 vdo1-rdma7 = &vdo1_rdma7;
50 #address-cells = <1>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a55";
57 enable-method = "psci";
58 performance-domains = <&performance 0>;
59 clock-frequency = <1701000000>;
60 capacity-dmips-mhz = <308>;
61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
62 i-cache-size = <32768>;
63 i-cache-line-size = <64>;
64 i-cache-sets = <128>;
65 d-cache-size = <32768>;
66 d-cache-line-size = <64>;
67 d-cache-sets = <128>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
74 compatible = "arm,cortex-a55";
76 enable-method = "psci";
77 performance-domains = <&performance 0>;
78 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
81 i-cache-size = <32768>;
82 i-cache-line-size = <64>;
83 i-cache-sets = <128>;
84 d-cache-size = <32768>;
85 d-cache-line-size = <64>;
86 d-cache-sets = <128>;
87 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>;
93 compatible = "arm,cortex-a55";
95 enable-method = "psci";
96 performance-domains = <&performance 0>;
97 clock-frequency = <1701000000>;
98 capacity-dmips-mhz = <308>;
99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
100 i-cache-size = <32768>;
101 i-cache-line-size = <64>;
102 i-cache-sets = <128>;
103 d-cache-size = <32768>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 next-level-cache = <&l2_0>;
107 #cooling-cells = <2>;
112 compatible = "arm,cortex-a55";
114 enable-method = "psci";
115 performance-domains = <&performance 0>;
116 clock-frequency = <1701000000>;
117 capacity-dmips-mhz = <308>;
118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
119 i-cache-size = <32768>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <128>;
122 d-cache-size = <32768>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&l2_0>;
126 #cooling-cells = <2>;
131 compatible = "arm,cortex-a78";
133 enable-method = "psci";
134 performance-domains = <&performance 1>;
135 clock-frequency = <2171000000>;
136 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
138 i-cache-size = <65536>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <256>;
141 d-cache-size = <65536>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <256>;
144 next-level-cache = <&l2_1>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a78";
152 enable-method = "psci";
153 performance-domains = <&performance 1>;
154 clock-frequency = <2171000000>;
155 capacity-dmips-mhz = <1024>;
156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
157 i-cache-size = <65536>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <256>;
160 d-cache-size = <65536>;
161 d-cache-line-size = <64>;
162 d-cache-sets = <256>;
163 next-level-cache = <&l2_1>;
164 #cooling-cells = <2>;
169 compatible = "arm,cortex-a78";
171 enable-method = "psci";
172 performance-domains = <&performance 1>;
173 clock-frequency = <2171000000>;
174 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
176 i-cache-size = <65536>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <65536>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&l2_1>;
183 #cooling-cells = <2>;
188 compatible = "arm,cortex-a78";
190 enable-method = "psci";
191 performance-domains = <&performance 1>;
192 clock-frequency = <2171000000>;
193 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
195 i-cache-size = <65536>;
196 i-cache-line-size = <64>;
197 i-cache-sets = <256>;
198 d-cache-size = <65536>;
199 d-cache-line-size = <64>;
200 d-cache-sets = <256>;
201 next-level-cache = <&l2_1>;
202 #cooling-cells = <2>;
205 cpu-map {
241 idle-states {
242 entry-method = "psci";
244 cpu_ret_l: cpu-retention-l {
245 compatible = "arm,idle-state";
246 arm,psci-suspend-param = <0x00010001>;
247 local-timer-stop;
248 entry-latency-us = <50>;
249 exit-latency-us = <95>;
250 min-residency-us = <580>;
253 cpu_ret_b: cpu-retention-b {
254 compatible = "arm,idle-state";
255 arm,psci-suspend-param = <0x00010001>;
256 local-timer-stop;
257 entry-latency-us = <45>;
258 exit-latency-us = <140>;
259 min-residency-us = <740>;
262 cpu_off_l: cpu-off-l {
263 compatible = "arm,idle-state";
264 arm,psci-suspend-param = <0x01010002>;
265 local-timer-stop;
266 entry-latency-us = <55>;
267 exit-latency-us = <155>;
268 min-residency-us = <840>;
271 cpu_off_b: cpu-off-b {
272 compatible = "arm,idle-state";
273 arm,psci-suspend-param = <0x01010002>;
274 local-timer-stop;
275 entry-latency-us = <50>;
276 exit-latency-us = <200>;
277 min-residency-us = <1000>;
281 l2_0: l2-cache0 {
283 cache-level = <2>;
284 cache-size = <131072>;
285 cache-line-size = <64>;
286 cache-sets = <512>;
287 next-level-cache = <&l3_0>;
288 cache-unified;
291 l2_1: l2-cache1 {
293 cache-level = <2>;
294 cache-size = <262144>;
295 cache-line-size = <64>;
296 cache-sets = <512>;
297 next-level-cache = <&l3_0>;
298 cache-unified;
301 l3_0: l3-cache {
303 cache-level = <3>;
304 cache-size = <2097152>;
305 cache-line-size = <64>;
306 cache-sets = <2048>;
307 cache-unified;
311 dsu-pmu {
312 compatible = "arm,dsu-pmu";
319 dmic_codec: dmic-codec {
320 compatible = "dmic-codec";
321 num-channels = <2>;
322 wakeup-delay-ms = <50>;
325 sound: mt8195-sound {
330 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clock";
332 #clock-cells = <0>;
334 clock-div = <2>;
335 clock-mult = <1>;
336 clock-output-names = "clk13m";
339 clk26m: oscillator-26m {
340 compatible = "fixed-clock";
341 #clock-cells = <0>;
342 clock-frequency = <26000000>;
343 clock-output-names = "clk26m";
346 clk32k: oscillator-32k {
347 compatible = "fixed-clock";
348 #clock-cells = <0>;
349 clock-frequency = <32768>;
350 clock-output-names = "clk32k";
353 performance: performance-controller@11bc10 {
354 compatible = "mediatek,cpufreq-hw";
356 #performance-domain-cells = <1>;
359 gpu_opp_table: opp-table-gpu {
360 compatible = "operating-points-v2";
361 opp-shared;
363 opp-390000000 {
364 opp-hz = /bits/ 64 <390000000>;
365 opp-microvolt = <625000>;
367 opp-410000000 {
368 opp-hz = /bits/ 64 <410000000>;
369 opp-microvolt = <631250>;
371 opp-431000000 {
372 opp-hz = /bits/ 64 <431000000>;
373 opp-microvolt = <631250>;
375 opp-473000000 {
376 opp-hz = /bits/ 64 <473000000>;
377 opp-microvolt = <637500>;
379 opp-515000000 {
380 opp-hz = /bits/ 64 <515000000>;
381 opp-microvolt = <637500>;
383 opp-556000000 {
384 opp-hz = /bits/ 64 <556000000>;
385 opp-microvolt = <643750>;
387 opp-598000000 {
388 opp-hz = /bits/ 64 <598000000>;
389 opp-microvolt = <650000>;
391 opp-640000000 {
392 opp-hz = /bits/ 64 <640000000>;
393 opp-microvolt = <650000>;
395 opp-670000000 {
396 opp-hz = /bits/ 64 <670000000>;
397 opp-microvolt = <662500>;
399 opp-700000000 {
400 opp-hz = /bits/ 64 <700000000>;
401 opp-microvolt = <675000>;
403 opp-730000000 {
404 opp-hz = /bits/ 64 <730000000>;
405 opp-microvolt = <687500>;
407 opp-760000000 {
408 opp-hz = /bits/ 64 <760000000>;
409 opp-microvolt = <700000>;
411 opp-790000000 {
412 opp-hz = /bits/ 64 <790000000>;
413 opp-microvolt = <712500>;
415 opp-820000000 {
416 opp-hz = /bits/ 64 <820000000>;
417 opp-microvolt = <725000>;
419 opp-850000000 {
420 opp-hz = /bits/ 64 <850000000>;
421 opp-microvolt = <737500>;
423 opp-880000000 {
424 opp-hz = /bits/ 64 <880000000>;
425 opp-microvolt = <750000>;
429 pmu-a55 {
430 compatible = "arm,cortex-a55-pmu";
431 interrupt-parent = <&gic>;
435 pmu-a78 {
436 compatible = "arm,cortex-a78-pmu";
437 interrupt-parent = <&gic>;
442 compatible = "arm,psci-1.0";
447 compatible = "arm,armv8-timer";
448 interrupt-parent = <&gic>;
456 #address-cells = <2>;
457 #size-cells = <2>;
458 compatible = "simple-bus";
460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
462 gic: interrupt-controller@c000000 {
463 compatible = "arm,gic-v3";
464 #interrupt-cells = <4>;
465 #redistributor-regions = <1>;
466 interrupt-parent = <&gic>;
467 interrupt-controller;
472 ppi-partitions {
473 ppi_cluster0: interrupt-partition-0 {
477 ppi_cluster1: interrupt-partition-1 {
484 compatible = "mediatek,mt8195-topckgen", "syscon";
486 #clock-cells = <1>;
490 compatible = "mediatek,mt8195-infracfg_ao", "syscon";
492 #clock-cells = <1>;
493 #reset-cells = <1>;
497 compatible = "mediatek,mt8195-pericfg", "syscon";
499 #clock-cells = <1>;
503 compatible = "mediatek,mt8195-pinctrl";
512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
515 gpio-controller;
516 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0 0 144>;
518 interrupt-controller;
520 #interrupt-cells = <2>;
524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
528 spm: power-controller {
529 compatible = "mediatek,mt8195-power-controller";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 #power-domain-cells = <1>;
535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <1>;
541 power-domain@MT8195_POWER_DOMAIN_MFG1 {
545 clock-names = "mfg", "alt";
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #power-domain-cells = <1>;
551 power-domain@MT8195_POWER_DOMAIN_MFG2 {
553 #power-domain-cells = <0>;
556 power-domain@MT8195_POWER_DOMAIN_MFG3 {
558 #power-domain-cells = <0>;
561 power-domain@MT8195_POWER_DOMAIN_MFG4 {
563 #power-domain-cells = <0>;
566 power-domain@MT8195_POWER_DOMAIN_MFG5 {
568 #power-domain-cells = <0>;
571 power-domain@MT8195_POWER_DOMAIN_MFG6 {
573 #power-domain-cells = <0>;
578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 "vppsys0-18";
616 #address-cells = <1>;
617 #size-cells = <0>;
618 #power-domain-cells = <1>;
620 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
623 clock-names = "vdec1-0";
625 #power-domain-cells = <0>;
628 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
631 clock-names = "venc1-larb";
633 #power-domain-cells = <0>;
636 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
645 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
646 "vdosys0-2", "vdosys0-3",
647 "vdosys0-4", "vdosys0-5";
649 #address-cells = <1>;
650 #size-cells = <0>;
651 #power-domain-cells = <1>;
653 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
658 clock-names = "vppsys1", "vppsys1-0",
659 "vppsys1-1";
661 #power-domain-cells = <0>;
664 power-domain@MT8195_POWER_DOMAIN_WPESYS {
670 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
671 "wepsys-3";
673 #power-domain-cells = <0>;
676 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
679 clock-names = "vdec0-0";
681 #power-domain-cells = <0>;
684 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
687 clock-names = "vdec2-0";
689 #power-domain-cells = <0>;
692 power-domain@MT8195_POWER_DOMAIN_VENC {
695 clock-names = "venc0-larb";
697 #power-domain-cells = <0>;
700 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
706 clock-names = "vdosys1", "vdosys1-0",
707 "vdosys1-1", "vdosys1-2";
709 #address-cells = <1>;
710 #size-cells = <0>;
711 #power-domain-cells = <1>;
713 power-domain@MT8195_POWER_DOMAIN_DP_TX {
716 #power-domain-cells = <0>;
719 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
722 #power-domain-cells = <0>;
725 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
728 clock-names = "hdmi_tx";
729 #power-domain-cells = <0>;
733 power-domain@MT8195_POWER_DOMAIN_IMG {
737 clock-names = "img-0", "img-1";
739 #address-cells = <1>;
740 #size-cells = <0>;
741 #power-domain-cells = <1>;
743 power-domain@MT8195_POWER_DOMAIN_DIP {
745 #power-domain-cells = <0>;
748 power-domain@MT8195_POWER_DOMAIN_IPE {
753 clock-names = "ipe", "ipe-0", "ipe-1";
755 #power-domain-cells = <0>;
759 power-domain@MT8195_POWER_DOMAIN_CAM {
761 clocks = <&camsys CLK_CAM_LARB13>,
762 <&camsys CLK_CAM_LARB14>,
763 <&camsys CLK_CAM_CAM2MM0_GALS>,
764 <&camsys CLK_CAM_CAM2MM1_GALS>,
765 <&camsys CLK_CAM_CAM2SYS_GALS>;
766 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
767 "cam-4";
769 #address-cells = <1>;
770 #size-cells = <0>;
771 #power-domain-cells = <1>;
773 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
775 #power-domain-cells = <0>;
778 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
780 #power-domain-cells = <0>;
783 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
785 #power-domain-cells = <0>;
791 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
794 #power-domain-cells = <0>;
797 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
800 #power-domain-cells = <0>;
803 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
805 #power-domain-cells = <0>;
808 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
810 #power-domain-cells = <0>;
813 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
817 clock-names = "csi_rx_top", "csi_rx_top1";
818 #power-domain-cells = <0>;
821 power-domain@MT8195_POWER_DOMAIN_ETHER {
824 clock-names = "ether";
825 #power-domain-cells = <0>;
828 power-domain@MT8195_POWER_DOMAIN_ADSP {
832 clock-names = "adsp", "adsp1";
833 #address-cells = <1>;
834 #size-cells = <0>;
836 #power-domain-cells = <1>;
838 power-domain@MT8195_POWER_DOMAIN_AUDIO {
844 clock-names = "audio", "audio1", "audio2",
847 #power-domain-cells = <0>;
854 compatible = "mediatek,mt8195-wdt";
855 mediatek,disable-extrst;
857 #reset-cells = <1>;
861 compatible = "mediatek,mt8195-apmixedsys", "syscon";
863 #clock-cells = <1>;
867 compatible = "mediatek,mt8195-timer",
868 "mediatek,mt6765-timer";
875 compatible = "mediatek,mt8195-pwrap", "syscon";
877 reg-names = "pwrap";
881 clock-names = "spi", "wrap";
882 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
883 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
887 compatible = "mediatek,mt8195-spmi";
890 reg-names = "pmif", "spmimst";
894 clock-names = "pmif_sys_ck",
897 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
898 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
901 iommu_infra: infra-iommu@10315000 {
902 compatible = "mediatek,mt8195-iommu-infra";
909 #iommu-cells = <1>;
913 compatible = "mediatek,mt8195-gce";
916 #mbox-cells = <2>;
921 compatible = "mediatek,mt8195-gce";
924 #mbox-cells = <2>;
929 compatible = "mediatek,mt8195-scp";
933 reg-names = "sram", "cfg", "l1tcm";
938 scp_adsp: clock-controller@10720000 {
939 compatible = "mediatek,mt8195-scp_adsp";
941 #clock-cells = <1>;
945 compatible = "mediatek,mt8195-dsp";
948 reg-names = "cfg", "sram";
955 clock-names = "adsp_sel",
961 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
962 mbox-names = "rx", "tx";
968 compatible = "mediatek,mt8195-adsp-mbox";
969 #mbox-cells = <0>;
975 compatible = "mediatek,mt8195-adsp-mbox";
976 #mbox-cells = <0>;
981 afe: mt8195-afe-pcm@10890000 {
982 compatible = "mediatek,mt8195-audio";
985 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
988 reset-names = "audiosys";
1008 clock-names = "clk26m",
1031 compatible = "mediatek,mt8195-uart",
1032 "mediatek,mt6577-uart";
1036 clock-names = "baud", "bus";
1041 compatible = "mediatek,mt8195-uart",
1042 "mediatek,mt6577-uart";
1046 clock-names = "baud", "bus";
1051 compatible = "mediatek,mt8195-uart",
1052 "mediatek,mt6577-uart";
1056 clock-names = "baud", "bus";
1061 compatible = "mediatek,mt8195-uart",
1062 "mediatek,mt6577-uart";
1066 clock-names = "baud", "bus";
1071 compatible = "mediatek,mt8195-uart",
1072 "mediatek,mt6577-uart";
1076 clock-names = "baud", "bus";
1081 compatible = "mediatek,mt8195-uart",
1082 "mediatek,mt6577-uart";
1086 clock-names = "baud", "bus";
1091 compatible = "mediatek,mt8195-auxadc",
1092 "mediatek,mt8173-auxadc";
1095 clock-names = "main";
1096 #io-channel-cells = <1>;
1101 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1103 #clock-cells = <1>;
1107 compatible = "mediatek,mt8195-spi",
1108 "mediatek,mt6765-spi";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1116 clock-names = "parent-clk", "sel-clk", "spi-clk";
1120 lvts_ap: thermal-sensor@1100b000 {
1121 compatible = "mediatek,mt8195-lvts-ap";
1126 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1127 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1128 #thermal-sensor-cells = <1>;
1132 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1135 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1136 #pwm-cells = <2>;
1139 clock-names = "main", "mm";
1144 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1147 #pwm-cells = <2>;
1150 clock-names = "main", "mm";
1155 compatible = "mediatek,mt8195-spi",
1156 "mediatek,mt6765-spi";
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1164 clock-names = "parent-clk", "sel-clk", "spi-clk";
1169 compatible = "mediatek,mt8195-spi",
1170 "mediatek,mt6765-spi";
1171 #address-cells = <1>;
1172 #size-cells = <0>;
1178 clock-names = "parent-clk", "sel-clk", "spi-clk";
1183 compatible = "mediatek,mt8195-spi",
1184 "mediatek,mt6765-spi";
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1192 clock-names = "parent-clk", "sel-clk", "spi-clk";
1197 compatible = "mediatek,mt8195-spi",
1198 "mediatek,mt6765-spi";
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1206 clock-names = "parent-clk", "sel-clk", "spi-clk";
1211 compatible = "mediatek,mt8195-spi",
1212 "mediatek,mt6765-spi";
1213 #address-cells = <1>;
1214 #size-cells = <0>;
1220 clock-names = "parent-clk", "sel-clk", "spi-clk";
1225 compatible = "mediatek,mt8195-spi-slave";
1229 clock-names = "spi";
1230 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1231 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1236 compatible = "mediatek,mt8195-spi-slave";
1240 clock-names = "spi";
1241 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1242 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1247 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1250 interrupt-names = "macirq";
1251 clock-names = "axi",
1263 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1266 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1269 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1271 snps,axi-config = <&stmmac_axi_setup>;
1272 snps,mtl-rx-config = <&mtl_rx_setup>;
1273 snps,mtl-tx-config = <&mtl_tx_setup>;
1276 snps,clk-csr = <0>;
1280 compatible = "snps,dwmac-mdio";
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1285 stmmac_axi_setup: stmmac-axi-config {
1291 mtl_rx_setup: rx-queues-config {
1292 snps,rx-queues-to-use = <4>;
1293 snps,rx-sched-sp;
1295 snps,dcb-algorithm;
1296 snps,map-to-dma-channel = <0x0>;
1299 snps,dcb-algorithm;
1300 snps,map-to-dma-channel = <0x0>;
1303 snps,dcb-algorithm;
1304 snps,map-to-dma-channel = <0x0>;
1307 snps,dcb-algorithm;
1308 snps,map-to-dma-channel = <0x0>;
1312 mtl_tx_setup: tx-queues-config {
1313 snps,tx-queues-to-use = <4>;
1314 snps,tx-sched-wrr;
1317 snps,dcb-algorithm;
1322 snps,dcb-algorithm;
1327 snps,dcb-algorithm;
1332 snps,dcb-algorithm;
1339 compatible = "mediatek,mt8195-xhci",
1340 "mediatek,mtk-xhci";
1343 reg-names = "mac", "ippc";
1347 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1349 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1356 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1358 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1359 wakeup-source;
1364 compatible = "mediatek,mt8195-mmc",
1365 "mediatek,mt8183-mmc";
1372 clock-names = "source", "hclk", "source_cg";
1377 compatible = "mediatek,mt8195-mmc",
1378 "mediatek,mt8183-mmc";
1385 clock-names = "source", "hclk", "source_cg";
1386 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1387 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1392 compatible = "mediatek,mt8195-mmc",
1393 "mediatek,mt8183-mmc";
1400 clock-names = "source", "hclk", "source_cg";
1401 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1402 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1406 lvts_mcu: thermal-sensor@11278000 {
1407 compatible = "mediatek,mt8195-lvts-mcu";
1412 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1413 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1414 #thermal-sensor-cells = <1>;
1418 compatible = "mediatek,mt8195-xhci",
1419 "mediatek,mtk-xhci";
1422 reg-names = "mac", "ippc";
1425 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1427 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1434 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1436 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1437 wakeup-source;
1442 compatible = "mediatek,mt8195-xhci",
1443 "mediatek,mtk-xhci";
1446 reg-names = "mac", "ippc";
1449 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1451 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1458 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1460 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1461 wakeup-source;
1466 compatible = "mediatek,mt8195-xhci",
1467 "mediatek,mtk-xhci";
1470 reg-names = "mac", "ippc";
1473 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1475 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1482 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1484 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1485 wakeup-source;
1490 compatible = "mediatek,mt8195-pcie",
1491 "mediatek,mt8192-pcie";
1493 #address-cells = <3>;
1494 #size-cells = <2>;
1496 reg-names = "pcie-mac";
1498 bus-range = <0x00 0xff>;
1504 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1505 iommu-map-mask = <0x0>;
1513 clock-names = "pl_250m", "tl_26m", "tl_96m",
1515 assigned-clocks = <&topckgen CLK_TOP_TL>;
1516 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1519 phy-names = "pcie-phy";
1521 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1524 reset-names = "mac";
1526 #interrupt-cells = <1>;
1527 interrupt-map-mask = <0 0 0 7>;
1528 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1534 pcie_intc0: interrupt-controller {
1535 interrupt-controller;
1536 #address-cells = <0>;
1537 #interrupt-cells = <1>;
1542 compatible = "mediatek,mt8195-pcie",
1543 "mediatek,mt8192-pcie";
1545 #address-cells = <3>;
1546 #size-cells = <2>;
1548 reg-names = "pcie-mac";
1550 bus-range = <0x00 0xff>;
1556 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1557 iommu-map-mask = <0x0>;
1566 clock-names = "pl_250m", "tl_26m", "tl_96m",
1568 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1569 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1572 phy-names = "pcie-phy";
1573 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1576 reset-names = "mac";
1578 #interrupt-cells = <1>;
1579 interrupt-map-mask = <0 0 0 7>;
1580 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1586 pcie_intc1: interrupt-controller {
1587 interrupt-controller;
1588 #address-cells = <0>;
1589 #interrupt-cells = <1>;
1594 compatible = "mediatek,mt8195-nor",
1595 "mediatek,mt8173-nor";
1601 clock-names = "spi", "sf", "axi";
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1608 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1610 #address-cells = <1>;
1611 #size-cells = <1>;
1612 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1616 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1620 u3_intr_p0: usb3-intr@185 {
1624 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1628 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1632 comb_intr_p1: usb3-intr@187 {
1636 u2_intr_p0: usb2-intr-p0@188,1 {
1640 u2_intr_p1: usb2-intr-p1@188,2 {
1644 u2_intr_p2: usb2-intr-p2@189,1 {
1648 u2_intr_p3: usb2-intr-p3@189,2 {
1652 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1656 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1660 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1664 pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1668 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1672 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1676 pciephy_glb_intr: pciephy-glb-intr@193 {
1680 dp_calibration: dp-data@1ac {
1683 lvts_efuse_data1: lvts1-calib@1bc {
1686 lvts_efuse_data2: lvts2-calib@1d0 {
1691 u3phy2: t-phy@11c40000 {
1692 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1693 #address-cells = <1>;
1694 #size-cells = <1>;
1698 u2port2: usb-phy@0 {
1701 clock-names = "ref";
1702 #phy-cells = <1>;
1706 u3phy3: t-phy@11c50000 {
1707 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1708 #address-cells = <1>;
1709 #size-cells = <1>;
1713 u2port3: usb-phy@0 {
1716 clock-names = "ref";
1717 #phy-cells = <1>;
1722 compatible = "mediatek,mt8195-i2c",
1723 "mediatek,mt8192-i2c";
1727 clock-div = <1>;
1730 clock-names = "main", "dma";
1731 #address-cells = <1>;
1732 #size-cells = <0>;
1737 compatible = "mediatek,mt8195-i2c",
1738 "mediatek,mt8192-i2c";
1742 clock-div = <1>;
1745 clock-names = "main", "dma";
1746 #address-cells = <1>;
1747 #size-cells = <0>;
1752 compatible = "mediatek,mt8195-i2c",
1753 "mediatek,mt8192-i2c";
1757 clock-div = <1>;
1760 clock-names = "main", "dma";
1761 #address-cells = <1>;
1762 #size-cells = <0>;
1766 imp_iic_wrap_s: clock-controller@11d03000 {
1767 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1769 #clock-cells = <1>;
1773 compatible = "mediatek,mt8195-i2c",
1774 "mediatek,mt8192-i2c";
1778 clock-div = <1>;
1781 clock-names = "main", "dma";
1782 #address-cells = <1>;
1783 #size-cells = <0>;
1788 compatible = "mediatek,mt8195-i2c",
1789 "mediatek,mt8192-i2c";
1793 clock-div = <1>;
1796 clock-names = "main", "dma";
1797 #address-cells = <1>;
1798 #size-cells = <0>;
1803 compatible = "mediatek,mt8195-i2c",
1804 "mediatek,mt8192-i2c";
1808 clock-div = <1>;
1811 clock-names = "main", "dma";
1812 #address-cells = <1>;
1813 #size-cells = <0>;
1818 compatible = "mediatek,mt8195-i2c",
1819 "mediatek,mt8192-i2c";
1823 clock-div = <1>;
1826 clock-names = "main", "dma";
1827 #address-cells = <1>;
1828 #size-cells = <0>;
1833 compatible = "mediatek,mt8195-i2c",
1834 "mediatek,mt8192-i2c";
1838 clock-div = <1>;
1841 clock-names = "main", "dma";
1842 #address-cells = <1>;
1843 #size-cells = <0>;
1847 imp_iic_wrap_w: clock-controller@11e05000 {
1848 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1850 #clock-cells = <1>;
1853 u3phy1: t-phy@11e30000 {
1854 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1855 #address-cells = <1>;
1856 #size-cells = <1>;
1858 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1861 u2port1: usb-phy@0 {
1865 clock-names = "ref", "da_ref";
1866 #phy-cells = <1>;
1869 u3port1: usb-phy@700 {
1873 clock-names = "ref", "da_ref";
1874 nvmem-cells = <&comb_intr_p1>,
1877 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1878 #phy-cells = <1>;
1882 u3phy0: t-phy@11e40000 {
1883 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1884 #address-cells = <1>;
1885 #size-cells = <1>;
1889 u2port0: usb-phy@0 {
1893 clock-names = "ref", "da_ref";
1894 #phy-cells = <1>;
1897 u3port0: usb-phy@700 {
1901 clock-names = "ref", "da_ref";
1902 nvmem-cells = <&u3_intr_p0>,
1905 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1906 #phy-cells = <1>;
1911 compatible = "mediatek,mt8195-pcie-phy";
1913 reg-names = "sif";
1914 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1918 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1922 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1923 #phy-cells = <0>;
1927 ufsphy: ufs-phy@11fa0000 {
1928 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1931 clock-names = "unipro", "mp";
1932 #phy-cells = <0>;
1937 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
1938 "arm,mali-valhall-jm";
1945 interrupt-names = "job", "mmu", "gpu";
1946 operating-points-v2 = <&gpu_opp_table>;
1947 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
1952 power-domain-names = "core0", "core1", "core2", "core3", "core4";
1956 mfgcfg: clock-controller@13fbf000 {
1957 compatible = "mediatek,mt8195-mfgcfg";
1959 #clock-cells = <1>;
1963 compatible = "mediatek,mt8195-vppsys0", "syscon";
1965 #clock-cells = <1>;
1966 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
1970 compatible = "mediatek,mt8195-vpp-mutex";
1973 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
1975 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1979 compatible = "mediatek,mt8195-smi-sub-common";
1984 clock-names = "apb", "smi", "gals0";
1986 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1990 compatible = "mediatek,mt8195-smi-sub-common";
1995 clock-names = "apb", "smi", "gals0";
1997 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2001 compatible = "mediatek,mt8195-smi-common-vpp";
2007 clock-names = "apb", "smi", "gals0", "gals1";
2008 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2012 compatible = "mediatek,mt8195-smi-larb";
2014 mediatek,larb-id = <4>;
2018 clock-names = "apb", "smi";
2019 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2023 compatible = "mediatek,mt8195-iommu-vpp";
2031 clock-names = "bclk";
2032 #iommu-cells = <1>;
2033 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2036 wpesys: clock-controller@14e00000 {
2037 compatible = "mediatek,mt8195-wpesys";
2039 #clock-cells = <1>;
2042 wpesys_vpp0: clock-controller@14e02000 {
2043 compatible = "mediatek,mt8195-wpesys_vpp0";
2045 #clock-cells = <1>;
2048 wpesys_vpp1: clock-controller@14e03000 {
2049 compatible = "mediatek,mt8195-wpesys_vpp1";
2051 #clock-cells = <1>;
2055 compatible = "mediatek,mt8195-smi-larb";
2057 mediatek,larb-id = <7>;
2061 clock-names = "apb", "smi";
2062 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2066 compatible = "mediatek,mt8195-smi-larb";
2068 mediatek,larb-id = <8>;
2073 clock-names = "apb", "smi", "gals";
2074 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2078 compatible = "mediatek,mt8195-vppsys1", "syscon";
2080 #clock-cells = <1>;
2081 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
2085 compatible = "mediatek,mt8195-vpp-mutex";
2088 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2090 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2094 compatible = "mediatek,mt8195-smi-larb";
2096 mediatek,larb-id = <5>;
2101 clock-names = "apb", "smi", "gals";
2102 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2106 compatible = "mediatek,mt8195-smi-larb";
2108 mediatek,larb-id = <6>;
2113 clock-names = "apb", "smi", "gals";
2114 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2117 imgsys: clock-controller@15000000 {
2118 compatible = "mediatek,mt8195-imgsys";
2120 #clock-cells = <1>;
2124 compatible = "mediatek,mt8195-smi-larb";
2126 mediatek,larb-id = <9>;
2131 clock-names = "apb", "smi", "gals";
2132 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2136 compatible = "mediatek,mt8195-smi-sub-common";
2141 clock-names = "apb", "smi", "gals0";
2143 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2147 compatible = "mediatek,mt8195-smi-sub-common";
2152 clock-names = "apb", "smi", "gals0";
2154 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2157 imgsys1_dip_top: clock-controller@15110000 {
2158 compatible = "mediatek,mt8195-imgsys1_dip_top";
2160 #clock-cells = <1>;
2164 compatible = "mediatek,mt8195-smi-larb";
2166 mediatek,larb-id = <10>;
2170 clock-names = "apb", "smi";
2171 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2174 imgsys1_dip_nr: clock-controller@15130000 {
2175 compatible = "mediatek,mt8195-imgsys1_dip_nr";
2177 #clock-cells = <1>;
2180 imgsys1_wpe: clock-controller@15220000 {
2181 compatible = "mediatek,mt8195-imgsys1_wpe";
2183 #clock-cells = <1>;
2187 compatible = "mediatek,mt8195-smi-larb";
2189 mediatek,larb-id = <11>;
2193 clock-names = "apb", "smi";
2194 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2197 ipesys: clock-controller@15330000 {
2198 compatible = "mediatek,mt8195-ipesys";
2200 #clock-cells = <1>;
2204 compatible = "mediatek,mt8195-smi-larb";
2206 mediatek,larb-id = <12>;
2210 clock-names = "apb", "smi";
2211 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2214 camsys: clock-controller@16000000 { label
2215 compatible = "mediatek,mt8195-camsys";
2217 #clock-cells = <1>;
2221 compatible = "mediatek,mt8195-smi-larb";
2223 mediatek,larb-id = <13>;
2225 clocks = <&camsys CLK_CAM_LARB13>,
2226 <&camsys CLK_CAM_LARB13>,
2227 <&camsys CLK_CAM_CAM2MM0_GALS>;
2228 clock-names = "apb", "smi", "gals";
2229 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2233 compatible = "mediatek,mt8195-smi-larb";
2235 mediatek,larb-id = <14>;
2237 clocks = <&camsys CLK_CAM_LARB14>,
2238 <&camsys CLK_CAM_LARB14>;
2239 clock-names = "apb", "smi";
2240 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2244 compatible = "mediatek,mt8195-smi-sub-common";
2246 clocks = <&camsys CLK_CAM_LARB13>,
2247 <&camsys CLK_CAM_LARB13>,
2248 <&camsys CLK_CAM_CAM2MM0_GALS>;
2249 clock-names = "apb", "smi", "gals0";
2251 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2255 compatible = "mediatek,mt8195-smi-sub-common";
2257 clocks = <&camsys CLK_CAM_LARB14>,
2258 <&camsys CLK_CAM_CAM2MM1_GALS>,
2260 clock-names = "apb", "smi", "gals0";
2262 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2266 compatible = "mediatek,mt8195-smi-larb";
2268 mediatek,larb-id = <16>;
2272 clock-names = "apb", "smi";
2273 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2277 compatible = "mediatek,mt8195-smi-larb";
2279 mediatek,larb-id = <17>;
2283 clock-names = "apb", "smi";
2284 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2288 compatible = "mediatek,mt8195-smi-larb";
2290 mediatek,larb-id = <27>;
2294 clock-names = "apb", "smi";
2295 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2299 compatible = "mediatek,mt8195-smi-larb";
2301 mediatek,larb-id = <28>;
2305 clock-names = "apb", "smi";
2306 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2309 camsys_rawa: clock-controller@1604f000 {
2310 compatible = "mediatek,mt8195-camsys_rawa";
2312 #clock-cells = <1>;
2315 camsys_yuva: clock-controller@1606f000 {
2316 compatible = "mediatek,mt8195-camsys_yuva";
2318 #clock-cells = <1>;
2321 camsys_rawb: clock-controller@1608f000 {
2322 compatible = "mediatek,mt8195-camsys_rawb";
2324 #clock-cells = <1>;
2327 camsys_yuvb: clock-controller@160af000 {
2328 compatible = "mediatek,mt8195-camsys_yuvb";
2330 #clock-cells = <1>;
2333 camsys_mraw: clock-controller@16140000 {
2334 compatible = "mediatek,mt8195-camsys_mraw";
2336 #clock-cells = <1>;
2340 compatible = "mediatek,mt8195-smi-larb";
2342 mediatek,larb-id = <25>;
2344 clocks = <&camsys CLK_CAM_LARB13>,
2346 <&camsys CLK_CAM_CAM2MM0_GALS>;
2347 clock-names = "apb", "smi", "gals";
2348 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2352 compatible = "mediatek,mt8195-smi-larb";
2354 mediatek,larb-id = <26>;
2358 clock-names = "apb", "smi";
2359 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2363 ccusys: clock-controller@17200000 {
2364 compatible = "mediatek,mt8195-ccusys";
2366 #clock-cells = <1>;
2370 compatible = "mediatek,mt8195-smi-larb";
2372 mediatek,larb-id = <18>;
2376 clock-names = "apb", "smi";
2377 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2380 video-codec@18000000 {
2381 compatible = "mediatek,mt8195-vcodec-dec";
2384 #address-cells = <2>;
2385 #size-cells = <2>;
2390 video-codec@2000 {
2391 compatible = "mediatek,mtk-vcodec-lat-soc";
2399 clock-names = "sel", "vdec", "lat", "top";
2400 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2401 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2402 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2405 video-codec@10000 {
2406 compatible = "mediatek,mtk-vcodec-lat";
2419 clock-names = "sel", "vdec", "lat", "top";
2420 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2421 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2422 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2425 video-codec@25000 {
2426 compatible = "mediatek,mtk-vcodec-core";
2443 clock-names = "sel", "vdec", "lat", "top";
2444 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2445 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2446 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2451 compatible = "mediatek,mt8195-smi-larb";
2453 mediatek,larb-id = <24>;
2457 clock-names = "apb", "smi";
2458 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2462 compatible = "mediatek,mt8195-smi-larb";
2464 mediatek,larb-id = <23>;
2468 clock-names = "apb", "smi";
2469 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2472 vdecsys_soc: clock-controller@1800f000 {
2473 compatible = "mediatek,mt8195-vdecsys_soc";
2475 #clock-cells = <1>;
2479 compatible = "mediatek,mt8195-smi-larb";
2481 mediatek,larb-id = <21>;
2485 clock-names = "apb", "smi";
2486 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2489 vdecsys: clock-controller@1802f000 {
2490 compatible = "mediatek,mt8195-vdecsys";
2492 #clock-cells = <1>;
2496 compatible = "mediatek,mt8195-smi-larb";
2498 mediatek,larb-id = <22>;
2502 clock-names = "apb", "smi";
2503 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2506 vdecsys_core1: clock-controller@1803f000 {
2507 compatible = "mediatek,mt8195-vdecsys_core1";
2509 #clock-cells = <1>;
2512 apusys_pll: clock-controller@190f3000 {
2513 compatible = "mediatek,mt8195-apusys_pll";
2515 #clock-cells = <1>;
2518 vencsys: clock-controller@1a000000 {
2519 compatible = "mediatek,mt8195-vencsys";
2521 #clock-cells = <1>;
2525 compatible = "mediatek,mt8195-smi-larb";
2527 mediatek,larb-id = <19>;
2531 clock-names = "apb", "smi";
2532 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2535 venc: video-codec@1a020000 {
2536 compatible = "mediatek,mt8195-vcodec-enc";
2550 clock-names = "venc_sel";
2551 assigned-clocks = <&topckgen CLK_TOP_VENC>;
2552 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2553 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2554 #address-cells = <2>;
2555 #size-cells = <2>;
2558 jpgdec-master {
2559 compatible = "mediatek,mt8195-jpgdec";
2560 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2567 #address-cells = <2>;
2568 #size-cells = <2>;
2572 compatible = "mediatek,mt8195-jpgdec-hw";
2582 clock-names = "jpgdec";
2583 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2587 compatible = "mediatek,mt8195-jpgdec-hw";
2597 clock-names = "jpgdec";
2598 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2602 compatible = "mediatek,mt8195-jpgdec-hw";
2612 clock-names = "jpgdec";
2613 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2617 vencsys_core1: clock-controller@1b000000 {
2618 compatible = "mediatek,mt8195-vencsys_core1";
2620 #clock-cells = <1>;
2624 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
2627 #clock-cells = <1>;
2628 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
2632 jpgenc-master {
2633 compatible = "mediatek,mt8195-jpgenc";
2634 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2639 #address-cells = <2>;
2640 #size-cells = <2>;
2644 compatible = "mediatek,mt8195-jpgenc-hw";
2652 clock-names = "jpgenc";
2653 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2657 compatible = "mediatek,mt8195-jpgenc-hw";
2665 clock-names = "jpgenc";
2666 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2671 compatible = "mediatek,mt8195-smi-larb";
2673 mediatek,larb-id = <20>;
2678 clock-names = "apb", "smi", "gals";
2679 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2683 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
2686 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2689 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
2693 compatible = "mediatek,mt8195-disp-rdma";
2696 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2699 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
2703 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
2706 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2708 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
2712 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
2715 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2717 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
2721 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
2724 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2726 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
2730 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
2733 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2735 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
2739 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
2742 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2744 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
2748 compatible = "mediatek,mt8195-disp-dsc";
2751 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2753 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
2757 compatible = "mediatek,mt8195-disp-merge";
2760 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2762 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
2765 dp_intf0: dp-intf@1c015000 {
2766 compatible = "mediatek,mt8195-dp-intf";
2772 clock-names = "pixel", "engine", "pll";
2777 compatible = "mediatek,mt8195-disp-mutex";
2780 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2782 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
2783 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
2787 compatible = "mediatek,mt8195-smi-larb";
2789 mediatek,larb-id = <0>;
2794 clock-names = "apb", "smi", "gals";
2795 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2799 compatible = "mediatek,mt8195-smi-larb";
2801 mediatek,larb-id = <1>;
2806 clock-names = "apb", "smi", "gals";
2807 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2811 compatible = "mediatek,mt8195-vdosys1", "syscon";
2814 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
2815 #clock-cells = <1>;
2816 #reset-cells = <1>;
2820 compatible = "mediatek,mt8195-smi-common-vdo";
2826 clock-names = "apb", "smi", "gals0", "gals1";
2827 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2832 compatible = "mediatek,mt8195-iommu-vdo";
2839 #iommu-cells = <1>;
2841 clock-names = "bclk";
2842 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2846 compatible = "mediatek,mt8195-disp-mutex";
2849 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2851 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
2852 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
2856 compatible = "mediatek,mt8195-smi-larb";
2858 mediatek,larb-id = <2>;
2863 clock-names = "apb", "smi", "gals";
2864 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2868 compatible = "mediatek,mt8195-smi-larb";
2870 mediatek,larb-id = <3>;
2875 clock-names = "apb", "smi", "gals";
2876 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2879 vdo1_rdma0: dma-controller@1c104000 {
2880 compatible = "mediatek,mt8195-vdo1-rdma";
2884 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2886 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
2887 #dma-cells = <1>;
2890 vdo1_rdma1: dma-controller@1c105000 {
2891 compatible = "mediatek,mt8195-vdo1-rdma";
2895 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2897 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
2898 #dma-cells = <1>;
2901 vdo1_rdma2: dma-controller@1c106000 {
2902 compatible = "mediatek,mt8195-vdo1-rdma";
2906 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2908 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
2909 #dma-cells = <1>;
2912 vdo1_rdma3: dma-controller@1c107000 {
2913 compatible = "mediatek,mt8195-vdo1-rdma";
2917 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2919 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
2920 #dma-cells = <1>;
2923 vdo1_rdma4: dma-controller@1c108000 {
2924 compatible = "mediatek,mt8195-vdo1-rdma";
2928 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2930 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
2931 #dma-cells = <1>;
2934 vdo1_rdma5: dma-controller@1c109000 {
2935 compatible = "mediatek,mt8195-vdo1-rdma";
2939 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2941 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
2942 #dma-cells = <1>;
2945 vdo1_rdma6: dma-controller@1c10a000 {
2946 compatible = "mediatek,mt8195-vdo1-rdma";
2950 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2952 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
2953 #dma-cells = <1>;
2956 vdo1_rdma7: dma-controller@1c10b000 {
2957 compatible = "mediatek,mt8195-vdo1-rdma";
2961 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2963 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
2964 #dma-cells = <1>;
2967 merge1: vpp-merge@1c10c000 {
2968 compatible = "mediatek,mt8195-disp-merge";
2973 clock-names = "merge","merge_async";
2974 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2975 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
2976 mediatek,merge-mute;
2980 merge2: vpp-merge@1c10d000 {
2981 compatible = "mediatek,mt8195-disp-merge";
2986 clock-names = "merge","merge_async";
2987 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2988 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
2989 mediatek,merge-mute;
2993 merge3: vpp-merge@1c10e000 {
2994 compatible = "mediatek,mt8195-disp-merge";
2999 clock-names = "merge","merge_async";
3000 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3001 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
3002 mediatek,merge-mute;
3006 merge4: vpp-merge@1c10f000 {
3007 compatible = "mediatek,mt8195-disp-merge";
3012 clock-names = "merge","merge_async";
3013 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3014 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3015 mediatek,merge-mute;
3019 merge5: vpp-merge@1c110000 {
3020 compatible = "mediatek,mt8195-disp-merge";
3025 clock-names = "merge","merge_async";
3026 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3027 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3028 mediatek,merge-fifo-en;
3032 dp_intf1: dp-intf@1c113000 {
3033 compatible = "mediatek,mt8195-dp-intf";
3036 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3040 clock-names = "pixel", "engine", "pll";
3044 ethdr0: hdr-engine@1c114000 {
3045 compatible = "mediatek,mt8195-disp-ethdr";
3053 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3055 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3075 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3079 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3088 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
3092 edp_tx: edp-tx@1c500000 {
3093 compatible = "mediatek,mt8195-edp-tx";
3095 nvmem-cells = <&dp_calibration>;
3096 nvmem-cell-names = "dp_calibration_data";
3097 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3099 max-linkrate-mhz = <8100>;
3103 dp_tx: dp-tx@1c600000 {
3104 compatible = "mediatek,mt8195-dp-tx";
3106 nvmem-cells = <&dp_calibration>;
3107 nvmem-cell-names = "dp_calibration_data";
3108 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3110 max-linkrate-mhz = <8100>;
3115 thermal_zones: thermal-zones {
3116 cpu0-thermal {
3117 polling-delay = <1000>;
3118 polling-delay-passive = <250>;
3119 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3122 cpu0_alert: trip-alert {
3128 cpu0_crit: trip-crit {
3135 cooling-maps {
3138 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3146 cpu1-thermal {
3147 polling-delay = <1000>;
3148 polling-delay-passive = <250>;
3149 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3152 cpu1_alert: trip-alert {
3158 cpu1_crit: trip-crit {
3165 cooling-maps {
3168 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3176 cpu2-thermal {
3177 polling-delay = <1000>;
3178 polling-delay-passive = <250>;
3179 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3182 cpu2_alert: trip-alert {
3188 cpu2_crit: trip-crit {
3195 cooling-maps {
3198 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3206 cpu3-thermal {
3207 polling-delay = <1000>;
3208 polling-delay-passive = <250>;
3209 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3212 cpu3_alert: trip-alert {
3218 cpu3_crit: trip-crit {
3225 cooling-maps {
3228 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3236 cpu4-thermal {
3237 polling-delay = <1000>;
3238 polling-delay-passive = <250>;
3239 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3242 cpu4_alert: trip-alert {
3248 cpu4_crit: trip-crit {
3255 cooling-maps {
3258 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3266 cpu5-thermal {
3267 polling-delay = <1000>;
3268 polling-delay-passive = <250>;
3269 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3272 cpu5_alert: trip-alert {
3278 cpu5_crit: trip-crit {
3285 cooling-maps {
3288 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3296 cpu6-thermal {
3297 polling-delay = <1000>;
3298 polling-delay-passive = <250>;
3299 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3302 cpu6_alert: trip-alert {
3308 cpu6_crit: trip-crit {
3315 cooling-maps {
3318 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3326 cpu7-thermal {
3327 polling-delay = <1000>;
3328 polling-delay-passive = <250>;
3329 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3332 cpu7_alert: trip-alert {
3338 cpu7_crit: trip-crit {
3345 cooling-maps {
3348 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3356 vpu0-thermal {
3357 polling-delay = <1000>;
3358 polling-delay-passive = <250>;
3359 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
3362 vpu0_alert: trip-alert {
3368 vpu0_crit: trip-crit {
3376 vpu1-thermal {
3377 polling-delay = <1000>;
3378 polling-delay-passive = <250>;
3379 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
3382 vpu1_alert: trip-alert {
3388 vpu1_crit: trip-crit {
3396 gpu-thermal {
3397 polling-delay = <1000>;
3398 polling-delay-passive = <250>;
3399 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
3402 gpu0_alert: trip-alert {
3408 gpu0_crit: trip-crit {
3416 gpu1-thermal {
3417 polling-delay = <1000>;
3418 polling-delay-passive = <250>;
3419 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
3422 gpu1_alert: trip-alert {
3428 gpu1_crit: trip-crit {
3436 vdec-thermal {
3437 polling-delay = <1000>;
3438 polling-delay-passive = <250>;
3439 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
3442 vdec_alert: trip-alert {
3448 vdec_crit: trip-crit {
3456 img-thermal {
3457 polling-delay = <1000>;
3458 polling-delay-passive = <250>;
3459 thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
3462 img_alert: trip-alert {
3468 img_crit: trip-crit {
3476 infra-thermal {
3477 polling-delay = <1000>;
3478 polling-delay-passive = <250>;
3479 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
3482 infra_alert: trip-alert {
3488 infra_crit: trip-crit {
3496 cam0-thermal {
3497 polling-delay = <1000>;
3498 polling-delay-passive = <250>;
3499 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
3502 cam0_alert: trip-alert {
3508 cam0_crit: trip-crit {
3516 cam1-thermal {
3517 polling-delay = <1000>;
3518 polling-delay-passive = <250>;
3519 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
3522 cam1_alert: trip-alert {
3528 cam1_crit: trip-crit {