Lines Matching +full:1 +full:a040000
50 #address-cells = <1>;
134 performance-domains = <&performance 1>;
153 performance-domains = <&performance 1>;
172 performance-domains = <&performance 1>;
191 performance-domains = <&performance 1>;
335 clock-mult = <1>;
356 #performance-domain-cells = <1>;
465 #redistributor-regions = <1>;
477 ppi_cluster1: interrupt-partition-1 {
486 #clock-cells = <1>;
492 #clock-cells = <1>;
493 #reset-cells = <1>;
499 #clock-cells = <1>;
530 #address-cells = <1>;
532 #power-domain-cells = <1>;
537 #address-cells = <1>;
539 #power-domain-cells = <1>;
547 #address-cells = <1>;
549 #power-domain-cells = <1>;
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
616 #address-cells = <1>;
618 #power-domain-cells = <1>;
645 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
649 #address-cells = <1>;
651 #power-domain-cells = <1>;
659 "vppsys1-1";
670 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
707 "vdosys1-1", "vdosys1-2";
709 #address-cells = <1>;
711 #power-domain-cells = <1>;
737 clock-names = "img-0", "img-1";
739 #address-cells = <1>;
741 #power-domain-cells = <1>;
753 clock-names = "ipe", "ipe-0", "ipe-1";
766 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
769 #address-cells = <1>;
771 #power-domain-cells = <1>;
833 #address-cells = <1>;
836 #power-domain-cells = <1>;
857 #reset-cells = <1>;
863 #clock-cells = <1>;
909 #iommu-cells = <1>;
941 #clock-cells = <1>;
1096 #io-channel-cells = <1>;
1103 #clock-cells = <1>;
1109 #address-cells = <1>;
1127 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1128 #thermal-sensor-cells = <1>;
1157 #address-cells = <1>;
1171 #address-cells = <1>;
1185 #address-cells = <1>;
1199 #address-cells = <1>;
1213 #address-cells = <1>;
1281 #address-cells = <1>;
1413 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1414 #thermal-sensor-cells = <1>;
1526 #interrupt-cells = <1>;
1528 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1529 <0 0 0 2 &pcie_intc0 1>,
1537 #interrupt-cells = <1>;
1575 #interrupt-cells = <1>;
1577 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1578 <0 0 0 2 &pcie_intc1 1>,
1586 #interrupt-cells = <1>;
1599 #address-cells = <1>;
1607 #address-cells = <1>;
1608 #size-cells = <1>;
1609 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1621 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1633 u2_intr_p0: usb2-intr-p0@188,1 {
1641 u2_intr_p2: usb2-intr-p2@189,1 {
1649 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1657 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1665 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1677 dp_calibration: dp-data@1ac {
1680 lvts_efuse_data1: lvts1-calib@1bc {
1683 lvts_efuse_data2: lvts2-calib@1d0 {
1690 #address-cells = <1>;
1691 #size-cells = <1>;
1699 #phy-cells = <1>;
1705 #address-cells = <1>;
1706 #size-cells = <1>;
1714 #phy-cells = <1>;
1724 clock-div = <1>;
1728 #address-cells = <1>;
1739 clock-div = <1>;
1743 #address-cells = <1>;
1754 clock-div = <1>;
1758 #address-cells = <1>;
1766 #clock-cells = <1>;
1775 clock-div = <1>;
1779 #address-cells = <1>;
1790 clock-div = <1>;
1794 #address-cells = <1>;
1805 clock-div = <1>;
1809 #address-cells = <1>;
1820 clock-div = <1>;
1824 #address-cells = <1>;
1835 clock-div = <1>;
1839 #address-cells = <1>;
1847 #clock-cells = <1>;
1852 #address-cells = <1>;
1853 #size-cells = <1>;
1863 #phy-cells = <1>;
1875 #phy-cells = <1>;
1881 #address-cells = <1>;
1882 #size-cells = <1>;
1891 #phy-cells = <1>;
1903 #phy-cells = <1>;
1956 #clock-cells = <1>;
1962 #clock-cells = <1>;
2029 #iommu-cells = <1>;
2036 #clock-cells = <1>;
2042 #clock-cells = <1>;
2048 #clock-cells = <1>;
2077 #clock-cells = <1>;
2117 #clock-cells = <1>;
2157 #clock-cells = <1>;
2174 #clock-cells = <1>;
2180 #clock-cells = <1>;
2197 #clock-cells = <1>;
2214 #clock-cells = <1>;
2309 #clock-cells = <1>;
2315 #clock-cells = <1>;
2321 #clock-cells = <1>;
2327 #clock-cells = <1>;
2333 #clock-cells = <1>;
2363 #clock-cells = <1>;
2472 #clock-cells = <1>;
2489 #clock-cells = <1>;
2506 #clock-cells = <1>;
2512 #clock-cells = <1>;
2515 vencsys: clock-controller@1a000000 {
2518 #clock-cells = <1>;
2521 larb19: larb@1a010000 {
2532 venc: video-codec@1a020000 {
2568 jpgdec@1a040000 {
2583 jpgdec@1a050000 {
2598 jpgdec@1b040000 {
2614 vencsys_core1: clock-controller@1b000000 {
2617 #clock-cells = <1>;
2620 vdosys0: syscon@1c01a000 {
2624 #clock-cells = <1>;
2640 jpgenc@1a030000 {
2653 jpgenc@1b030000 {
2667 larb20: larb@1b010000 {
2679 ovl0: ovl@1c000000 {
2689 rdma0: rdma@1c002000 {
2699 color0: color@1c003000 {
2708 ccorr0: ccorr@1c004000 {
2717 aal0: aal@1c005000 {
2726 gamma0: gamma@1c006000 {
2735 dither0: dither@1c007000 {
2744 dsc0: dsc@1c009000 {
2753 merge0: merge@1c014000 {
2762 dp_intf0: dp-intf@1c015000 {
2773 mutex: mutex@1c016000 {
2783 larb0: larb@1c018000 {
2795 larb1: larb@1c019000 {
2798 mediatek,larb-id = <1>;
2807 vdosys1: syscon@1c100000 {
2810 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
2812 #clock-cells = <1>;
2813 #reset-cells = <1>;
2816 smi_common_vdo: smi@1c01b000 {
2828 iommu_vdo: iommu@1c01f000 {
2836 #iommu-cells = <1>;
2842 mutex1: mutex@1c101000 {
2852 larb2: larb@1c102000 {
2864 larb3: larb@1c103000 {
2876 vdo1_rdma0: dma-controller@1c104000 {
2884 #dma-cells = <1>;
2887 vdo1_rdma1: dma-controller@1c105000 {
2895 #dma-cells = <1>;
2898 vdo1_rdma2: dma-controller@1c106000 {
2906 #dma-cells = <1>;
2909 vdo1_rdma3: dma-controller@1c107000 {
2917 #dma-cells = <1>;
2920 vdo1_rdma4: dma-controller@1c108000 {
2928 #dma-cells = <1>;
2931 vdo1_rdma5: dma-controller@1c109000 {
2939 #dma-cells = <1>;
2942 vdo1_rdma6: dma-controller@1c10a000 {
2950 #dma-cells = <1>;
2953 vdo1_rdma7: dma-controller@1c10b000 {
2961 #dma-cells = <1>;
2964 merge1: vpp-merge@1c10c000 {
2977 merge2: vpp-merge@1c10d000 {
2990 merge3: vpp-merge@1c10e000 {
3003 merge4: vpp-merge@1c10f000 {
3016 merge5: vpp-merge@1c110000 {
3029 dp_intf1: dp-intf@1c113000 {
3041 ethdr0: hdr-engine@1c114000 {
3089 edp_tx: edp-tx@1c500000 {
3100 dp_tx: dp-tx@1c600000 {