Lines Matching full:iommu0
1457 iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
1458 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
1469 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
1470 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
1480 iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
1569 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
1570 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
1581 iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
1597 iommu0: m4u@1401d000 { label
1650 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
1659 iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
1660 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
1661 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
1662 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
1663 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
1664 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
1665 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
1666 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
1682 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
1683 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
1684 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
1685 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
1686 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
1687 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
1688 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
1689 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
1690 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
1691 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
1692 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
1759 iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
1760 <&iommu0 M4U_PORT_L7_VENC_REC>,
1761 <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
1762 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
1763 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
1764 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
1765 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
1766 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
1767 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
1768 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
1769 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;