Lines Matching +full:cpu +full:- +full:power +full:- +full:controller
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
16 #include <dt-bindings/reset/mt8192-resets.h>
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
26 ovl-2l0 = &ovl_2l0;
27 ovl-2l2 = &ovl_2l2;
32 clk13m: fixed-factor-clock-13m {
33 compatible = "fixed-factor-clock";
34 #clock-cells = <0>;
36 clock-div = <2>;
37 clock-mult = <1>;
38 clock-output-names = "clk13m";
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <26000000>;
45 clock-output-names = "clk26m";
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <32768>;
52 clock-output-names = "clk32k";
56 #address-cells = <1>;
57 #size-cells = <0>;
59 cpu0: cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a55";
63 enable-method = "psci";
64 clock-frequency = <1701000000>;
65 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
66 i-cache-size = <32768>;
67 i-cache-line-size = <64>;
68 i-cache-sets = <128>;
69 d-cache-size = <32768>;
70 d-cache-line-size = <64>;
71 d-cache-sets = <128>;
72 next-level-cache = <&l2_0>;
73 performance-domains = <&performance 0>;
74 capacity-dmips-mhz = <427>;
77 cpu1: cpu@100 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a55";
81 enable-method = "psci";
82 clock-frequency = <1701000000>;
83 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
84 i-cache-size = <32768>;
85 i-cache-line-size = <64>;
86 i-cache-sets = <128>;
87 d-cache-size = <32768>;
88 d-cache-line-size = <64>;
89 d-cache-sets = <128>;
90 next-level-cache = <&l2_0>;
91 performance-domains = <&performance 0>;
92 capacity-dmips-mhz = <427>;
95 cpu2: cpu@200 {
96 device_type = "cpu";
97 compatible = "arm,cortex-a55";
99 enable-method = "psci";
100 clock-frequency = <1701000000>;
101 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
102 i-cache-size = <32768>;
103 i-cache-line-size = <64>;
104 i-cache-sets = <128>;
105 d-cache-size = <32768>;
106 d-cache-line-size = <64>;
107 d-cache-sets = <128>;
108 next-level-cache = <&l2_0>;
109 performance-domains = <&performance 0>;
110 capacity-dmips-mhz = <427>;
113 cpu3: cpu@300 {
114 device_type = "cpu";
115 compatible = "arm,cortex-a55";
117 enable-method = "psci";
118 clock-frequency = <1701000000>;
119 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
120 i-cache-size = <32768>;
121 i-cache-line-size = <64>;
122 i-cache-sets = <128>;
123 d-cache-size = <32768>;
124 d-cache-line-size = <64>;
125 d-cache-sets = <128>;
126 next-level-cache = <&l2_0>;
127 performance-domains = <&performance 0>;
128 capacity-dmips-mhz = <427>;
131 cpu4: cpu@400 {
132 device_type = "cpu";
133 compatible = "arm,cortex-a76";
135 enable-method = "psci";
136 clock-frequency = <2171000000>;
137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
138 i-cache-size = <65536>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <256>;
141 d-cache-size = <65536>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <256>;
144 next-level-cache = <&l2_1>;
145 performance-domains = <&performance 1>;
146 capacity-dmips-mhz = <1024>;
149 cpu5: cpu@500 {
150 device_type = "cpu";
151 compatible = "arm,cortex-a76";
153 enable-method = "psci";
154 clock-frequency = <2171000000>;
155 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
156 i-cache-size = <65536>;
157 i-cache-line-size = <64>;
158 i-cache-sets = <256>;
159 d-cache-size = <65536>;
160 d-cache-line-size = <64>;
161 d-cache-sets = <256>;
162 next-level-cache = <&l2_1>;
163 performance-domains = <&performance 1>;
164 capacity-dmips-mhz = <1024>;
167 cpu6: cpu@600 {
168 device_type = "cpu";
169 compatible = "arm,cortex-a76";
171 enable-method = "psci";
172 clock-frequency = <2171000000>;
173 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
174 i-cache-size = <65536>;
175 i-cache-line-size = <64>;
176 i-cache-sets = <256>;
177 d-cache-size = <65536>;
178 d-cache-line-size = <64>;
179 d-cache-sets = <256>;
180 next-level-cache = <&l2_1>;
181 performance-domains = <&performance 1>;
182 capacity-dmips-mhz = <1024>;
185 cpu7: cpu@700 {
186 device_type = "cpu";
187 compatible = "arm,cortex-a76";
189 enable-method = "psci";
190 clock-frequency = <2171000000>;
191 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
192 i-cache-size = <65536>;
193 i-cache-line-size = <64>;
194 i-cache-sets = <256>;
195 d-cache-size = <65536>;
196 d-cache-line-size = <64>;
197 d-cache-sets = <256>;
198 next-level-cache = <&l2_1>;
199 performance-domains = <&performance 1>;
200 capacity-dmips-mhz = <1024>;
203 cpu-map {
206 cpu = <&cpu0>;
209 cpu = <&cpu1>;
212 cpu = <&cpu2>;
215 cpu = <&cpu3>;
218 cpu = <&cpu4>;
221 cpu = <&cpu5>;
224 cpu = <&cpu6>;
227 cpu = <&cpu7>;
232 l2_0: l2-cache0 {
234 cache-level = <2>;
235 cache-size = <131072>;
236 cache-line-size = <64>;
237 cache-sets = <512>;
238 next-level-cache = <&l3_0>;
239 cache-unified;
242 l2_1: l2-cache1 {
244 cache-level = <2>;
245 cache-size = <262144>;
246 cache-line-size = <64>;
247 cache-sets = <512>;
248 next-level-cache = <&l3_0>;
249 cache-unified;
252 l3_0: l3-cache {
254 cache-level = <3>;
255 cache-size = <2097152>;
256 cache-line-size = <64>;
257 cache-sets = <2048>;
258 cache-unified;
261 idle-states {
262 entry-method = "psci";
263 cpu_ret_l: cpu-retention-l {
264 compatible = "arm,idle-state";
265 arm,psci-suspend-param = <0x00010001>;
266 local-timer-stop;
267 entry-latency-us = <55>;
268 exit-latency-us = <140>;
269 min-residency-us = <780>;
271 cpu_ret_b: cpu-retention-b {
272 compatible = "arm,idle-state";
273 arm,psci-suspend-param = <0x00010001>;
274 local-timer-stop;
275 entry-latency-us = <35>;
276 exit-latency-us = <145>;
277 min-residency-us = <720>;
279 cpu_off_l: cpu-off-l {
280 compatible = "arm,idle-state";
281 arm,psci-suspend-param = <0x01010002>;
282 local-timer-stop;
283 entry-latency-us = <60>;
284 exit-latency-us = <155>;
285 min-residency-us = <860>;
287 cpu_off_b: cpu-off-b {
288 compatible = "arm,idle-state";
289 arm,psci-suspend-param = <0x01010002>;
290 local-timer-stop;
291 entry-latency-us = <40>;
292 exit-latency-us = <155>;
293 min-residency-us = <780>;
298 pmu-a55 {
299 compatible = "arm,cortex-a55-pmu";
300 interrupt-parent = <&gic>;
304 pmu-a76 {
305 compatible = "arm,cortex-a76-pmu";
306 interrupt-parent = <&gic>;
311 compatible = "arm,psci-1.0";
316 compatible = "arm,armv8-timer";
317 interrupt-parent = <&gic>;
322 clock-frequency = <13000000>;
325 gpu_opp_table: opp-table-0 {
326 compatible = "operating-points-v2";
327 opp-shared;
329 opp-358000000 {
330 opp-hz = /bits/ 64 <358000000>;
331 opp-microvolt = <606250>;
334 opp-399000000 {
335 opp-hz = /bits/ 64 <399000000>;
336 opp-microvolt = <618750>;
339 opp-440000000 {
340 opp-hz = /bits/ 64 <440000000>;
341 opp-microvolt = <631250>;
344 opp-482000000 {
345 opp-hz = /bits/ 64 <482000000>;
346 opp-microvolt = <643750>;
349 opp-523000000 {
350 opp-hz = /bits/ 64 <523000000>;
351 opp-microvolt = <656250>;
354 opp-564000000 {
355 opp-hz = /bits/ 64 <564000000>;
356 opp-microvolt = <668750>;
359 opp-605000000 {
360 opp-hz = /bits/ 64 <605000000>;
361 opp-microvolt = <681250>;
364 opp-647000000 {
365 opp-hz = /bits/ 64 <647000000>;
366 opp-microvolt = <693750>;
369 opp-688000000 {
370 opp-hz = /bits/ 64 <688000000>;
371 opp-microvolt = <706250>;
374 opp-724000000 {
375 opp-hz = /bits/ 64 <724000000>;
376 opp-microvolt = <725000>;
379 opp-748000000 {
380 opp-hz = /bits/ 64 <748000000>;
381 opp-microvolt = <737500>;
384 opp-772000000 {
385 opp-hz = /bits/ 64 <772000000>;
386 opp-microvolt = <750000>;
389 opp-795000000 {
390 opp-hz = /bits/ 64 <795000000>;
391 opp-microvolt = <762500>;
394 opp-819000000 {
395 opp-hz = /bits/ 64 <819000000>;
396 opp-microvolt = <775000>;
399 opp-843000000 {
400 opp-hz = /bits/ 64 <843000000>;
401 opp-microvolt = <787500>;
404 opp-866000000 {
405 opp-hz = /bits/ 64 <866000000>;
406 opp-microvolt = <800000>;
411 #address-cells = <2>;
412 #size-cells = <2>;
413 compatible = "simple-bus";
414 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
417 performance: performance-controller@11bc10 {
418 compatible = "mediatek,cpufreq-hw";
420 #performance-domain-cells = <1>;
423 gic: interrupt-controller@c000000 {
424 compatible = "arm,gic-v3";
425 #interrupt-cells = <4>;
426 #redistributor-regions = <1>;
427 interrupt-parent = <&gic>;
428 interrupt-controller;
433 ppi-partitions {
434 ppi_cluster0: interrupt-partition-0 {
437 ppi_cluster1: interrupt-partition-1 {
444 compatible = "mediatek,mt8192-topckgen", "syscon";
446 #clock-cells = <1>;
450 compatible = "mediatek,mt8192-infracfg", "syscon";
452 #clock-cells = <1>;
453 #reset-cells = <1>;
457 compatible = "mediatek,mt8192-pericfg", "syscon";
459 #clock-cells = <1>;
463 compatible = "mediatek,mt8192-pinctrl";
475 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
479 gpio-controller;
480 #gpio-cells = <2>;
481 gpio-ranges = <&pio 0 0 220>;
482 interrupt-controller;
484 #interrupt-cells = <2>;
488 compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd";
491 /* System Power Manager */
492 spm: power-controller {
493 compatible = "mediatek,mt8192-power-controller";
494 #address-cells = <1>;
495 #size-cells = <0>;
496 #power-domain-cells = <1>;
498 /* power domain of the SoC */
499 power-domain@MT8192_POWER_DOMAIN_AUDIO {
504 clock-names = "audio", "audio1", "audio2";
506 #power-domain-cells = <0>;
509 power-domain@MT8192_POWER_DOMAIN_CONN {
512 clock-names = "conn";
514 #power-domain-cells = <0>;
517 mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 {
521 clock-names = "mfg", "alt";
522 #address-cells = <1>;
523 #size-cells = <0>;
524 #power-domain-cells = <1>;
526 mfg1: power-domain@MT8192_POWER_DOMAIN_MFG1 {
529 #address-cells = <1>;
530 #size-cells = <0>;
531 #power-domain-cells = <1>;
533 power-domain@MT8192_POWER_DOMAIN_MFG2 {
535 #power-domain-cells = <0>;
538 power-domain@MT8192_POWER_DOMAIN_MFG3 {
540 #power-domain-cells = <0>;
543 power-domain@MT8192_POWER_DOMAIN_MFG4 {
545 #power-domain-cells = <0>;
548 power-domain@MT8192_POWER_DOMAIN_MFG5 {
550 #power-domain-cells = <0>;
553 power-domain@MT8192_POWER_DOMAIN_MFG6 {
555 #power-domain-cells = <0>;
560 power-domain@MT8192_POWER_DOMAIN_DISP {
567 clock-names = "disp", "disp-0", "disp-1", "disp-2",
568 "disp-3";
570 #address-cells = <1>;
571 #size-cells = <0>;
572 #power-domain-cells = <1>;
574 power-domain@MT8192_POWER_DOMAIN_IPE {
581 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
582 "ipe-3";
584 #power-domain-cells = <0>;
587 power-domain@MT8192_POWER_DOMAIN_ISP {
592 clock-names = "isp", "isp-0", "isp-1";
594 #power-domain-cells = <0>;
597 power-domain@MT8192_POWER_DOMAIN_ISP2 {
602 clock-names = "isp2", "isp2-0", "isp2-1";
604 #power-domain-cells = <0>;
607 power-domain@MT8192_POWER_DOMAIN_MDP {
611 clock-names = "mdp", "mdp-0";
613 #power-domain-cells = <0>;
616 power-domain@MT8192_POWER_DOMAIN_VENC {
620 clock-names = "venc", "venc-0";
622 #power-domain-cells = <0>;
625 power-domain@MT8192_POWER_DOMAIN_VDEC {
631 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
633 #address-cells = <1>;
634 #size-cells = <0>;
635 #power-domain-cells = <1>;
637 power-domain@MT8192_POWER_DOMAIN_VDEC2 {
642 clock-names = "vdec2-0", "vdec2-1",
643 "vdec2-2";
644 #power-domain-cells = <0>;
648 power-domain@MT8192_POWER_DOMAIN_CAM {
655 clock-names = "cam", "cam-0", "cam-1", "cam-2",
656 "cam-3";
658 #address-cells = <1>;
659 #size-cells = <0>;
660 #power-domain-cells = <1>;
662 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {
665 clock-names = "cam_rawa-0";
666 #power-domain-cells = <0>;
669 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {
672 clock-names = "cam_rawb-0";
673 #power-domain-cells = <0>;
676 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {
679 clock-names = "cam_rawc-0";
680 #power-domain-cells = <0>;
688 compatible = "mediatek,mt8192-wdt";
690 #reset-cells = <1>;
694 compatible = "mediatek,mt8192-apmixedsys", "syscon";
696 #clock-cells = <1>;
700 compatible = "mediatek,mt8192-timer",
701 "mediatek,mt6765-timer";
708 compatible = "mediatek,mt6873-pwrap";
710 reg-names = "pwrap";
714 clock-names = "spi", "wrap";
715 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
716 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
720 compatible = "mediatek,mt6873-spmi";
723 reg-names = "pmif", "spmimst";
727 clock-names = "pmif_sys_ck",
730 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
731 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
735 compatible = "mediatek,mt8192-gce";
738 #mbox-cells = <2>;
740 clock-names = "gce";
743 scp_adsp: clock-controller@10720000 {
744 compatible = "mediatek,mt8192-scp_adsp";
746 #clock-cells = <1>;
747 /* power domain dependency not upstreamed */
752 compatible = "mediatek,mt8192-uart",
753 "mediatek,mt6577-uart";
757 clock-names = "baud", "bus";
762 compatible = "mediatek,mt8192-uart",
763 "mediatek,mt6577-uart";
767 clock-names = "baud", "bus";
771 imp_iic_wrap_c: clock-controller@11007000 {
772 compatible = "mediatek,mt8192-imp_iic_wrap_c";
774 #clock-cells = <1>;
778 compatible = "mediatek,mt8192-spi",
779 "mediatek,mt6765-spi";
780 #address-cells = <1>;
781 #size-cells = <0>;
787 clock-names = "parent-clk", "sel-clk", "spi-clk";
792 compatible = "mediatek,mt8183-disp-pwm";
795 #pwm-cells = <2>;
798 clock-names = "main", "mm";
803 compatible = "mediatek,mt8192-spi",
804 "mediatek,mt6765-spi";
805 #address-cells = <1>;
806 #size-cells = <0>;
812 clock-names = "parent-clk", "sel-clk", "spi-clk";
817 compatible = "mediatek,mt8192-spi",
818 "mediatek,mt6765-spi";
819 #address-cells = <1>;
820 #size-cells = <0>;
826 clock-names = "parent-clk", "sel-clk", "spi-clk";
831 compatible = "mediatek,mt8192-spi",
832 "mediatek,mt6765-spi";
833 #address-cells = <1>;
834 #size-cells = <0>;
840 clock-names = "parent-clk", "sel-clk", "spi-clk";
845 compatible = "mediatek,mt8192-spi",
846 "mediatek,mt6765-spi";
847 #address-cells = <1>;
848 #size-cells = <0>;
854 clock-names = "parent-clk", "sel-clk", "spi-clk";
859 compatible = "mediatek,mt8192-spi",
860 "mediatek,mt6765-spi";
861 #address-cells = <1>;
862 #size-cells = <0>;
868 clock-names = "parent-clk", "sel-clk", "spi-clk";
873 compatible = "mediatek,mt8192-spi",
874 "mediatek,mt6765-spi";
875 #address-cells = <1>;
876 #size-cells = <0>;
882 clock-names = "parent-clk", "sel-clk", "spi-clk";
887 compatible = "mediatek,mt8192-spi",
888 "mediatek,mt6765-spi";
889 #address-cells = <1>;
890 #size-cells = <0>;
896 clock-names = "parent-clk", "sel-clk", "spi-clk";
901 compatible = "mediatek,mt8192-scp";
905 reg-names = "sram", "cfg", "l1tcm";
908 clock-names = "main";
913 compatible = "mediatek,mt8192-xhci",
914 "mediatek,mtk-xhci";
917 reg-names = "mac", "ippc";
918 interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
919 interrupt-names = "host";
922 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
924 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
931 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
933 wakeup-source;
934 mediatek,syscon-wakeup = <&pericfg 0x420 102>;
939 compatible = "mediatek,mt8192-audsys", "syscon";
941 #clock-cells = <1>;
943 afe: mt8192-afe-pcm {
944 compatible = "mediatek,mt8192-audio";
947 reset-names = "audiosys";
951 power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
1008 clock-names = "aud_afe_clk",
1068 compatible = "mediatek,mt8192-pcie";
1071 reg-names = "pcie-mac";
1072 #address-cells = <3>;
1073 #size-cells = <2>;
1080 clock-names = "pl_250m", "tl_26m", "tl_96m",
1082 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
1083 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
1085 bus-range = <0x00 0xff>;
1088 #interrupt-cells = <1>;
1089 interrupt-map-mask = <0 0 0 7>;
1090 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1095 pcie_intc0: interrupt-controller {
1096 interrupt-controller;
1097 #address-cells = <0>;
1098 #interrupt-cells = <1>;
1103 compatible = "mediatek,mt8192-nor";
1109 clock-names = "spi", "sf", "axi";
1110 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
1111 assigned-clock-parents = <&clk26m>;
1112 #address-cells = <1>;
1113 #size-cells = <0>;
1118 compatible = "mediatek,mt8192-efuse", "mediatek,efuse";
1120 #address-cells = <1>;
1121 #size-cells = <1>;
1133 compatible = "mediatek,mt8192-i2c";
1139 clock-names = "main", "dma";
1140 clock-div = <1>;
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1146 imp_iic_wrap_e: clock-controller@11cb1000 {
1147 compatible = "mediatek,mt8192-imp_iic_wrap_e";
1149 #clock-cells = <1>;
1153 compatible = "mediatek,mt8192-i2c";
1159 clock-names = "main", "dma";
1160 clock-div = <1>;
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1167 compatible = "mediatek,mt8192-i2c";
1173 clock-names = "main", "dma";
1174 clock-div = <1>;
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1181 compatible = "mediatek,mt8192-i2c";
1187 clock-names = "main", "dma";
1188 clock-div = <1>;
1189 #address-cells = <1>;
1190 #size-cells = <0>;
1194 imp_iic_wrap_s: clock-controller@11d03000 {
1195 compatible = "mediatek,mt8192-imp_iic_wrap_s";
1197 #clock-cells = <1>;
1201 compatible = "mediatek,mt8192-i2c";
1207 clock-names = "main", "dma";
1208 clock-div = <1>;
1209 #address-cells = <1>;
1210 #size-cells = <0>;
1215 compatible = "mediatek,mt8192-i2c";
1221 clock-names = "main", "dma";
1222 clock-div = <1>;
1223 #address-cells = <1>;
1224 #size-cells = <0>;
1229 compatible = "mediatek,mt8192-i2c";
1235 clock-names = "main", "dma";
1236 clock-div = <1>;
1237 #address-cells = <1>;
1238 #size-cells = <0>;
1242 imp_iic_wrap_ws: clock-controller@11d23000 {
1243 compatible = "mediatek,mt8192-imp_iic_wrap_ws";
1245 #clock-cells = <1>;
1249 compatible = "mediatek,mt8192-i2c";
1255 clock-names = "main", "dma";
1256 clock-div = <1>;
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1262 imp_iic_wrap_w: clock-controller@11e01000 {
1263 compatible = "mediatek,mt8192-imp_iic_wrap_w";
1265 #clock-cells = <1>;
1268 u3phy0: t-phy@11e40000 {
1269 compatible = "mediatek,mt8192-tphy",
1270 "mediatek,generic-tphy-v2";
1271 #address-cells = <1>;
1272 #size-cells = <1>;
1275 u2port0: usb-phy@0 {
1278 clock-names = "ref";
1279 #phy-cells = <1>;
1282 u3port0: usb-phy@700 {
1285 clock-names = "ref";
1286 #phy-cells = <1>;
1290 mipi_tx0: dsi-phy@11e50000 {
1291 compatible = "mediatek,mt8183-mipi-tx";
1294 #clock-cells = <0>;
1295 #phy-cells = <0>;
1296 clock-output-names = "mipi_tx0_pll";
1301 compatible = "mediatek,mt8192-i2c";
1307 clock-names = "main", "dma";
1308 clock-div = <1>;
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1315 compatible = "mediatek,mt8192-i2c";
1321 clock-names = "main", "dma";
1322 clock-div = <1>;
1323 #address-cells = <1>;
1324 #size-cells = <0>;
1328 imp_iic_wrap_n: clock-controller@11f02000 {
1329 compatible = "mediatek,mt8192-imp_iic_wrap_n";
1331 #clock-cells = <1>;
1334 msdc_top: clock-controller@11f10000 {
1335 compatible = "mediatek,mt8192-msdc_top";
1337 #clock-cells = <1>;
1341 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1351 clock-names = "source", "hclk", "source_cg", "sys_cg",
1357 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1367 clock-names = "source", "hclk", "source_cg", "sys_cg",
1373 compatible = "mediatek,mt8192-mali", "arm,mali-valhall-jm";
1378 interrupt-names = "job", "mmu", "gpu";
1382 power-domains = <&spm MT8192_POWER_DOMAIN_MFG2>,
1387 power-domain-names = "core0", "core1", "core2", "core3", "core4";
1389 operating-points-v2 = <&gpu_opp_table>;
1394 mfgcfg: clock-controller@13fbf000 {
1395 compatible = "mediatek,mt8192-mfgcfg";
1397 #clock-cells = <1>;
1401 compatible = "mediatek,mt8192-mmsys", "syscon";
1403 #clock-cells = <1>;
1404 #reset-cells = <1>;
1407 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1411 compatible = "mediatek,mt8192-disp-mutex";
1415 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1416 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1418 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1422 compatible = "mediatek,mt8192-smi-common";
1428 clock-names = "apb", "smi", "gals0", "gals1";
1429 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1433 compatible = "mediatek,mt8192-smi-larb";
1435 mediatek,larb-id = <0>;
1438 clock-names = "apb", "smi";
1439 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1443 compatible = "mediatek,mt8192-smi-larb";
1445 mediatek,larb-id = <1>;
1448 clock-names = "apb", "smi";
1449 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1453 compatible = "mediatek,mt8192-disp-ovl";
1459 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1460 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1464 compatible = "mediatek,mt8192-disp-ovl-2l";
1467 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1471 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1475 compatible = "mediatek,mt8192-disp-rdma",
1476 "mediatek,mt8183-disp-rdma";
1481 mediatek,rdma-fifo-size = <5120>;
1482 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1483 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1487 compatible = "mediatek,mt8192-disp-color",
1488 "mediatek,mt8173-disp-color";
1491 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1493 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1497 compatible = "mediatek,mt8192-disp-ccorr";
1500 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1502 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1506 compatible = "mediatek,mt8192-disp-aal",
1507 "mediatek,mt8183-disp-aal";
1510 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1512 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1516 compatible = "mediatek,mt8192-disp-gamma",
1517 "mediatek,mt8183-disp-gamma";
1520 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1522 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1526 compatible = "mediatek,mt8192-disp-postmask";
1529 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1531 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1535 compatible = "mediatek,mt8192-disp-dither",
1536 "mediatek,mt8183-disp-dither";
1539 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1541 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1545 compatible = "mediatek,mt8183-dsi";
1551 clock-names = "engine", "digital", "hs";
1553 phy-names = "dphy";
1554 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1564 compatible = "mediatek,mt8192-disp-ovl-2l";
1567 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1571 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1575 compatible = "mediatek,mt8192-disp-rdma",
1576 "mediatek,mt8183-disp-rdma";
1579 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1582 mediatek,rdma-fifo-size = <2048>;
1583 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1587 compatible = "mediatek,mt8192-dpi";
1593 clock-names = "pixel", "engine", "pll";
1598 compatible = "mediatek,mt8192-m4u";
1607 clock-names = "bclk";
1608 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1609 #iommu-cells = <1>;
1612 imgsys: clock-controller@15020000 {
1613 compatible = "mediatek,mt8192-imgsys";
1615 #clock-cells = <1>;
1619 compatible = "mediatek,mt8192-smi-larb";
1621 mediatek,larb-id = <9>;
1625 clock-names = "apb", "smi";
1626 power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
1629 imgsys2: clock-controller@15820000 {
1630 compatible = "mediatek,mt8192-imgsys2";
1632 #clock-cells = <1>;
1636 compatible = "mediatek,mt8192-smi-larb";
1638 mediatek,larb-id = <11>;
1642 clock-names = "apb", "smi";
1643 power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
1646 vcodec_dec: video-codec@16000000 {
1647 compatible = "mediatek,mt8192-vcodec-dec";
1651 #address-cells = <2>;
1652 #size-cells = <2>;
1655 video-codec@10000 {
1656 compatible = "mediatek,mtk-vcodec-lat";
1672 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
1673 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
1674 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
1675 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
1678 video-codec@25000 {
1679 compatible = "mediatek,mtk-vcodec-core";
1698 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
1699 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
1700 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
1701 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
1706 compatible = "mediatek,mt8192-smi-larb";
1708 mediatek,larb-id = <5>;
1712 clock-names = "apb", "smi";
1713 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
1716 vdecsys_soc: clock-controller@1600f000 {
1717 compatible = "mediatek,mt8192-vdecsys_soc";
1719 #clock-cells = <1>;
1723 compatible = "mediatek,mt8192-smi-larb";
1725 mediatek,larb-id = <4>;
1729 clock-names = "apb", "smi";
1730 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
1733 vdecsys: clock-controller@1602f000 {
1734 compatible = "mediatek,mt8192-vdecsys";
1736 #clock-cells = <1>;
1739 vencsys: clock-controller@17000000 {
1740 compatible = "mediatek,mt8192-vencsys";
1742 #clock-cells = <1>;
1746 compatible = "mediatek,mt8192-smi-larb";
1748 mediatek,larb-id = <7>;
1752 clock-names = "apb", "smi";
1753 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1757 compatible = "mediatek,mt8192-vcodec-enc";
1772 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1774 clock-names = "venc_sel";
1775 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1776 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
1779 camsys: clock-controller@1a000000 {
1780 compatible = "mediatek,mt8192-camsys";
1782 #clock-cells = <1>;
1786 compatible = "mediatek,mt8192-smi-larb";
1788 mediatek,larb-id = <13>;
1792 clock-names = "apb", "smi";
1793 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1797 compatible = "mediatek,mt8192-smi-larb";
1799 mediatek,larb-id = <14>;
1803 clock-names = "apb", "smi";
1804 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1808 compatible = "mediatek,mt8192-smi-larb";
1810 mediatek,larb-id = <16>;
1814 clock-names = "apb", "smi";
1815 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
1819 compatible = "mediatek,mt8192-smi-larb";
1821 mediatek,larb-id = <17>;
1825 clock-names = "apb", "smi";
1826 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
1830 compatible = "mediatek,mt8192-smi-larb";
1832 mediatek,larb-id = <18>;
1836 clock-names = "apb", "smi";
1837 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
1840 camsys_rawa: clock-controller@1a04f000 {
1841 compatible = "mediatek,mt8192-camsys_rawa";
1843 #clock-cells = <1>;
1846 camsys_rawb: clock-controller@1a06f000 {
1847 compatible = "mediatek,mt8192-camsys_rawb";
1849 #clock-cells = <1>;
1852 camsys_rawc: clock-controller@1a08f000 {
1853 compatible = "mediatek,mt8192-camsys_rawc";
1855 #clock-cells = <1>;
1858 ipesys: clock-controller@1b000000 {
1859 compatible = "mediatek,mt8192-ipesys";
1861 #clock-cells = <1>;
1865 compatible = "mediatek,mt8192-smi-larb";
1867 mediatek,larb-id = <20>;
1871 clock-names = "apb", "smi";
1872 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1876 compatible = "mediatek,mt8192-smi-larb";
1878 mediatek,larb-id = <19>;
1882 clock-names = "apb", "smi";
1883 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1886 mdpsys: clock-controller@1f000000 {
1887 compatible = "mediatek,mt8192-mdpsys";
1889 #clock-cells = <1>;
1893 compatible = "mediatek,mt8192-smi-larb";
1895 mediatek,larb-id = <2>;
1899 clock-names = "apb", "smi";
1900 power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;