dts/mediatek/mt8192.dtsi

37 		clock-mult = <1>;
56 		#address-cells = <1>;
145 			performance-domains = <&performance 1>;
163 			performance-domains = <&performance 1>;
181 			performance-domains = <&performance 1>;
199 			performance-domains = <&performance 1>;
420 			#performance-domain-cells = <1>;
426 			#redistributor-regions = <1>;
437 				ppi_cluster1: interrupt-partition-1 {
446 			#clock-cells = <1>;
452 			#clock-cells = <1>;
453 			#reset-cells = <1>;
459 			#clock-cells = <1>;
494 				#address-cells = <1>;
496 				#power-domain-cells = <1>;
522 					#address-cells = <1>;
524 					#power-domain-cells = <1>;
529 						#address-cells = <1>;
531 						#power-domain-cells = <1>;
567 					clock-names = "disp", "disp-0", "disp-1", "disp-2",
570 					#address-cells = <1>;
572 					#power-domain-cells = <1>;
581 						clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
592 						clock-names = "isp", "isp-0", "isp-1";
602 						clock-names = "isp2", "isp2-0", "isp2-1";
631 						clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
633 						#address-cells = <1>;
635 						#power-domain-cells = <1>;
642 							clock-names = "vdec2-0", "vdec2-1",
655 						clock-names = "cam", "cam-0", "cam-1", "cam-2",
658 						#address-cells = <1>;
660 						#power-domain-cells = <1>;
690 			#reset-cells = <1>;
696 			#clock-cells = <1>;
746 			#clock-cells = <1>;
774 			#clock-cells = <1>;
780 			#address-cells = <1>;
805 			#address-cells = <1>;
819 			#address-cells = <1>;
833 			#address-cells = <1>;
847 			#address-cells = <1>;
861 			#address-cells = <1>;
875 			#address-cells = <1>;
889 			#address-cells = <1>;
941 			#clock-cells = <1>;
1088 			#interrupt-cells = <1>;
1090 			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1091 					<0 0 0 2 &pcie_intc0 1>,
1098 				#interrupt-cells = <1>;
1112 			#address-cells = <1>;
1120 			#address-cells = <1>;
1121 			#size-cells = <1>;
1123 			lvts_e_data1: data1@1c0 {
1140 			clock-div = <1>;
1141 			#address-cells = <1>;
1149 			#clock-cells = <1>;
1160 			clock-div = <1>;
1161 			#address-cells = <1>;
1174 			clock-div = <1>;
1175 			#address-cells = <1>;
1188 			clock-div = <1>;
1189 			#address-cells = <1>;
1197 			#clock-cells = <1>;
1208 			clock-div = <1>;
1209 			#address-cells = <1>;
1222 			clock-div = <1>;
1223 			#address-cells = <1>;
1236 			clock-div = <1>;
1237 			#address-cells = <1>;
1245 			#clock-cells = <1>;
1256 			clock-div = <1>;
1257 			#address-cells = <1>;
1265 			#clock-cells = <1>;
1268 		u3phy0: t-phy@11e40000 {
1271 			#address-cells = <1>;
1272 			#size-cells = <1>;
1279 				#phy-cells = <1>;
1286 				#phy-cells = <1>;
1308 			clock-div = <1>;
1309 			#address-cells = <1>;
1322 			clock-div = <1>;
1323 			#address-cells = <1>;
1331 			#clock-cells = <1>;
1337 			#clock-cells = <1>;
1397 			#clock-cells = <1>;
1403 			#clock-cells = <1>;
1404 			#reset-cells = <1>;
1406 				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1445 			mediatek,larb-id = <1>;
1609 			#iommu-cells = <1>;
1615 			#clock-cells = <1>;
1632 			#clock-cells = <1>;
1719 			#clock-cells = <1>;
1736 			#clock-cells = <1>;
1742 			#clock-cells = <1>;
1779 		camsys: clock-controller@1a000000 {
1782 			#clock-cells = <1>;
1785 		larb13: larb@1a001000 {
1796 		larb14: larb@1a002000 {
1807 		larb16: larb@1a00f000 {
1818 		larb17: larb@1a010000 {
1829 		larb18: larb@1a011000 {
1840 		camsys_rawa: clock-controller@1a04f000 {
1843 			#clock-cells = <1>;
1846 		camsys_rawb: clock-controller@1a06f000 {
1849 			#clock-cells = <1>;
1852 		camsys_rawc: clock-controller@1a08f000 {
1855 			#clock-cells = <1>;
1858 		ipesys: clock-controller@1b000000 {
1861 			#clock-cells = <1>;
1864 		larb20: larb@1b00f000 {
1875 		larb19: larb@1b10f000 {
1886 		mdpsys: clock-controller@1f000000 {
1889 			#clock-cells = <1>;
1892 		larb2: larb@1f002000 {