Lines Matching +full:required +full:- +full:opps
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/reset/mt8186-resets.h>
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
25 ovl-2l0 = &ovl_2l0;
31 compatible = "mediatek,mt8186-cci";
34 clock-names = "cci", "intermediate";
35 operating-points-v2 = <&cci_opp>;
38 cci_opp: opp-table-cci {
39 compatible = "operating-points-v2";
40 opp-shared;
42 cci_opp_0: opp-500000000 {
43 opp-hz = /bits/ 64 <500000000>;
44 opp-microvolt = <600000>;
47 cci_opp_1: opp-560000000 {
48 opp-hz = /bits/ 64 <560000000>;
49 opp-microvolt = <675000>;
52 cci_opp_2: opp-612000000 {
53 opp-hz = /bits/ 64 <612000000>;
54 opp-microvolt = <693750>;
57 cci_opp_3: opp-682000000 {
58 opp-hz = /bits/ 64 <682000000>;
59 opp-microvolt = <718750>;
62 cci_opp_4: opp-752000000 {
63 opp-hz = /bits/ 64 <752000000>;
64 opp-microvolt = <743750>;
67 cci_opp_5: opp-822000000 {
68 opp-hz = /bits/ 64 <822000000>;
69 opp-microvolt = <768750>;
72 cci_opp_6: opp-875000000 {
73 opp-hz = /bits/ 64 <875000000>;
74 opp-microvolt = <781250>;
77 cci_opp_7: opp-927000000 {
78 opp-hz = /bits/ 64 <927000000>;
79 opp-microvolt = <800000>;
82 cci_opp_8: opp-980000000 {
83 opp-hz = /bits/ 64 <980000000>;
84 opp-microvolt = <818750>;
87 cci_opp_9: opp-1050000000 {
88 opp-hz = /bits/ 64 <1050000000>;
89 opp-microvolt = <843750>;
92 cci_opp_10: opp-1120000000 {
93 opp-hz = /bits/ 64 <1120000000>;
94 opp-microvolt = <862500>;
97 cci_opp_11: opp-1155000000 {
98 opp-hz = /bits/ 64 <1155000000>;
99 opp-microvolt = <887500>;
102 cci_opp_12: opp-1190000000 {
103 opp-hz = /bits/ 64 <1190000000>;
104 opp-microvolt = <906250>;
107 cci_opp_13: opp-1260000000 {
108 opp-hz = /bits/ 64 <1260000000>;
109 opp-microvolt = <950000>;
112 cci_opp_14: opp-1330000000 {
113 opp-hz = /bits/ 64 <1330000000>;
114 opp-microvolt = <993750>;
117 cci_opp_15: opp-1400000000 {
118 opp-hz = /bits/ 64 <1400000000>;
119 opp-microvolt = <1031250>;
123 cluster0_opp: opp-table-cluster0 {
124 compatible = "operating-points-v2";
125 opp-shared;
127 opp-500000000 {
128 opp-hz = /bits/ 64 <500000000>;
129 opp-microvolt = <600000>;
130 required-opps = <&cci_opp_0>;
133 opp-774000000 {
134 opp-hz = /bits/ 64 <774000000>;
135 opp-microvolt = <675000>;
136 required-opps = <&cci_opp_1>;
139 opp-875000000 {
140 opp-hz = /bits/ 64 <875000000>;
141 opp-microvolt = <700000>;
142 required-opps = <&cci_opp_2>;
145 opp-975000000 {
146 opp-hz = /bits/ 64 <975000000>;
147 opp-microvolt = <725000>;
148 required-opps = <&cci_opp_3>;
151 opp-1075000000 {
152 opp-hz = /bits/ 64 <1075000000>;
153 opp-microvolt = <750000>;
154 required-opps = <&cci_opp_4>;
157 opp-1175000000 {
158 opp-hz = /bits/ 64 <1175000000>;
159 opp-microvolt = <775000>;
160 required-opps = <&cci_opp_5>;
163 opp-1275000000 {
164 opp-hz = /bits/ 64 <1275000000>;
165 opp-microvolt = <800000>;
166 required-opps = <&cci_opp_6>;
169 opp-1375000000 {
170 opp-hz = /bits/ 64 <1375000000>;
171 opp-microvolt = <825000>;
172 required-opps = <&cci_opp_7>;
175 opp-1500000000 {
176 opp-hz = /bits/ 64 <1500000000>;
177 opp-microvolt = <856250>;
178 required-opps = <&cci_opp_8>;
181 opp-1618000000 {
182 opp-hz = /bits/ 64 <1618000000>;
183 opp-microvolt = <875000>;
184 required-opps = <&cci_opp_9>;
187 opp-1666000000 {
188 opp-hz = /bits/ 64 <1666000000>;
189 opp-microvolt = <900000>;
190 required-opps = <&cci_opp_10>;
193 opp-1733000000 {
194 opp-hz = /bits/ 64 <1733000000>;
195 opp-microvolt = <925000>;
196 required-opps = <&cci_opp_11>;
199 opp-1800000000 {
200 opp-hz = /bits/ 64 <1800000000>;
201 opp-microvolt = <950000>;
202 required-opps = <&cci_opp_12>;
205 opp-1866000000 {
206 opp-hz = /bits/ 64 <1866000000>;
207 opp-microvolt = <981250>;
208 required-opps = <&cci_opp_13>;
211 opp-1933000000 {
212 opp-hz = /bits/ 64 <1933000000>;
213 opp-microvolt = <1006250>;
214 required-opps = <&cci_opp_14>;
217 opp-2000000000 {
218 opp-hz = /bits/ 64 <2000000000>;
219 opp-microvolt = <1031250>;
220 required-opps = <&cci_opp_15>;
224 cluster1_opp: opp-table-cluster1 {
225 compatible = "operating-points-v2";
226 opp-shared;
228 opp-774000000 {
229 opp-hz = /bits/ 64 <774000000>;
230 opp-microvolt = <675000>;
231 required-opps = <&cci_opp_0>;
234 opp-835000000 {
235 opp-hz = /bits/ 64 <835000000>;
236 opp-microvolt = <693750>;
237 required-opps = <&cci_opp_1>;
240 opp-919000000 {
241 opp-hz = /bits/ 64 <919000000>;
242 opp-microvolt = <718750>;
243 required-opps = <&cci_opp_2>;
246 opp-1002000000 {
247 opp-hz = /bits/ 64 <1002000000>;
248 opp-microvolt = <743750>;
249 required-opps = <&cci_opp_3>;
252 opp-1085000000 {
253 opp-hz = /bits/ 64 <1085000000>;
254 opp-microvolt = <775000>;
255 required-opps = <&cci_opp_4>;
258 opp-1169000000 {
259 opp-hz = /bits/ 64 <1169000000>;
260 opp-microvolt = <800000>;
261 required-opps = <&cci_opp_5>;
264 opp-1308000000 {
265 opp-hz = /bits/ 64 <1308000000>;
266 opp-microvolt = <843750>;
267 required-opps = <&cci_opp_6>;
270 opp-1419000000 {
271 opp-hz = /bits/ 64 <1419000000>;
272 opp-microvolt = <875000>;
273 required-opps = <&cci_opp_7>;
276 opp-1530000000 {
277 opp-hz = /bits/ 64 <1530000000>;
278 opp-microvolt = <912500>;
279 required-opps = <&cci_opp_8>;
282 opp-1670000000 {
283 opp-hz = /bits/ 64 <1670000000>;
284 opp-microvolt = <956250>;
285 required-opps = <&cci_opp_9>;
288 opp-1733000000 {
289 opp-hz = /bits/ 64 <1733000000>;
290 opp-microvolt = <981250>;
291 required-opps = <&cci_opp_10>;
294 opp-1796000000 {
295 opp-hz = /bits/ 64 <1796000000>;
296 opp-microvolt = <1012500>;
297 required-opps = <&cci_opp_11>;
300 opp-1860000000 {
301 opp-hz = /bits/ 64 <1860000000>;
302 opp-microvolt = <1037500>;
303 required-opps = <&cci_opp_12>;
306 opp-1923000000 {
307 opp-hz = /bits/ 64 <1923000000>;
308 opp-microvolt = <1062500>;
309 required-opps = <&cci_opp_13>;
312 cluster1_opp_14: opp-1986000000 {
313 opp-hz = /bits/ 64 <1986000000>;
314 opp-microvolt = <1093750>;
315 required-opps = <&cci_opp_14>;
318 cluster1_opp_15: opp-2050000000 {
319 opp-hz = /bits/ 64 <2050000000>;
320 opp-microvolt = <1118750>;
321 required-opps = <&cci_opp_15>;
326 #address-cells = <1>;
327 #size-cells = <0>;
329 cpu-map {
367 compatible = "arm,cortex-a55";
369 enable-method = "psci";
370 clock-frequency = <2000000000>;
373 clock-names = "cpu", "intermediate";
374 operating-points-v2 = <&cluster0_opp>;
375 dynamic-power-coefficient = <84>;
376 capacity-dmips-mhz = <382>;
377 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
378 i-cache-size = <32768>;
379 i-cache-line-size = <64>;
380 i-cache-sets = <128>;
381 d-cache-size = <32768>;
382 d-cache-line-size = <64>;
383 d-cache-sets = <128>;
384 next-level-cache = <&l2_0>;
385 #cooling-cells = <2>;
391 compatible = "arm,cortex-a55";
393 enable-method = "psci";
394 clock-frequency = <2000000000>;
397 clock-names = "cpu", "intermediate";
398 operating-points-v2 = <&cluster0_opp>;
399 dynamic-power-coefficient = <84>;
400 capacity-dmips-mhz = <382>;
401 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
402 i-cache-size = <32768>;
403 i-cache-line-size = <64>;
404 i-cache-sets = <128>;
405 d-cache-size = <32768>;
406 d-cache-line-size = <64>;
407 d-cache-sets = <128>;
408 next-level-cache = <&l2_0>;
409 #cooling-cells = <2>;
415 compatible = "arm,cortex-a55";
417 enable-method = "psci";
418 clock-frequency = <2000000000>;
421 clock-names = "cpu", "intermediate";
422 operating-points-v2 = <&cluster0_opp>;
423 dynamic-power-coefficient = <84>;
424 capacity-dmips-mhz = <382>;
425 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
426 i-cache-size = <32768>;
427 i-cache-line-size = <64>;
428 i-cache-sets = <128>;
429 d-cache-size = <32768>;
430 d-cache-line-size = <64>;
431 d-cache-sets = <128>;
432 next-level-cache = <&l2_0>;
433 #cooling-cells = <2>;
439 compatible = "arm,cortex-a55";
441 enable-method = "psci";
442 clock-frequency = <2000000000>;
445 clock-names = "cpu", "intermediate";
446 operating-points-v2 = <&cluster0_opp>;
447 dynamic-power-coefficient = <84>;
448 capacity-dmips-mhz = <382>;
449 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
450 i-cache-size = <32768>;
451 i-cache-line-size = <64>;
452 i-cache-sets = <128>;
453 d-cache-size = <32768>;
454 d-cache-line-size = <64>;
455 d-cache-sets = <128>;
456 next-level-cache = <&l2_0>;
457 #cooling-cells = <2>;
463 compatible = "arm,cortex-a55";
465 enable-method = "psci";
466 clock-frequency = <2000000000>;
469 clock-names = "cpu", "intermediate";
470 operating-points-v2 = <&cluster0_opp>;
471 dynamic-power-coefficient = <84>;
472 capacity-dmips-mhz = <382>;
473 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
474 i-cache-size = <32768>;
475 i-cache-line-size = <64>;
476 i-cache-sets = <128>;
477 d-cache-size = <32768>;
478 d-cache-line-size = <64>;
479 d-cache-sets = <128>;
480 next-level-cache = <&l2_0>;
481 #cooling-cells = <2>;
487 compatible = "arm,cortex-a55";
489 enable-method = "psci";
490 clock-frequency = <2000000000>;
493 clock-names = "cpu", "intermediate";
494 operating-points-v2 = <&cluster0_opp>;
495 dynamic-power-coefficient = <84>;
496 capacity-dmips-mhz = <382>;
497 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
498 i-cache-size = <32768>;
499 i-cache-line-size = <64>;
500 i-cache-sets = <128>;
501 d-cache-size = <32768>;
502 d-cache-line-size = <64>;
503 d-cache-sets = <128>;
504 next-level-cache = <&l2_0>;
505 #cooling-cells = <2>;
511 compatible = "arm,cortex-a76";
513 enable-method = "psci";
514 clock-frequency = <2050000000>;
517 clock-names = "cpu", "intermediate";
518 operating-points-v2 = <&cluster1_opp>;
519 dynamic-power-coefficient = <335>;
520 capacity-dmips-mhz = <1024>;
521 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
522 i-cache-size = <65536>;
523 i-cache-line-size = <64>;
524 i-cache-sets = <256>;
525 d-cache-size = <65536>;
526 d-cache-line-size = <64>;
527 d-cache-sets = <256>;
528 next-level-cache = <&l2_1>;
529 #cooling-cells = <2>;
535 compatible = "arm,cortex-a76";
537 enable-method = "psci";
538 clock-frequency = <2050000000>;
541 clock-names = "cpu", "intermediate";
542 operating-points-v2 = <&cluster1_opp>;
543 dynamic-power-coefficient = <335>;
544 capacity-dmips-mhz = <1024>;
545 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
546 i-cache-size = <65536>;
547 i-cache-line-size = <64>;
548 i-cache-sets = <256>;
549 d-cache-size = <65536>;
550 d-cache-line-size = <64>;
551 d-cache-sets = <256>;
552 next-level-cache = <&l2_1>;
553 #cooling-cells = <2>;
557 idle-states {
558 entry-method = "psci";
560 cpu_ret_l: cpu-retention-l {
561 compatible = "arm,idle-state";
562 arm,psci-suspend-param = <0x00010001>;
563 local-timer-stop;
564 entry-latency-us = <50>;
565 exit-latency-us = <100>;
566 min-residency-us = <1600>;
569 cpu_ret_b: cpu-retention-b {
570 compatible = "arm,idle-state";
571 arm,psci-suspend-param = <0x00010001>;
572 local-timer-stop;
573 entry-latency-us = <50>;
574 exit-latency-us = <100>;
575 min-residency-us = <1400>;
578 cpu_off_l: cpu-off-l {
579 compatible = "arm,idle-state";
580 arm,psci-suspend-param = <0x01010001>;
581 local-timer-stop;
582 entry-latency-us = <100>;
583 exit-latency-us = <250>;
584 min-residency-us = <2100>;
587 cpu_off_b: cpu-off-b {
588 compatible = "arm,idle-state";
589 arm,psci-suspend-param = <0x01010001>;
590 local-timer-stop;
591 entry-latency-us = <100>;
592 exit-latency-us = <250>;
593 min-residency-us = <1900>;
597 l2_0: l2-cache0 {
599 cache-level = <2>;
600 cache-size = <131072>;
601 cache-line-size = <64>;
602 cache-sets = <512>;
603 next-level-cache = <&l3_0>;
604 cache-unified;
607 l2_1: l2-cache1 {
609 cache-level = <2>;
610 cache-size = <262144>;
611 cache-line-size = <64>;
612 cache-sets = <512>;
613 next-level-cache = <&l3_0>;
614 cache-unified;
617 l3_0: l3-cache {
619 cache-level = <3>;
620 cache-size = <1048576>;
621 cache-line-size = <64>;
622 cache-sets = <1024>;
623 cache-unified;
627 clk13m: fixed-factor-clock-13m {
628 compatible = "fixed-factor-clock";
629 #clock-cells = <0>;
631 clock-div = <2>;
632 clock-mult = <1>;
633 clock-output-names = "clk13m";
636 clk26m: oscillator-26m {
637 compatible = "fixed-clock";
638 #clock-cells = <0>;
639 clock-frequency = <26000000>;
640 clock-output-names = "clk26m";
643 clk32k: oscillator-32k {
644 compatible = "fixed-clock";
645 #clock-cells = <0>;
646 clock-frequency = <32768>;
647 clock-output-names = "clk32k";
650 gpu_opp_table: opp-table-gpu {
651 compatible = "operating-points-v2";
653 opp-299000000 {
654 opp-hz = /bits/ 64 <299000000>;
655 opp-microvolt = <612500>;
656 opp-supported-hw = <0xff>;
659 opp-332000000 {
660 opp-hz = /bits/ 64 <332000000>;
661 opp-microvolt = <625000>;
662 opp-supported-hw = <0xff>;
665 opp-366000000 {
666 opp-hz = /bits/ 64 <366000000>;
667 opp-microvolt = <637500>;
668 opp-supported-hw = <0xff>;
671 opp-400000000 {
672 opp-hz = /bits/ 64 <400000000>;
673 opp-microvolt = <643750>;
674 opp-supported-hw = <0xff>;
677 opp-434000000 {
678 opp-hz = /bits/ 64 <434000000>;
679 opp-microvolt = <656250>;
680 opp-supported-hw = <0xff>;
683 opp-484000000 {
684 opp-hz = /bits/ 64 <484000000>;
685 opp-microvolt = <668750>;
686 opp-supported-hw = <0xff>;
689 opp-535000000 {
690 opp-hz = /bits/ 64 <535000000>;
691 opp-microvolt = <687500>;
692 opp-supported-hw = <0xff>;
695 opp-586000000 {
696 opp-hz = /bits/ 64 <586000000>;
697 opp-microvolt = <700000>;
698 opp-supported-hw = <0xff>;
701 opp-637000000 {
702 opp-hz = /bits/ 64 <637000000>;
703 opp-microvolt = <712500>;
704 opp-supported-hw = <0xff>;
707 opp-690000000 {
708 opp-hz = /bits/ 64 <690000000>;
709 opp-microvolt = <737500>;
710 opp-supported-hw = <0xff>;
713 opp-743000000 {
714 opp-hz = /bits/ 64 <743000000>;
715 opp-microvolt = <756250>;
716 opp-supported-hw = <0xff>;
719 opp-796000000 {
720 opp-hz = /bits/ 64 <796000000>;
721 opp-microvolt = <781250>;
722 opp-supported-hw = <0xff>;
725 opp-850000000 {
726 opp-hz = /bits/ 64 <850000000>;
727 opp-microvolt = <800000>;
728 opp-supported-hw = <0xff>;
731 opp-900000000-3 {
732 opp-hz = /bits/ 64 <900000000>;
733 opp-microvolt = <850000>;
734 opp-supported-hw = <0xcf>;
737 opp-900000000-4 {
738 opp-hz = /bits/ 64 <900000000>;
739 opp-microvolt = <837500>;
740 opp-supported-hw = <0x10>;
743 opp-900000000-5 {
744 opp-hz = /bits/ 64 <900000000>;
745 opp-microvolt = <825000>;
746 opp-supported-hw = <0x20>;
749 opp-950000000-3 {
750 opp-hz = /bits/ 64 <950000000>;
751 opp-microvolt = <900000>;
752 opp-supported-hw = <0xcf>;
755 opp-950000000-4 {
756 opp-hz = /bits/ 64 <950000000>;
757 opp-microvolt = <875000>;
758 opp-supported-hw = <0x10>;
761 opp-950000000-5 {
762 opp-hz = /bits/ 64 <950000000>;
763 opp-microvolt = <850000>;
764 opp-supported-hw = <0x20>;
767 opp-1000000000-3 {
768 opp-hz = /bits/ 64 <1000000000>;
769 opp-microvolt = <950000>;
770 opp-supported-hw = <0xcf>;
773 opp-1000000000-4 {
774 opp-hz = /bits/ 64 <1000000000>;
775 opp-microvolt = <912500>;
776 opp-supported-hw = <0x10>;
779 opp-1000000000-5 {
780 opp-hz = /bits/ 64 <1000000000>;
781 opp-microvolt = <875000>;
782 opp-supported-hw = <0x20>;
786 pmu-a55 {
787 compatible = "arm,cortex-a55-pmu";
788 interrupt-parent = <&gic>;
792 pmu-a76 {
793 compatible = "arm,cortex-a76-pmu";
794 interrupt-parent = <&gic>;
799 compatible = "arm,psci-1.0";
804 compatible = "arm,armv8-timer";
805 interrupt-parent = <&gic>;
813 #address-cells = <2>;
814 #size-cells = <2>;
815 compatible = "simple-bus";
816 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
819 gic: interrupt-controller@c000000 {
820 compatible = "arm,gic-v3";
821 #interrupt-cells = <4>;
822 #redistributor-regions = <1>;
823 interrupt-parent = <&gic>;
824 interrupt-controller;
829 ppi-partitions {
830 ppi_cluster0: interrupt-partition-0 {
834 ppi_cluster1: interrupt-partition-1 {
841 compatible = "mediatek,mt8186-mcusys", "syscon";
843 #clock-cells = <1>;
847 compatible = "mediatek,mt8186-topckgen", "syscon";
849 #clock-cells = <1>;
853 compatible = "mediatek,mt8186-infracfg_ao", "syscon";
855 #clock-cells = <1>;
856 #reset-cells = <1>;
860 compatible = "mediatek,mt8186-pericfg", "syscon";
865 compatible = "mediatek,mt8186-pinctrl";
874 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",
876 gpio-controller;
877 #gpio-cells = <2>;
878 gpio-ranges = <&pio 0 0 185>;
879 interrupt-controller;
881 #interrupt-cells = <2>;
885 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";
889 spm: power-controller {
890 compatible = "mediatek,mt8186-power-controller";
891 #address-cells = <1>;
892 #size-cells = <0>;
893 #power-domain-cells = <1>;
896 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
899 clock-names = "mfg00";
900 #address-cells = <1>;
901 #size-cells = <0>;
902 #power-domain-cells = <1>;
904 mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 {
907 #address-cells = <1>;
908 #size-cells = <0>;
909 #power-domain-cells = <1>;
911 power-domain@MT8186_POWER_DOMAIN_MFG2 {
913 #power-domain-cells = <0>;
916 power-domain@MT8186_POWER_DOMAIN_MFG3 {
918 #power-domain-cells = <0>;
923 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP {
927 clock-names = "subsys-csirx-top0",
928 "subsys-csirx-top1";
929 #power-domain-cells = <0>;
932 power-domain@MT8186_POWER_DOMAIN_SSUSB {
936 clock-names = "sys_ck", "ref_ck";
937 #power-domain-cells = <0>;
940 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 {
944 clock-names = "sys_ck", "ref_ck";
945 #power-domain-cells = <0>;
948 power-domain@MT8186_POWER_DOMAIN_ADSP_AO {
952 clock-names = "audioadsp",
953 "subsys-adsp-bus";
954 #address-cells = <1>;
955 #size-cells = <0>;
956 #power-domain-cells = <1>;
958 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA {
960 #address-cells = <1>;
961 #size-cells = <0>;
962 #power-domain-cells = <1>;
964 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP {
967 #power-domain-cells = <0>;
972 power-domain@MT8186_POWER_DOMAIN_CONN_ON {
975 #power-domain-cells = <0>;
978 power-domain@MT8186_POWER_DOMAIN_DIS {
986 clock-names = "disp", "mdp",
987 "subsys-smi-infra",
988 "subsys-smi-common",
989 "subsys-smi-gals",
990 "subsys-smi-iommu";
992 #address-cells = <1>;
993 #size-cells = <0>;
994 #power-domain-cells = <1>;
996 power-domain@MT8186_POWER_DOMAIN_VDEC {
1000 clock-names = "vdec0", "larb";
1002 #power-domain-cells = <0>;
1005 power-domain@MT8186_POWER_DOMAIN_CAM {
1014 clock-names = "cam0", "cam1", "cam2",
1016 "subsys-cam-tm",
1017 "subsys-cam-top";
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021 #power-domain-cells = <1>;
1023 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB {
1025 #power-domain-cells = <0>;
1028 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA {
1030 #power-domain-cells = <0>;
1034 power-domain@MT8186_POWER_DOMAIN_IMG {
1038 clock-names = "gals", "subsys-img-top";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1042 #power-domain-cells = <1>;
1044 power-domain@MT8186_POWER_DOMAIN_IMG2 {
1046 #power-domain-cells = <0>;
1050 power-domain@MT8186_POWER_DOMAIN_IPE {
1057 clock-names = "subsys-ipe-top",
1058 "subsys-ipe-larb0",
1059 "subsys-ipe-larb1",
1060 "subsys-ipe-smi",
1061 "subsys-ipe-gals";
1063 #power-domain-cells = <0>;
1066 power-domain@MT8186_POWER_DOMAIN_VENC {
1070 clock-names = "venc0", "subsys-larb";
1072 #power-domain-cells = <0>;
1075 power-domain@MT8186_POWER_DOMAIN_WPE {
1080 clock-names = "wpe0",
1081 "subsys-larb-ck",
1082 "subsys-larb-pclk";
1084 #power-domain-cells = <0>;
1091 compatible = "mediatek,mt8186-wdt";
1092 mediatek,disable-extrst;
1094 #reset-cells = <1>;
1098 compatible = "mediatek,mt8186-apmixedsys", "syscon";
1100 #clock-cells = <1>;
1104 compatible = "mediatek,mt8186-pwrap", "syscon";
1106 reg-names = "pwrap";
1110 clock-names = "spi", "wrap";
1114 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi";
1116 reg-names = "pmif", "spmimst";
1120 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
1121 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>;
1122 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
1129 compatible = "mediatek,mt8186-timer",
1130 "mediatek,mt6765-timer";
1137 compatible = "mediatek,mt8186-gce";
1140 clock-names = "gce";
1142 #mbox-cells = <2>;
1146 compatible = "mediatek,mt8186-scp";
1149 reg-names = "sram", "cfg";
1154 compatible = "mediatek,mt8186-dsp";
1157 reg-names = "cfg", "sram", "sec", "bus";
1159 clock-names = "audiodsp", "adsp_bus";
1160 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>,
1162 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
1163 mbox-names = "rx", "tx";
1165 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>;
1170 compatible = "mediatek,mt8186-adsp-mbox";
1171 #mbox-cells = <0>;
1177 compatible = "mediatek,mt8186-adsp-mbox";
1178 #mbox-cells = <0>;
1184 compatible = "mediatek,mt8186-nor";
1190 clock-names = "spi", "sf", "axi", "axi_s";
1191 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
1192 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
1198 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";
1200 #io-channel-cells = <1>;
1202 clock-names = "main";
1206 compatible = "mediatek,mt8186-uart",
1207 "mediatek,mt6577-uart";
1211 clock-names = "baud", "bus";
1216 compatible = "mediatek,mt8186-uart",
1217 "mediatek,mt6577-uart";
1221 clock-names = "baud", "bus";
1226 compatible = "mediatek,mt8186-i2c";
1232 clock-names = "main", "dma";
1233 clock-div = <1>;
1234 #address-cells = <1>;
1235 #size-cells = <0>;
1240 compatible = "mediatek,mt8186-i2c";
1246 clock-names = "main", "dma";
1247 clock-div = <1>;
1248 #address-cells = <1>;
1249 #size-cells = <0>;
1254 compatible = "mediatek,mt8186-i2c";
1260 clock-names = "main", "dma";
1261 clock-div = <1>;
1262 #address-cells = <1>;
1263 #size-cells = <0>;
1268 compatible = "mediatek,mt8186-i2c";
1274 clock-names = "main", "dma";
1275 clock-div = <1>;
1276 #address-cells = <1>;
1277 #size-cells = <0>;
1282 compatible = "mediatek,mt8186-i2c";
1288 clock-names = "main", "dma";
1289 clock-div = <1>;
1290 #address-cells = <1>;
1291 #size-cells = <0>;
1296 compatible = "mediatek,mt8186-i2c";
1302 clock-names = "main", "dma";
1303 clock-div = <1>;
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1310 compatible = "mediatek,mt8186-i2c";
1316 clock-names = "main", "dma";
1317 clock-div = <1>;
1318 #address-cells = <1>;
1319 #size-cells = <0>;
1324 compatible = "mediatek,mt8186-i2c";
1330 clock-names = "main", "dma";
1331 clock-div = <1>;
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1338 compatible = "mediatek,mt8186-i2c";
1344 clock-names = "main", "dma";
1345 clock-div = <1>;
1346 #address-cells = <1>;
1347 #size-cells = <0>;
1352 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1353 #address-cells = <1>;
1354 #size-cells = <0>;
1360 clock-names = "parent-clk", "sel-clk", "spi-clk";
1365 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
1368 #pwm-cells = <2>;
1371 clock-names = "main", "mm";
1376 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1377 #address-cells = <1>;
1378 #size-cells = <0>;
1384 clock-names = "parent-clk", "sel-clk", "spi-clk";
1389 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1397 clock-names = "parent-clk", "sel-clk", "spi-clk";
1402 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1403 #address-cells = <1>;
1404 #size-cells = <0>;
1410 clock-names = "parent-clk", "sel-clk", "spi-clk";
1415 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1416 #address-cells = <1>;
1417 #size-cells = <0>;
1423 clock-names = "parent-clk", "sel-clk", "spi-clk";
1428 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1429 #address-cells = <1>;
1430 #size-cells = <0>;
1436 clock-names = "parent-clk", "sel-clk", "spi-clk";
1440 imp_iic_wrap: clock-controller@11017000 {
1441 compatible = "mediatek,mt8186-imp_iic_wrap";
1443 #clock-cells = <1>;
1447 compatible = "mediatek,mt8186-uart",
1448 "mediatek,mt6577-uart";
1452 clock-names = "baud", "bus";
1457 compatible = "mediatek,mt8186-i2c";
1463 clock-names = "main", "dma";
1464 clock-div = <1>;
1465 #address-cells = <1>;
1466 #size-cells = <0>;
1470 afe: audio-controller@11210000 {
1471 compatible = "mediatek,mt8186-sound";
1498 clock-names = "aud_infra_clk",
1528 reset-names = "audiosys";
1533 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
1535 reg-names = "mac", "ippc";
1541 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1544 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
1545 #address-cells = <2>;
1546 #size-cells = <2>;
1551 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
1553 reg-names = "mac";
1559 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1561 mediatek,syscon-wakeup = <&pericfg 0x420 2>;
1562 wakeup-source;
1568 compatible = "mediatek,mt8186-mmc",
1569 "mediatek,mt8183-mmc";
1576 clock-names = "source", "hclk", "source_cg", "crypto";
1578 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
1579 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>;
1584 compatible = "mediatek,mt8186-mmc",
1585 "mediatek,mt8183-mmc";
1591 clock-names = "source", "hclk", "source_cg";
1593 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1594 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1599 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
1601 reg-names = "mac", "ippc";
1607 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1610 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
1611 #address-cells = <2>;
1612 #size-cells = <2>;
1617 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
1619 reg-names = "mac";
1625 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
1627 mediatek,syscon-wakeup = <&pericfg 0x424 2>;
1628 wakeup-source;
1633 u3phy0: t-phy@11c80000 {
1634 compatible = "mediatek,mt8186-tphy",
1635 "mediatek,generic-tphy-v2";
1636 #address-cells = <1>;
1637 #size-cells = <1>;
1641 u2port1: usb-phy@0 {
1644 clock-names = "ref";
1645 #phy-cells = <1>;
1648 u3port1: usb-phy@700 {
1651 clock-names = "ref";
1652 #phy-cells = <1>;
1656 u3phy1: t-phy@11ca0000 {
1657 compatible = "mediatek,mt8186-tphy",
1658 "mediatek,generic-tphy-v2";
1659 #address-cells = <1>;
1660 #size-cells = <1>;
1664 u2port0: usb-phy@0 {
1667 clock-names = "ref";
1668 #phy-cells = <1>;
1674 compatible = "mediatek,mt8186-efuse", "mediatek,efuse";
1676 #address-cells = <1>;
1677 #size-cells = <1>;
1679 gpu_speedbin: gpu-speedbin@59c {
1685 mipi_tx0: dsi-phy@11cc0000 {
1686 compatible = "mediatek,mt8183-mipi-tx";
1689 #clock-cells = <0>;
1690 #phy-cells = <0>;
1691 clock-output-names = "mipi_tx0_pll";
1695 mfgsys: clock-controller@13000000 {
1696 compatible = "mediatek,mt8186-mfgsys";
1698 #clock-cells = <1>;
1702 compatible = "mediatek,mt8186-mali",
1703 "arm,mali-bifrost";
1710 interrupt-names = "job", "mmu", "gpu";
1711 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>,
1713 power-domain-names = "core0", "core1";
1714 #cooling-cells = <2>;
1715 nvmem-cells = <&gpu_speedbin>;
1716 nvmem-cell-names = "speed-bin";
1717 operating-points-v2 = <&gpu_opp_table>;
1718 dynamic-power-coefficient = <4687>;
1723 compatible = "mediatek,mt8186-mmsys", "syscon";
1725 #clock-cells = <1>;
1726 #reset-cells = <1>;
1729 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1733 compatible = "mediatek,mt8186-disp-mutex";
1737 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1738 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1740 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1744 compatible = "mediatek,mt8186-smi-common";
1748 clock-names = "apb", "smi", "gals0", "gals1";
1749 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1753 compatible = "mediatek,mt8186-smi-larb";
1757 clock-names = "apb", "smi";
1758 mediatek,larb-id = <0>;
1760 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1764 compatible = "mediatek,mt8186-smi-larb";
1768 clock-names = "apb", "smi";
1769 mediatek,larb-id = <1>;
1771 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1775 compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl";
1780 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1781 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1785 compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l";
1790 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1791 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1795 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
1800 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1801 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1805 compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color";
1809 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1810 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1814 compatible = "mediatek,mt8186-dpi";
1819 clock-names = "pixel", "engine", "pll";
1820 assigned-clocks = <&topckgen CLK_TOP_DPI>;
1821 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
1831 compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr";
1835 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1836 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1840 compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal";
1844 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1845 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1849 compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma";
1853 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1854 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1858 compatible = "mediatek,mt8186-disp-postmask",
1859 "mediatek,mt8192-disp-postmask";
1863 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1864 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1868 compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither";
1872 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1873 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1877 compatible = "mediatek,mt8186-dsi";
1882 clock-names = "engine", "digital", "hs";
1884 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1887 phy-names = "dphy";
1896 compatible = "mediatek,mt8186-iommu-mm";
1899 clock-names = "bclk";
1905 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1906 #iommu-cells = <1>;
1910 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
1915 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>;
1916 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1919 wpesys: clock-controller@14020000 {
1920 compatible = "mediatek,mt8186-wpesys";
1922 #clock-cells = <1>;
1926 compatible = "mediatek,mt8186-smi-larb";
1930 clock-names = "apb", "smi";
1931 mediatek,larb-id = <8>;
1933 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>;
1936 imgsys1: clock-controller@15020000 {
1937 compatible = "mediatek,mt8186-imgsys1";
1939 #clock-cells = <1>;
1943 compatible = "mediatek,mt8186-smi-larb";
1947 clock-names = "apb", "smi";
1948 mediatek,larb-id = <9>;
1950 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>;
1953 imgsys2: clock-controller@15820000 {
1954 compatible = "mediatek,mt8186-imgsys2";
1956 #clock-cells = <1>;
1960 compatible = "mediatek,mt8186-smi-larb";
1964 clock-names = "apb", "smi";
1965 mediatek,larb-id = <11>;
1967 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>;
1971 compatible = "mediatek,mt8186-smi-larb";
1975 clock-names = "apb", "smi";
1976 mediatek,larb-id = <4>;
1978 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
1981 vdecsys: clock-controller@1602f000 {
1982 compatible = "mediatek,mt8186-vdecsys";
1984 #clock-cells = <1>;
1987 vencsys: clock-controller@17000000 {
1988 compatible = "mediatek,mt8186-vencsys";
1990 #clock-cells = <1>;
1994 compatible = "mediatek,mt8186-smi-larb";
1998 clock-names = "apb", "smi";
1999 mediatek,larb-id = <7>;
2001 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
2004 camsys: clock-controller@1a000000 {
2005 compatible = "mediatek,mt8186-camsys";
2007 #clock-cells = <1>;
2011 compatible = "mediatek,mt8186-smi-larb";
2014 clock-names = "apb", "smi";
2015 mediatek,larb-id = <13>;
2017 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2021 compatible = "mediatek,mt8186-smi-larb";
2024 clock-names = "apb", "smi";
2025 mediatek,larb-id = <14>;
2027 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2031 compatible = "mediatek,mt8186-smi-larb";
2035 clock-names = "apb", "smi";
2036 mediatek,larb-id = <16>;
2038 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>;
2042 compatible = "mediatek,mt8186-smi-larb";
2046 clock-names = "apb", "smi";
2047 mediatek,larb-id = <17>;
2049 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>;
2052 camsys_rawa: clock-controller@1a04f000 {
2053 compatible = "mediatek,mt8186-camsys_rawa";
2055 #clock-cells = <1>;
2058 camsys_rawb: clock-controller@1a06f000 {
2059 compatible = "mediatek,mt8186-camsys_rawb";
2061 #clock-cells = <1>;
2064 mdpsys: clock-controller@1b000000 {
2065 compatible = "mediatek,mt8186-mdpsys";
2067 #clock-cells = <1>;
2071 compatible = "mediatek,mt8186-smi-larb";
2074 clock-names = "apb", "smi";
2075 mediatek,larb-id = <2>;
2077 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
2080 ipesys: clock-controller@1c000000 {
2081 compatible = "mediatek,mt8186-ipesys";
2083 #clock-cells = <1>;
2087 compatible = "mediatek,mt8186-smi-larb";
2090 clock-names = "apb", "smi";
2091 mediatek,larb-id = <20>;
2093 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
2097 compatible = "mediatek,mt8186-smi-larb";
2100 clock-names = "apb", "smi";
2101 mediatek,larb-id = <19>;
2103 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;