Lines Matching +full:0 +full:x1400e000
327 #size-cells = <0>;
365 cpu0: cpu@0 {
368 reg = <0x000>;
392 reg = <0x100>;
416 reg = <0x200>;
440 reg = <0x300>;
464 reg = <0x400>;
488 reg = <0x500>;
512 reg = <0x600>;
536 reg = <0x700>;
562 arm,psci-suspend-param = <0x00010001>;
571 arm,psci-suspend-param = <0x00010001>;
580 arm,psci-suspend-param = <0x01010001>;
589 arm,psci-suspend-param = <0x01010001>;
629 #clock-cells = <0>;
638 #clock-cells = <0>;
645 #clock-cells = <0>;
656 opp-supported-hw = <0xff>;
662 opp-supported-hw = <0xff>;
668 opp-supported-hw = <0xff>;
674 opp-supported-hw = <0xff>;
680 opp-supported-hw = <0xff>;
686 opp-supported-hw = <0xff>;
692 opp-supported-hw = <0xff>;
698 opp-supported-hw = <0xff>;
704 opp-supported-hw = <0xff>;
710 opp-supported-hw = <0xff>;
716 opp-supported-hw = <0xff>;
722 opp-supported-hw = <0xff>;
728 opp-supported-hw = <0xff>;
734 opp-supported-hw = <0xcf>;
740 opp-supported-hw = <0x10>;
746 opp-supported-hw = <0x20>;
752 opp-supported-hw = <0xcf>;
758 opp-supported-hw = <0x10>;
764 opp-supported-hw = <0x20>;
770 opp-supported-hw = <0xcf>;
776 opp-supported-hw = <0x10>;
782 opp-supported-hw = <0x20>;
806 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
807 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
808 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
809 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
816 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
825 reg = <0 0x0c000000 0 0x40000>,
826 <0 0x0c040000 0 0x200000>;
827 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
830 ppi_cluster0: interrupt-partition-0 {
842 reg = <0 0xc53a000 0 0x1000>;
848 reg = <0 0x10000000 0 0x1000>;
854 reg = <0 0x10001000 0 0x1000>;
861 reg = <0 0x10003000 0 0x1000>;
866 reg = <0 0x10005000 0 0x1000>,
867 <0 0x10002000 0 0x0200>,
868 <0 0x10002200 0 0x0200>,
869 <0 0x10002400 0 0x0200>,
870 <0 0x10002600 0 0x0200>,
871 <0 0x10002a00 0 0x0200>,
872 <0 0x10002c00 0 0x0200>,
873 <0 0x1000b000 0 0x1000>;
878 gpio-ranges = <&pio 0 0 185>;
880 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
886 reg = <0 0x10006000 0 0x1000>;
892 #size-cells = <0>;
901 #size-cells = <0>;
908 #size-cells = <0>;
913 #power-domain-cells = <0>;
918 #power-domain-cells = <0>;
929 #power-domain-cells = <0>;
937 #power-domain-cells = <0>;
945 #power-domain-cells = <0>;
955 #size-cells = <0>;
961 #size-cells = <0>;
967 #power-domain-cells = <0>;
975 #power-domain-cells = <0>;
993 #size-cells = <0>;
1002 #power-domain-cells = <0>;
1020 #size-cells = <0>;
1025 #power-domain-cells = <0>;
1030 #power-domain-cells = <0>;
1041 #size-cells = <0>;
1046 #power-domain-cells = <0>;
1063 #power-domain-cells = <0>;
1072 #power-domain-cells = <0>;
1084 #power-domain-cells = <0>;
1093 reg = <0 0x10007000 0 0x1000>;
1099 reg = <0 0x1000c000 0 0x1000>;
1105 reg = <0 0x1000d000 0 0x1000>;
1107 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1115 reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>;
1123 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>,
1124 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>;
1131 reg = <0 0x10017000 0 0x1000>;
1132 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>;
1138 reg = <0 0X1022c000 0 0x4000>;
1141 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
1147 reg = <0 0x10500000 0 0x40000>,
1148 <0 0x105c0000 0 0x19080>;
1150 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1155 reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>,
1156 <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>;
1171 #mbox-cells = <0>;
1172 reg = <0 0x10686100 0 0x1000>;
1173 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
1178 #mbox-cells = <0>;
1179 reg = <0 0x10687100 0 0x1000>;
1180 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>;
1185 reg = <0 0x11000000 0 0x1000>;
1193 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>;
1199 reg = <0 0x11001000 0 0x1000>;
1208 reg = <0 0x11002000 0 0x1000>;
1209 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
1218 reg = <0 0x11003000 0 0x1000>;
1219 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1227 reg = <0 0x11007000 0 0x1000>,
1228 <0 0x10200100 0 0x100>;
1229 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
1235 #size-cells = <0>;
1241 reg = <0 0x11008000 0 0x1000>,
1242 <0 0x10200200 0 0x100>;
1243 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1249 #size-cells = <0>;
1255 reg = <0 0x11009000 0 0x1000>,
1256 <0 0x10200300 0 0x180>;
1257 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>;
1263 #size-cells = <0>;
1269 reg = <0 0x1100f000 0 0x1000>,
1270 <0 0x10200480 0 0x100>;
1271 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
1277 #size-cells = <0>;
1283 reg = <0 0x11011000 0 0x1000>,
1284 <0 0x10200580 0 0x180>;
1285 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
1291 #size-cells = <0>;
1297 reg = <0 0x11016000 0 0x1000>,
1298 <0 0x10200700 0 0x100>;
1299 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
1305 #size-cells = <0>;
1311 reg = <0 0x1100d000 0 0x1000>,
1312 <0 0x10200800 0 0x100>;
1313 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
1319 #size-cells = <0>;
1325 reg = <0 0x11004000 0 0x1000>,
1326 <0 0x10200900 0 0x180>;
1327 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
1333 #size-cells = <0>;
1339 reg = <0 0x11005000 0 0x1000>,
1340 <0 0x10200A80 0 0x180>;
1341 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1347 #size-cells = <0>;
1354 #size-cells = <0>;
1355 reg = <0 0x1100a000 0 0x1000>;
1356 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
1366 reg = <0 0x1100e000 0 0x1000>;
1367 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1378 #size-cells = <0>;
1379 reg = <0 0x11010000 0 0x1000>;
1380 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>;
1391 #size-cells = <0>;
1392 reg = <0 0x11012000 0 0x1000>;
1393 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>;
1404 #size-cells = <0>;
1405 reg = <0 0x11013000 0 0x1000>;
1406 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
1417 #size-cells = <0>;
1418 reg = <0 0x11014000 0 0x1000>;
1419 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1430 #size-cells = <0>;
1431 reg = <0 0x11015000 0 0x1000>;
1432 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1442 reg = <0 0x11017000 0 0x1000>;
1449 reg = <0 0x11018000 0 0x1000>;
1450 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>;
1458 reg = <0 0x11019000 0 0x1000>,
1459 <0 0x10200c00 0 0x180>;
1460 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
1466 #size-cells = <0>;
1472 reg = <0 0x11210000 0 0x2000>;
1523 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1534 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
1542 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
1552 reg = <0 0x11200000 0 0x1000>;
1560 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
1561 mediatek,syscon-wakeup = <&pericfg 0x420 2>;
1570 reg = <0 0x11230000 0 0x10000>,
1571 <0 0x11cd0000 0 0x1000>;
1577 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
1586 reg = <0 0x11240000 0 0x1000>,
1587 <0 0x11c90000 0 0x1000>;
1592 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
1600 reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>;
1608 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
1618 reg = <0 0x11280000 0 0x1000>;
1626 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
1627 mediatek,syscon-wakeup = <&pericfg 0x424 2>;
1638 ranges = <0x0 0x0 0x11c80000 0x1000>;
1641 u2port1: usb-phy@0 {
1642 reg = <0x0 0x700>;
1649 reg = <0x700 0x900>;
1661 ranges = <0x0 0x0 0x11ca0000 0x1000>;
1664 u2port0: usb-phy@0 {
1665 reg = <0x0 0x700>;
1669 mediatek,discth = <0x8>;
1675 reg = <0 0x11cb0000 0 0x1000>;
1680 reg = <0x59c 0x4>;
1681 bits = <0 3>;
1687 reg = <0 0x11cc0000 0 0x1000>;
1689 #clock-cells = <0>;
1690 #phy-cells = <0>;
1697 reg = <0 0x13000000 0 0x1000>;
1704 reg = <0 0x13040000 0 0x4000>;
1707 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>,
1708 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
1709 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
1724 reg = <0 0x14000000 0 0x1000>;
1727 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1729 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1734 reg = <0 0x14001000 0 0x1000>;
1736 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
1737 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1745 reg = <0 0x14002000 0 0x1000>;
1754 reg = <0 0x14003000 0 0x1000>;
1758 mediatek,larb-id = <0>;
1765 reg = <0 0x14004000 0 0x1000>;
1776 reg = <0 0x14005000 0 0x1000>;
1778 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
1780 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1786 reg = <0 0x14006000 0 0x1000>;
1788 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
1790 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1796 reg = <0 0x14007000 0 0x1000>;
1798 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
1800 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1806 reg = <0 0x14009000 0 0x1000>;
1808 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>;
1809 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1815 reg = <0 0x1400a000 0 0x1000>;
1822 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
1832 reg = <0 0x1400b000 0 0x1000>;
1834 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>;
1835 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1841 reg = <0 0x1400c000 0 0x1000>;
1843 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>;
1844 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1850 reg = <0 0x1400d000 0 0x1000>;
1852 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
1853 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1860 reg = <0 0x1400e000 0 0x1000>;
1862 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
1863 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1869 reg = <0 0x1400f000 0 0x1000>;
1871 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>;
1872 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1878 reg = <0 0x14013000 0 0x1000>;
1883 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>;
1897 reg = <0 0x14016000 0 0x1000>;
1900 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>;
1911 reg = <0 0x1401f000 0 0x1000>;
1913 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>;
1915 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>;
1921 reg = <0 0x14020000 0 0x1000>;
1927 reg = <0 0x14023000 0 0x1000>;
1938 reg = <0 0x15020000 0 0x1000>;
1944 reg = <0 0x1502e000 0 0x1000>;
1955 reg = <0 0x15820000 0 0x1000>;
1961 reg = <0 0x1582e000 0 0x1000>;
1972 reg = <0 0x1602e000 0 0x1000>;
1983 reg = <0 0x1602f000 0 0x1000>;
1989 reg = <0 0x17000000 0 0x1000>;
1995 reg = <0 0x17010000 0 0x1000>;
2006 reg = <0 0x1a000000 0 0x1000>;
2012 reg = <0 0x1a001000 0 0x1000>;
2022 reg = <0 0x1a002000 0 0x1000>;
2032 reg = <0 0x1a00f000 0 0x1000>;
2043 reg = <0 0x1a010000 0 0x1000>;
2054 reg = <0 0x1a04f000 0 0x1000>;
2060 reg = <0 0x1a06f000 0 0x1000>;
2066 reg = <0 0x1b000000 0 0x1000>;
2072 reg = <0 0x1b002000 0 0x1000>;
2082 reg = <0 0x1c000000 0 0x1000>;
2088 reg = <0 0x1c00f000 0 0x1000>;
2098 reg = <0 0x1c10f000 0 0x1000>;