Lines Matching +full:gce +full:- +full:client +full:- +full:reg
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
16 #include "mt8173-pinfunc.h"
20 interrupt-parent = <&sysirq>;
21 #address-cells = <2>;
22 #size-cells = <2>;
39 mdp-rdma0 = &mdp_rdma0;
40 mdp-rdma1 = &mdp_rdma1;
41 mdp-rsz0 = &mdp_rsz0;
42 mdp-rsz1 = &mdp_rsz1;
43 mdp-rsz2 = &mdp_rsz2;
44 mdp-wdma0 = &mdp_wdma0;
45 mdp-wrot0 = &mdp_wrot0;
46 mdp-wrot1 = &mdp_wrot1;
53 cluster0_opp: opp-table-0 {
54 compatible = "operating-points-v2";
55 opp-shared;
56 opp-507000000 {
57 opp-hz = /bits/ 64 <507000000>;
58 opp-microvolt = <859000>;
60 opp-702000000 {
61 opp-hz = /bits/ 64 <702000000>;
62 opp-microvolt = <908000>;
64 opp-1001000000 {
65 opp-hz = /bits/ 64 <1001000000>;
66 opp-microvolt = <983000>;
68 opp-1105000000 {
69 opp-hz = /bits/ 64 <1105000000>;
70 opp-microvolt = <1009000>;
72 opp-1209000000 {
73 opp-hz = /bits/ 64 <1209000000>;
74 opp-microvolt = <1034000>;
76 opp-1300000000 {
77 opp-hz = /bits/ 64 <1300000000>;
78 opp-microvolt = <1057000>;
80 opp-1508000000 {
81 opp-hz = /bits/ 64 <1508000000>;
82 opp-microvolt = <1109000>;
84 opp-1703000000 {
85 opp-hz = /bits/ 64 <1703000000>;
86 opp-microvolt = <1125000>;
90 cluster1_opp: opp-table-1 {
91 compatible = "operating-points-v2";
92 opp-shared;
93 opp-507000000 {
94 opp-hz = /bits/ 64 <507000000>;
95 opp-microvolt = <828000>;
97 opp-702000000 {
98 opp-hz = /bits/ 64 <702000000>;
99 opp-microvolt = <867000>;
101 opp-1001000000 {
102 opp-hz = /bits/ 64 <1001000000>;
103 opp-microvolt = <927000>;
105 opp-1209000000 {
106 opp-hz = /bits/ 64 <1209000000>;
107 opp-microvolt = <968000>;
109 opp-1404000000 {
110 opp-hz = /bits/ 64 <1404000000>;
111 opp-microvolt = <1007000>;
113 opp-1612000000 {
114 opp-hz = /bits/ 64 <1612000000>;
115 opp-microvolt = <1049000>;
117 opp-1807000000 {
118 opp-hz = /bits/ 64 <1807000000>;
119 opp-microvolt = <1089000>;
121 opp-2106000000 {
122 opp-hz = /bits/ 64 <2106000000>;
123 opp-microvolt = <1125000>;
128 #address-cells = <1>;
129 #size-cells = <0>;
131 cpu-map {
153 compatible = "arm,cortex-a53";
154 reg = <0x000>;
155 enable-method = "psci";
156 cpu-idle-states = <&CPU_SLEEP_0>;
157 #cooling-cells = <2>;
158 dynamic-power-coefficient = <263>;
161 clock-names = "cpu", "intermediate";
162 operating-points-v2 = <&cluster0_opp>;
163 capacity-dmips-mhz = <740>;
168 compatible = "arm,cortex-a53";
169 reg = <0x001>;
170 enable-method = "psci";
171 cpu-idle-states = <&CPU_SLEEP_0>;
172 #cooling-cells = <2>;
173 dynamic-power-coefficient = <263>;
176 clock-names = "cpu", "intermediate";
177 operating-points-v2 = <&cluster0_opp>;
178 capacity-dmips-mhz = <740>;
183 compatible = "arm,cortex-a72";
184 reg = <0x100>;
185 enable-method = "psci";
186 cpu-idle-states = <&CPU_SLEEP_0>;
187 #cooling-cells = <2>;
188 dynamic-power-coefficient = <530>;
191 clock-names = "cpu", "intermediate";
192 operating-points-v2 = <&cluster1_opp>;
193 capacity-dmips-mhz = <1024>;
198 compatible = "arm,cortex-a72";
199 reg = <0x101>;
200 enable-method = "psci";
201 cpu-idle-states = <&CPU_SLEEP_0>;
202 #cooling-cells = <2>;
203 dynamic-power-coefficient = <530>;
206 clock-names = "cpu", "intermediate";
207 operating-points-v2 = <&cluster1_opp>;
208 capacity-dmips-mhz = <1024>;
211 idle-states {
212 entry-method = "psci";
214 CPU_SLEEP_0: cpu-sleep-0 {
215 compatible = "arm,idle-state";
216 local-timer-stop;
217 entry-latency-us = <639>;
218 exit-latency-us = <680>;
219 min-residency-us = <1088>;
220 arm,psci-suspend-param = <0x0010000>;
226 compatible = "arm,cortex-a53-pmu";
229 interrupt-affinity = <&cpu0>, <&cpu1>;
233 compatible = "arm,cortex-a72-pmu";
236 interrupt-affinity = <&cpu2>, <&cpu3>;
240 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
248 compatible = "fixed-clock";
249 #clock-cells = <0>;
250 clock-frequency = <26000000>;
251 clock-output-names = "clk26m";
255 compatible = "fixed-clock";
256 #clock-cells = <0>;
257 clock-frequency = <32000>;
258 clock-output-names = "clk32k";
262 compatible = "fixed-clock";
263 #clock-cells = <0>;
264 clock-frequency = <0>;
265 clock-output-names = "cpum_ck";
268 thermal-zones {
269 cpu_thermal: cpu-thermal {
270 polling-delay-passive = <1000>; /* milliseconds */
271 polling-delay = <1000>; /* milliseconds */
273 thermal-sensors = <&thermal>;
274 sustainable-power = <1500>; /* milliwatts */
277 threshold: trip-point0 {
283 target: trip-point1 {
296 cooling-maps {
299 cooling-device = <&cpu0 THERMAL_NO_LIMIT
307 cooling-device = <&cpu2 THERMAL_NO_LIMIT
317 reserved-memory {
318 #address-cells = <2>;
319 #size-cells = <2>;
322 compatible = "shared-dma-pool";
323 reg = <0 0xb7000000 0 0x500000>;
325 no-map;
330 compatible = "arm,armv8-timer";
331 interrupt-parent = <&gic>;
340 arm,no-tick-in-suspend;
344 #address-cells = <2>;
345 #size-cells = <2>;
346 compatible = "simple-bus";
349 topckgen: clock-controller@10000000 {
350 compatible = "mediatek,mt8173-topckgen";
351 reg = <0 0x10000000 0 0x1000>;
352 #clock-cells = <1>;
355 infracfg: power-controller@10001000 {
356 compatible = "mediatek,mt8173-infracfg", "syscon";
357 reg = <0 0x10001000 0 0x1000>;
358 #clock-cells = <1>;
359 #reset-cells = <1>;
362 pericfg: power-controller@10003000 {
363 compatible = "mediatek,mt8173-pericfg", "syscon";
364 reg = <0 0x10003000 0 0x1000>;
365 #clock-cells = <1>;
366 #reset-cells = <1>;
370 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
371 reg = <0 0x10005000 0 0x1000>;
375 compatible = "mediatek,mt8173-pinctrl";
376 reg = <0 0x1000b000 0 0x1000>;
377 mediatek,pctl-regmap = <&syscfg_pctl_a>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
391 input-enable;
392 bias-pull-down;
400 bias-disable;
408 bias-disable;
416 bias-disable;
424 bias-disable;
432 bias-disable;
440 bias-disable;
446 compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
447 reg = <0 0x10006000 0 0x1000>;
450 spm: power-controller {
451 compatible = "mediatek,mt8173-power-controller";
452 #address-cells = <1>;
453 #size-cells = <0>;
454 #power-domain-cells = <1>;
457 power-domain@MT8173_POWER_DOMAIN_VDEC {
458 reg = <MT8173_POWER_DOMAIN_VDEC>;
460 clock-names = "mm";
461 #power-domain-cells = <0>;
463 power-domain@MT8173_POWER_DOMAIN_VENC {
464 reg = <MT8173_POWER_DOMAIN_VENC>;
467 clock-names = "mm", "venc";
468 #power-domain-cells = <0>;
470 power-domain@MT8173_POWER_DOMAIN_ISP {
471 reg = <MT8173_POWER_DOMAIN_ISP>;
473 clock-names = "mm";
474 #power-domain-cells = <0>;
476 power-domain@MT8173_POWER_DOMAIN_MM {
477 reg = <MT8173_POWER_DOMAIN_MM>;
479 clock-names = "mm";
480 #power-domain-cells = <0>;
483 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
484 reg = <MT8173_POWER_DOMAIN_VENC_LT>;
487 clock-names = "mm", "venclt";
488 #power-domain-cells = <0>;
490 power-domain@MT8173_POWER_DOMAIN_AUDIO {
491 reg = <MT8173_POWER_DOMAIN_AUDIO>;
492 #power-domain-cells = <0>;
494 power-domain@MT8173_POWER_DOMAIN_USB {
495 reg = <MT8173_POWER_DOMAIN_USB>;
496 #power-domain-cells = <0>;
498 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
499 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
501 clock-names = "mfg";
502 #address-cells = <1>;
503 #size-cells = <0>;
504 #power-domain-cells = <1>;
506 power-domain@MT8173_POWER_DOMAIN_MFG_2D {
507 reg = <MT8173_POWER_DOMAIN_MFG_2D>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510 #power-domain-cells = <1>;
512 power-domain@MT8173_POWER_DOMAIN_MFG {
513 reg = <MT8173_POWER_DOMAIN_MFG>;
514 #power-domain-cells = <0>;
523 compatible = "mediatek,mt8173-wdt",
524 "mediatek,mt6589-wdt";
525 reg = <0 0x10007000 0 0x100>;
529 compatible = "mediatek,mt8173-timer",
530 "mediatek,mt6577-timer";
531 reg = <0 0x10008000 0 0x1000>;
538 compatible = "mediatek,mt8173-pwrap";
539 reg = <0 0x1000d000 0 0x1000>;
540 reg-names = "pwrap";
543 reset-names = "pwrap";
545 clock-names = "spi", "wrap";
549 compatible = "mediatek,mt8173-cec";
550 reg = <0 0x10013000 0 0xbc>;
557 compatible = "mediatek,mt8173-vpu";
558 reg = <0 0x10020000 0 0x30000>,
560 reg-names = "tcm", "cfg_reg";
563 clock-names = "main";
564 memory-region = <&vpu_dma_reserved>;
567 sysirq: intpol-controller@10200620 {
568 compatible = "mediatek,mt8173-sysirq",
569 "mediatek,mt6577-sysirq";
570 interrupt-controller;
571 #interrupt-cells = <3>;
572 interrupt-parent = <&gic>;
573 reg = <0 0x10200620 0 0x20>;
577 compatible = "mediatek,mt8173-m4u";
578 reg = <0 0x10205000 0 0x1000>;
581 clock-names = "bclk";
585 #iommu-cells = <1>;
589 compatible = "mediatek,mt8173-efuse";
590 reg = <0 0x10206000 0 0x1000>;
591 #address-cells = <1>;
592 #size-cells = <1>;
594 reg = <0x528 0xc>;
598 apmixedsys: clock-controller@10209000 {
599 compatible = "mediatek,mt8173-apmixedsys";
600 reg = <0 0x10209000 0 0x1000>;
601 #clock-cells = <1>;
604 hdmi_phy: hdmi-phy@10209100 {
605 compatible = "mediatek,mt8173-hdmi-phy";
606 reg = <0 0x10209100 0 0x24>;
608 clock-names = "pll_ref";
609 clock-output-names = "hdmitx_dig_cts";
612 #clock-cells = <0>;
613 #phy-cells = <0>;
617 gce: mailbox@10212000 { label
618 compatible = "mediatek,mt8173-gce";
619 reg = <0 0x10212000 0 0x1000>;
622 clock-names = "gce";
623 #mbox-cells = <2>;
626 mipi_tx0: dsi-phy@10215000 {
627 compatible = "mediatek,mt8173-mipi-tx";
628 reg = <0 0x10215000 0 0x1000>;
630 clock-output-names = "mipi_tx0_pll";
631 #clock-cells = <0>;
632 #phy-cells = <0>;
636 mipi_tx1: dsi-phy@10216000 {
637 compatible = "mediatek,mt8173-mipi-tx";
638 reg = <0 0x10216000 0 0x1000>;
640 clock-output-names = "mipi_tx1_pll";
641 #clock-cells = <0>;
642 #phy-cells = <0>;
646 gic: interrupt-controller@10221000 {
647 compatible = "arm,gic-400";
648 #interrupt-cells = <3>;
649 interrupt-parent = <&gic>;
650 interrupt-controller;
651 reg = <0 0x10221000 0 0x1000>,
660 compatible = "mediatek,mt8173-auxadc";
661 reg = <0 0x11001000 0 0x1000>;
663 clock-names = "main";
664 #io-channel-cells = <1>;
668 compatible = "mediatek,mt8173-uart",
669 "mediatek,mt6577-uart";
670 reg = <0 0x11002000 0 0x400>;
673 clock-names = "baud", "bus";
678 compatible = "mediatek,mt8173-uart",
679 "mediatek,mt6577-uart";
680 reg = <0 0x11003000 0 0x400>;
683 clock-names = "baud", "bus";
688 compatible = "mediatek,mt8173-uart",
689 "mediatek,mt6577-uart";
690 reg = <0 0x11004000 0 0x400>;
693 clock-names = "baud", "bus";
698 compatible = "mediatek,mt8173-uart",
699 "mediatek,mt6577-uart";
700 reg = <0 0x11005000 0 0x400>;
703 clock-names = "baud", "bus";
708 compatible = "mediatek,mt8173-i2c";
709 reg = <0 0x11007000 0 0x70>,
712 clock-div = <16>;
715 clock-names = "main", "dma";
716 pinctrl-names = "default";
717 pinctrl-0 = <&i2c0_pins_a>;
718 #address-cells = <1>;
719 #size-cells = <0>;
724 compatible = "mediatek,mt8173-i2c";
725 reg = <0 0x11008000 0 0x70>,
728 clock-div = <16>;
731 clock-names = "main", "dma";
732 pinctrl-names = "default";
733 pinctrl-0 = <&i2c1_pins_a>;
734 #address-cells = <1>;
735 #size-cells = <0>;
740 compatible = "mediatek,mt8173-i2c";
741 reg = <0 0x11009000 0 0x70>,
744 clock-div = <16>;
747 clock-names = "main", "dma";
748 pinctrl-names = "default";
749 pinctrl-0 = <&i2c2_pins_a>;
750 #address-cells = <1>;
751 #size-cells = <0>;
756 compatible = "mediatek,mt8173-spi";
757 #address-cells = <1>;
758 #size-cells = <0>;
759 reg = <0 0x1100a000 0 0x1000>;
764 clock-names = "parent-clk", "sel-clk", "spi-clk";
769 #thermal-sensor-cells = <0>;
770 compatible = "mediatek,mt8173-thermal";
771 reg = <0 0x1100b000 0 0x1000>;
774 clock-names = "therm", "auxadc";
778 nvmem-cells = <&thermal_calibration>;
779 nvmem-cell-names = "calibration-data";
783 compatible = "mediatek,mt8173-nor";
784 reg = <0 0x1100d000 0 0xe0>;
785 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
786 assigned-clock-parents = <&clk26m>;
790 clock-names = "spi", "sf", "axi";
791 #address-cells = <1>;
792 #size-cells = <0>;
797 compatible = "mediatek,mt8173-i2c";
798 reg = <0 0x11010000 0 0x70>,
801 clock-div = <16>;
804 clock-names = "main", "dma";
805 pinctrl-names = "default";
806 pinctrl-0 = <&i2c3_pins_a>;
807 #address-cells = <1>;
808 #size-cells = <0>;
813 compatible = "mediatek,mt8173-i2c";
814 reg = <0 0x11011000 0 0x70>,
817 clock-div = <16>;
820 clock-names = "main", "dma";
821 pinctrl-names = "default";
822 pinctrl-0 = <&i2c4_pins_a>;
823 #address-cells = <1>;
824 #size-cells = <0>;
829 compatible = "mediatek,mt8173-hdmi-ddc";
831 reg = <0 0x11012000 0 0x1C>;
833 clock-names = "ddc-i2c";
837 compatible = "mediatek,mt8173-i2c";
838 reg = <0 0x11013000 0 0x70>,
841 clock-div = <16>;
844 clock-names = "main", "dma";
845 pinctrl-names = "default";
846 pinctrl-0 = <&i2c6_pins_a>;
847 #address-cells = <1>;
848 #size-cells = <0>;
852 afe: audio-controller@11220000 {
853 compatible = "mediatek,mt8173-afe-pcm";
854 reg = <0 0x11220000 0 0x1000>;
856 power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>;
867 clock-names = "infra_sys_audio_clk",
877 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
879 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
884 compatible = "mediatek,mt8173-mmc";
885 reg = <0 0x11230000 0 0x1000>;
889 clock-names = "source", "hclk";
894 compatible = "mediatek,mt8173-mmc";
895 reg = <0 0x11240000 0 0x1000>;
899 clock-names = "source", "hclk";
904 compatible = "mediatek,mt8173-mmc";
905 reg = <0 0x11250000 0 0x1000>;
909 clock-names = "source", "hclk";
914 compatible = "mediatek,mt8173-mmc";
915 reg = <0 0x11260000 0 0x1000>;
919 clock-names = "source", "hclk";
924 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
925 reg = <0 0x11271000 0 0x3000>,
927 reg-names = "mac", "ippc";
932 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
934 clock-names = "sys_ck", "ref_ck";
935 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
936 #address-cells = <2>;
937 #size-cells = <2>;
942 compatible = "mediatek,mt8173-xhci",
943 "mediatek,mtk-xhci";
944 reg = <0 0x11270000 0 0x1000>;
945 reg-names = "mac";
947 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
949 clock-names = "sys_ck", "ref_ck";
954 u3phy: t-phy@11290000 {
955 compatible = "mediatek,mt8173-u3phy";
956 reg = <0 0x11290000 0 0x800>;
957 #address-cells = <2>;
958 #size-cells = <2>;
962 u2port0: usb-phy@11290800 {
963 reg = <0 0x11290800 0 0x100>;
965 clock-names = "ref";
966 #phy-cells = <1>;
970 u3port0: usb-phy@11290900 {
971 reg = <0 0x11290900 0 0x700>;
973 clock-names = "ref";
974 #phy-cells = <1>;
978 u2port1: usb-phy@11291000 {
979 reg = <0 0x11291000 0 0x100>;
981 clock-names = "ref";
982 #phy-cells = <1>;
988 compatible = "mediatek,mt8173-mmsys", "syscon";
989 reg = <0 0x14000000 0 0x1000>;
990 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
991 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
992 assigned-clock-rates = <400000000>;
993 #clock-cells = <1>;
994 #reset-cells = <1>;
995 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
996 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
997 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1001 compatible = "mediatek,mt8173-mdp-rdma",
1002 "mediatek,mt8173-mdp";
1003 reg = <0 0x14001000 0 0x1000>;
1006 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1012 compatible = "mediatek,mt8173-mdp-rdma";
1013 reg = <0 0x14002000 0 0x1000>;
1016 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1021 compatible = "mediatek,mt8173-mdp-rsz";
1022 reg = <0 0x14003000 0 0x1000>;
1024 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1028 compatible = "mediatek,mt8173-mdp-rsz";
1029 reg = <0 0x14004000 0 0x1000>;
1031 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1035 compatible = "mediatek,mt8173-mdp-rsz";
1036 reg = <0 0x14005000 0 0x1000>;
1038 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1042 compatible = "mediatek,mt8173-mdp-wdma";
1043 reg = <0 0x14006000 0 0x1000>;
1045 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1050 compatible = "mediatek,mt8173-mdp-wrot";
1051 reg = <0 0x14007000 0 0x1000>;
1053 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1058 compatible = "mediatek,mt8173-mdp-wrot";
1059 reg = <0 0x14008000 0 0x1000>;
1061 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1066 compatible = "mediatek,mt8173-disp-ovl";
1067 reg = <0 0x1400c000 0 0x1000>;
1069 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1072 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1076 compatible = "mediatek,mt8173-disp-ovl";
1077 reg = <0 0x1400d000 0 0x1000>;
1079 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1082 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1086 compatible = "mediatek,mt8173-disp-rdma";
1087 reg = <0 0x1400e000 0 0x1000>;
1089 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1092 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1096 compatible = "mediatek,mt8173-disp-rdma";
1097 reg = <0 0x1400f000 0 0x1000>;
1099 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1102 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1106 compatible = "mediatek,mt8173-disp-rdma";
1107 reg = <0 0x14010000 0 0x1000>;
1109 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1112 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1116 compatible = "mediatek,mt8173-disp-wdma";
1117 reg = <0 0x14011000 0 0x1000>;
1119 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1122 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1126 compatible = "mediatek,mt8173-disp-wdma";
1127 reg = <0 0x14012000 0 0x1000>;
1129 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1132 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1136 compatible = "mediatek,mt8173-disp-color";
1137 reg = <0 0x14013000 0 0x1000>;
1139 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1141 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1145 compatible = "mediatek,mt8173-disp-color";
1146 reg = <0 0x14014000 0 0x1000>;
1148 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1150 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1154 compatible = "mediatek,mt8173-disp-aal";
1155 reg = <0 0x14015000 0 0x1000>;
1157 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1159 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1163 compatible = "mediatek,mt8173-disp-gamma";
1164 reg = <0 0x14016000 0 0x1000>;
1166 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1168 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1172 compatible = "mediatek,mt8173-disp-merge";
1173 reg = <0 0x14017000 0 0x1000>;
1174 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1179 compatible = "mediatek,mt8173-disp-split";
1180 reg = <0 0x14018000 0 0x1000>;
1181 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1186 compatible = "mediatek,mt8173-disp-split";
1187 reg = <0 0x14019000 0 0x1000>;
1188 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1193 compatible = "mediatek,mt8173-disp-ufoe";
1194 reg = <0 0x1401a000 0 0x1000>;
1196 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1198 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
1202 compatible = "mediatek,mt8173-dsi";
1203 reg = <0 0x1401b000 0 0x1000>;
1205 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1209 clock-names = "engine", "digital", "hs";
1212 phy-names = "dphy";
1217 compatible = "mediatek,mt8173-dsi";
1218 reg = <0 0x1401c000 0 0x1000>;
1220 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1224 clock-names = "engine", "digital", "hs";
1226 phy-names = "dphy";
1231 compatible = "mediatek,mt8173-dpi";
1232 reg = <0 0x1401d000 0 0x1000>;
1234 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1238 clock-names = "pixel", "engine", "pll";
1243 remote-endpoint = <&hdmi0_in>;
1249 compatible = "mediatek,mt8173-disp-pwm",
1250 "mediatek,mt6595-disp-pwm";
1251 reg = <0 0x1401e000 0 0x1000>;
1252 #pwm-cells = <2>;
1255 clock-names = "main", "mm";
1260 compatible = "mediatek,mt8173-disp-pwm",
1261 "mediatek,mt6595-disp-pwm";
1262 reg = <0 0x1401f000 0 0x1000>;
1263 #pwm-cells = <2>;
1266 clock-names = "main", "mm";
1271 compatible = "mediatek,mt8173-disp-mutex";
1272 reg = <0 0x14020000 0 0x1000>;
1274 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1276 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
1277 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
1282 compatible = "mediatek,mt8173-smi-larb";
1283 reg = <0 0x14021000 0 0x1000>;
1285 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1288 clock-names = "apb", "smi";
1292 compatible = "mediatek,mt8173-smi-common";
1293 reg = <0 0x14022000 0 0x1000>;
1294 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1297 clock-names = "apb", "smi";
1301 compatible = "mediatek,mt8173-disp-od";
1302 reg = <0 0x14023000 0 0x1000>;
1304 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
1308 compatible = "mediatek,mt8173-hdmi";
1309 reg = <0 0x14025000 0 0x400>;
1315 clock-names = "pixel", "pll", "bclk", "spdif";
1316 pinctrl-names = "default";
1317 pinctrl-0 = <&hdmi_pin>;
1319 phy-names = "hdmi";
1320 mediatek,syscon-hdmi = <&mmsys 0x900>;
1321 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1322 assigned-clock-parents = <&hdmi_phy>;
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1330 reg = <0>;
1333 remote-endpoint = <&dpi0_out>;
1340 compatible = "mediatek,mt8173-smi-larb";
1341 reg = <0 0x14027000 0 0x1000>;
1343 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1346 clock-names = "apb", "smi";
1349 imgsys: clock-controller@15000000 {
1350 compatible = "mediatek,mt8173-imgsys", "syscon";
1351 reg = <0 0x15000000 0 0x1000>;
1352 #clock-cells = <1>;
1356 compatible = "mediatek,mt8173-smi-larb";
1357 reg = <0 0x15001000 0 0x1000>;
1359 power-domains = <&spm MT8173_POWER_DOMAIN_ISP>;
1362 clock-names = "apb", "smi";
1365 vdecsys: clock-controller@16000000 {
1366 compatible = "mediatek,mt8173-vdecsys", "syscon";
1367 reg = <0 0x16000000 0 0x1000>;
1368 #clock-cells = <1>;
1372 compatible = "mediatek,mt8173-vcodec-dec";
1373 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
1395 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1404 clock-names = "vcodecpll",
1412 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1417 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1420 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1424 compatible = "mediatek,mt8173-smi-larb";
1425 reg = <0 0x16010000 0 0x1000>;
1427 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1430 clock-names = "apb", "smi";
1433 vencsys: clock-controller@18000000 {
1434 compatible = "mediatek,mt8173-vencsys", "syscon";
1435 reg = <0 0x18000000 0 0x1000>;
1436 #clock-cells = <1>;
1440 compatible = "mediatek,mt8173-smi-larb";
1441 reg = <0 0x18001000 0 0x1000>;
1443 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1446 clock-names = "apb", "smi";
1450 compatible = "mediatek,mt8173-vcodec-enc";
1451 reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
1466 clock-names = "venc_sel";
1467 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1468 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
1469 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1473 compatible = "mediatek,mt8173-jpgdec";
1474 reg = <0 0x18004000 0 0x1000>;
1478 clock-names = "jpgdec-smi",
1480 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1485 vencltsys: clock-controller@19000000 {
1486 compatible = "mediatek,mt8173-vencltsys", "syscon";
1487 reg = <0 0x19000000 0 0x1000>;
1488 #clock-cells = <1>;
1492 compatible = "mediatek,mt8173-smi-larb";
1493 reg = <0 0x19001000 0 0x1000>;
1495 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
1498 clock-names = "apb", "smi";
1502 compatible = "mediatek,mt8173-vcodec-enc-vp8";
1503 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
1516 clock-names = "venc_lt_sel";
1517 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1518 assigned-clock-parents =
1520 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;