Lines Matching +full:default +full:- +full:pins
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 chassis-type = "embedded";
19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
38 sram-supply = <&mt6380_vm_reg>;
42 gpio-keys {
43 compatible = "gpio-keys";
45 key-factory {
51 key-wps {
63 reg_1p8v: regulator-1p8v {
64 compatible = "regulator-fixed";
65 regulator-name = "fixed-1.8V";
66 regulator-min-microvolt = <1800000>;
67 regulator-max-microvolt = <1800000>;
68 regulator-always-on;
71 reg_3p3v: regulator-3p3v {
72 compatible = "regulator-fixed";
73 regulator-name = "fixed-3.3V";
74 regulator-min-microvolt = <3300000>;
75 regulator-max-microvolt = <3300000>;
76 regulator-boot-on;
77 regulator-always-on;
80 reg_5v: regulator-5v {
81 compatible = "regulator-fixed";
82 regulator-name = "fixed-5V";
83 regulator-min-microvolt = <5000000>;
84 regulator-max-microvolt = <5000000>;
85 regulator-boot-on;
86 regulator-always-on;
99 pinctrl-names = "default";
100 pinctrl-0 = <&irrx_pins>;
105 pinctrl-names = "default";
106 pinctrl-0 = <ð_pins>;
110 compatible = "mediatek,eth-mac";
112 phy-mode = "2500base-x";
114 fixed-link {
116 full-duplex;
121 mdio-bus {
122 #address-cells = <1>;
123 #size-cells = <0>;
128 reset-gpios = <&pio 54 0>;
131 #address-cells = <1>;
132 #size-cells = <0>;
163 phy-mode = "2500base-x";
165 fixed-link {
167 full-duplex;
178 pinctrl-names = "default";
179 pinctrl-0 = <&i2c1_pins>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&i2c2_pins>;
190 pinctrl-names = "default", "state_uhs";
191 pinctrl-0 = <&emmc_pins_default>;
192 pinctrl-1 = <&emmc_pins_uhs>;
194 bus-width = <8>;
195 max-frequency = <50000000>;
196 cap-mmc-highspeed;
197 mmc-hs200-1_8v;
198 vmmc-supply = <®_3p3v>;
199 vqmmc-supply = <®_1p8v>;
200 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
201 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
202 non-removable;
206 pinctrl-names = "default", "state_uhs";
207 pinctrl-0 = <&sd0_pins_default>;
208 pinctrl-1 = <&sd0_pins_uhs>;
210 bus-width = <4>;
211 max-frequency = <50000000>;
212 cap-sd-highspeed;
213 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
214 vmmc-supply = <®_3p3v>;
215 vqmmc-supply = <®_3p3v>;
216 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
217 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
221 pinctrl-names = "default";
222 pinctrl-0 = <¶llel_nand_pins>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&spi_nor_pins>;
232 compatible = "jedec,spi-nor";
238 pinctrl-names = "default";
239 pinctrl-0 = <&pcie0_pins>;
245 emmc_pins_default: emmc-pins-default {
252 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
255 conf-cmd-dat {
256 pins = "NDL0", "NDL1", "NDL2",
259 input-enable;
260 bias-pull-up;
263 conf-clk {
264 pins = "NCLE";
265 bias-pull-down;
269 emmc_pins_uhs: emmc-pins-uhs {
275 conf-cmd-dat {
276 pins = "NDL0", "NDL1", "NDL2",
279 input-enable;
280 drive-strength = <4>;
281 bias-pull-up;
284 conf-clk {
285 pins = "NCLE";
286 drive-strength = <4>;
287 bias-pull-down;
291 eth_pins: eth-pins {
298 i2c1_pins: i2c1-pins {
305 i2c2_pins: i2c2-pins {
312 i2s1_pins: i2s1-pins {
321 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
323 drive-strength = <12>;
324 bias-pull-down;
328 irrx_pins: irrx-pins {
335 irtx_pins: irtx-pins {
343 parallel_nand_pins: parallel-nand-pins {
350 pcie0_pins: pcie0-pins {
359 pcie1_pins: pcie1-pins {
368 pmic_bus_pins: pmic-bus-pins {
375 pwm7_pins: pwm1-2-pins {
382 wled_pins: wled-pins {
389 sd0_pins_default: sd0-pins-default {
399 conf-cmd-data {
400 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
402 input-enable;
403 drive-strength = <8>;
404 bias-pull-up;
406 conf-clk {
407 pins = "I2S3_OUT";
408 drive-strength = <12>;
409 bias-pull-down;
411 conf-cd {
412 pins = "TXD3";
413 bias-pull-up;
417 sd0_pins_uhs: sd0-pins-uhs {
423 conf-cmd-data {
424 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
426 input-enable;
427 bias-pull-up;
430 conf-clk {
431 pins = "I2S3_OUT";
432 bias-pull-down;
436 /* Serial NAND is shared pin with SPI-NOR */
437 serial_nand_pins: serial-nand-pins {
444 spic0_pins: spic0-pins {
451 spic1_pins: spic1-pins {
458 /* SPI-NOR is shared pin with serial NAND */
459 spi_nor_pins: spi-nor-pins {
466 /* serial NAND is shared pin with SPI-NOR */
467 serial_nand_pins: serial-nand-pins {
474 uart0_pins: uart0-pins {
481 uart2_pins: uart2-pins {
488 watchdog_pins: watchdog-pins {
495 wmac_pins: wmac-pins {
507 pinctrl-names = "default";
508 pinctrl-0 = <&pwm7_pins>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&pmic_bus_pins>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&spic0_pins>;
534 pinctrl-names = "default";
535 pinctrl-0 = <&spic1_pins>;
540 vusb33-supply = <®_3p3v>;
541 vbus-supply = <®_5v>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&uart0_pins>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&uart2_pins>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&watchdog_pins>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&wmac_pins>;