Lines Matching +full:conf +full:- +full:mdio
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
38 sram-supply = <&mt6380_vm_reg>;
42 gpio-keys {
43 compatible = "gpio-keys";
45 factory-key {
51 wps-key {
59 compatible = "gpio-leds";
61 led-0 {
62 label = "bpi-r64:pio:green";
65 default-state = "off";
68 led-1 {
69 label = "bpi-r64:pio:red";
72 default-state = "off";
81 reg_1p8v: regulator-1p8v {
82 compatible = "regulator-fixed";
83 regulator-name = "fixed-1.8V";
84 regulator-min-microvolt = <1800000>;
85 regulator-max-microvolt = <1800000>;
86 regulator-always-on;
89 reg_3p3v: regulator-3p3v {
90 compatible = "regulator-fixed";
91 regulator-name = "fixed-3.3V";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
94 regulator-boot-on;
95 regulator-always-on;
98 reg_5v: regulator-5v {
99 compatible = "regulator-fixed";
100 regulator-name = "fixed-5V";
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
103 regulator-boot-on;
104 regulator-always-on;
117 pinctrl-names = "default";
118 pinctrl-0 = <&irrx_pins>;
125 compatible = "mediatek,eth-mac";
127 phy-mode = "2500base-x";
129 fixed-link {
131 full-duplex;
137 compatible = "mediatek,eth-mac";
139 phy-mode = "rgmii";
141 fixed-link {
143 full-duplex;
148 mdio: mdio-bus { label
149 #address-cells = <1>;
150 #size-cells = <0>;
155 interrupt-controller;
156 #interrupt-cells = <1>;
157 interrupt-parent = <&pio>;
159 reset-gpios = <&pio 54 0>;
162 #address-cells = <1>;
163 #size-cells = <0>;
194 phy-mode = "2500base-x";
196 fixed-link {
198 full-duplex;
209 pinctrl-names = "default";
210 pinctrl-0 = <&i2c1_pins>;
215 pinctrl-names = "default";
216 pinctrl-0 = <&i2c2_pins>;
221 pinctrl-names = "default", "state_uhs";
222 pinctrl-0 = <&emmc_pins_default>;
223 pinctrl-1 = <&emmc_pins_uhs>;
225 bus-width = <8>;
226 max-frequency = <50000000>;
227 cap-mmc-highspeed;
228 mmc-hs200-1_8v;
229 vmmc-supply = <®_3p3v>;
230 vqmmc-supply = <®_1p8v>;
231 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
232 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
233 non-removable;
237 pinctrl-names = "default", "state_uhs";
238 pinctrl-0 = <&sd0_pins_default>;
239 pinctrl-1 = <&sd0_pins_uhs>;
241 bus-width = <4>;
242 max-frequency = <50000000>;
243 cap-sd-highspeed;
244 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
245 vmmc-supply = <®_3p3v>;
246 vqmmc-supply = <®_3p3v>;
247 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
248 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
252 pinctrl-names = "default";
253 pinctrl-0 = <¶llel_nand_pins>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&serial_nand_pins>;
266 compatible = "spi-nand";
268 spi-tx-bus-width = <4>;
269 spi-rx-bus-width = <4>;
270 nand-ecc-engine = <&snfi>;
272 compatible = "fixed-partitions";
273 #address-cells = <1>;
274 #size-cells = <1>;
279 read-only;
285 read-only;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pcie0_pins>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&pcie1_pins>;
310 * SATA functions. i.e. output-high: PCIe, output-low: SATA
313 gpio-hog;
315 output-high;
319 emmc_pins_default: emmc-pins-default {
329 conf-cmd-dat {
333 input-enable;
334 bias-pull-up;
337 conf-clk {
339 bias-pull-down;
343 emmc_pins_uhs: emmc-pins-uhs {
349 conf-cmd-dat {
353 input-enable;
354 drive-strength = <4>;
355 bias-pull-up;
358 conf-clk {
360 drive-strength = <4>;
361 bias-pull-down;
365 eth_pins: eth-pins {
372 i2c1_pins: i2c1-pins {
379 i2c2_pins: i2c2-pins {
386 i2s1_pins: i2s1-pins {
394 conf {
397 drive-strength = <12>;
398 bias-pull-down;
402 irrx_pins: irrx-pins {
409 irtx_pins: irtx-pins {
417 parallel_nand_pins: parallel-nand-pins {
424 pcie0_pins: pcie0-pins {
433 pcie1_pins: pcie1-pins {
442 pmic_bus_pins: pmic-bus-pins {
449 pwm_pins: pwm-pins {
461 wled_pins: wled-pins {
468 sd0_pins_default: sd0-pins-default {
478 conf-cmd-data {
481 input-enable;
482 drive-strength = <8>;
483 bias-pull-up;
485 conf-clk {
487 drive-strength = <12>;
488 bias-pull-down;
490 conf-cd {
492 bias-pull-up;
496 sd0_pins_uhs: sd0-pins-uhs {
502 conf-cmd-data {
505 input-enable;
506 bias-pull-up;
509 conf-clk {
511 bias-pull-down;
515 /* Serial NAND is shared pin with SPI-NOR */
516 serial_nand_pins: serial-nand-pins {
523 spic0_pins: spic0-pins {
530 spic1_pins: spic1-pins {
537 /* SPI-NOR is shared pin with serial NAND */
538 spi_nor_pins: spi-nor-pins {
545 /* serial NAND is shared pin with SPI-NOR */
546 serial_nand_pins: serial-nand-pins {
553 uart0_pins: uart0-pins {
560 uart2_pins: uart2-pins {
567 watchdog_pins: watchdog-pins {
576 pinctrl-names = "default";
577 pinctrl-0 = <&pwm_pins>;
582 pinctrl-names = "default";
583 pinctrl-0 = <&pmic_bus_pins>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&spic0_pins>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&spic1_pins>;
608 vusb33-supply = <®_3p3v>;
609 vbus-supply = <®_5v>;
618 pinctrl-names = "default";
619 pinctrl-0 = <&uart0_pins>;
624 pinctrl-names = "default";
625 pinctrl-0 = <&uart2_pins>;
629 pinctrl-names = "default";
630 pinctrl-0 = <&watchdog_pins>;