dts/mediatek/mt6795.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
10 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
11 #include <dt-bindings/memory/mt6795-larb-port.h>
12 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
13 #include <dt-bindings/power/mt6795-power.h>
14 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
18 	interrupt-parent = <&sysirq>;
19 	#address-cells = <2>;
20 	#size-cells = <2>;
23 		compatible = "arm,psci-0.2";
28 		#address-cells = <1>;
29 		#size-cells = <0>;
31 		cpu0: cpu@0 {
32 			device_type = "cpu";
33 			compatible = "arm,cortex-a53";
34 			enable-method = "psci";
36 			cci-control-port = <&cci_control2>;
37 			next-level-cache = <&l2_0>;
40 		cpu1: cpu@1 {
41 			device_type = "cpu";
42 			compatible = "arm,cortex-a53";
43 			enable-method = "psci";
45 			cci-control-port = <&cci_control2>;
46 			i-cache-size = <32768>;
47 			i-cache-line-size = <64>;
48 			i-cache-sets = <256>;
49 			d-cache-size = <32768>;
50 			d-cache-line-size = <64>;
51 			d-cache-sets = <128>;
52 			next-level-cache = <&l2_0>;
55 		cpu2: cpu@2 {
56 			device_type = "cpu";
57 			compatible = "arm,cortex-a53";
58 			enable-method = "psci";
60 			cci-control-port = <&cci_control2>;
61 			i-cache-size = <32768>;
62 			i-cache-line-size = <64>;
63 			i-cache-sets = <256>;
64 			d-cache-size = <32768>;
65 			d-cache-line-size = <64>;
66 			d-cache-sets = <128>;
67 			next-level-cache = <&l2_0>;
70 		cpu3: cpu@3 {
71 			device_type = "cpu";
72 			compatible = "arm,cortex-a53";
73 			enable-method = "psci";
75 			cci-control-port = <&cci_control2>;
76 			i-cache-size = <32768>;
77 			i-cache-line-size = <64>;
78 			i-cache-sets = <256>;
79 			d-cache-size = <32768>;
80 			d-cache-line-size = <64>;
81 			d-cache-sets = <128>;
82 			next-level-cache = <&l2_0>;
85 		cpu4: cpu@100 {
86 			device_type = "cpu";
87 			compatible = "arm,cortex-a53";
88 			enable-method = "psci";
90 			cci-control-port = <&cci_control1>;
91 			i-cache-size = <32768>;
92 			i-cache-line-size = <64>;
93 			i-cache-sets = <256>;
94 			d-cache-size = <32768>;
95 			d-cache-line-size = <64>;
96 			d-cache-sets = <128>;
97 			next-level-cache = <&l2_1>;
100 		cpu5: cpu@101 {
101 			device_type = "cpu";
102 			compatible = "arm,cortex-a53";
103 			enable-method = "psci";
105 			cci-control-port = <&cci_control1>;
106 			i-cache-size = <32768>;
107 			i-cache-line-size = <64>;
108 			i-cache-sets = <256>;
109 			d-cache-size = <32768>;
110 			d-cache-line-size = <64>;
111 			d-cache-sets = <128>;
112 			next-level-cache = <&l2_1>;
115 		cpu6: cpu@102 {
116 			device_type = "cpu";
117 			compatible = "arm,cortex-a53";
118 			enable-method = "psci";
120 			cci-control-port = <&cci_control1>;
121 			i-cache-size = <32768>;
122 			i-cache-line-size = <64>;
123 			i-cache-sets = <256>;
124 			d-cache-size = <32768>;
125 			d-cache-line-size = <64>;
126 			d-cache-sets = <128>;
127 			next-level-cache = <&l2_1>;
130 		cpu7: cpu@103 {
131 			device_type = "cpu";
132 			compatible = "arm,cortex-a53";
133 			enable-method = "psci";
135 			cci-control-port = <&cci_control1>;
136 			i-cache-size = <32768>;
137 			i-cache-line-size = <64>;
138 			i-cache-sets = <256>;
139 			d-cache-size = <32768>;
140 			d-cache-line-size = <64>;
141 			d-cache-sets = <128>;
142 			next-level-cache = <&l2_1>;
145 		cpu-map {
148 					cpu = <&cpu0>;
152 					cpu = <&cpu1>;
156 					cpu = <&cpu2>;
160 					cpu = <&cpu3>;
166 					cpu = <&cpu4>;
170 					cpu = <&cpu5>;
174 					cpu = <&cpu6>;
178 					cpu = <&cpu7>;
183 		l2_0: l2-cache0 {
185 			cache-level = <2>;
186 			cache-size = <1048576>;
187 			cache-line-size = <64>;
188 			cache-sets = <1024>;
189 			cache-unified;
192 		l2_1: l2-cache1 {
194 			cache-level = <2>;
195 			cache-size = <1048576>;
196 			cache-line-size = <64>;
197 			cache-sets = <1024>;
198 			cache-unified;
202 	clk26m: oscillator-26m {
203 		compatible = "fixed-clock";
204 		#clock-cells = <0>;
205 		clock-frequency = <26000000>;
206 		clock-output-names = "clk26m";
209 	clk32k: oscillator-32k {
210 		compatible = "fixed-clock";
211 		#clock-cells = <0>;
212 		clock-frequency = <32000>;
213 		clock-output-names = "clk32k";
217 		compatible = "fixed-clock";
218 		clock-frequency = <13000000>;
219 		#clock-cells = <0>;
223 		compatible = "arm,cortex-a53-pmu";
228 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
232 		compatible = "arm,armv8-timer";
233 		interrupt-parent = <&gic>;
245 		#address-cells = <2>;
246 		#size-cells = <2>;
247 		compatible = "simple-bus";
251 			compatible = "mediatek,mt6795-topckgen", "syscon";
253 			#clock-cells = <1>;
257 			compatible = "mediatek,mt6795-infracfg", "syscon";
259 			#clock-cells = <1>;
260 			#reset-cells = <1>;
264 			compatible = "mediatek,mt6795-pericfg", "syscon";
266 			#clock-cells = <1>;
267 			#reset-cells = <1>;
271 			compatible = "syscon", "simple-mfd";
273 			#power-domain-cells = <1>;
275 			/* System Power Manager */
276 			spm: power-controller {
277 				compatible = "mediatek,mt6795-power-controller";
278 				#address-cells = <1>;
279 				#size-cells = <0>;
280 				#power-domain-cells = <1>;
282 				/* power domains of the SoC */
283 				power-domain@MT6795_POWER_DOMAIN_VDEC {
286 					clock-names = "mm";
287 					#power-domain-cells = <0>;
289 				power-domain@MT6795_POWER_DOMAIN_VENC {
293 					clock-names = "mm", "venc";
294 					#power-domain-cells = <0>;
296 				power-domain@MT6795_POWER_DOMAIN_ISP {
299 					clock-names = "mm";
300 					#power-domain-cells = <0>;
303 				power-domain@MT6795_POWER_DOMAIN_MM {
306 					clock-names = "mm";
307 					#power-domain-cells = <0>;
311 				power-domain@MT6795_POWER_DOMAIN_MJC {
315 					clock-names = "mm", "mjc";
316 					#power-domain-cells = <0>;
319 				power-domain@MT6795_POWER_DOMAIN_AUDIO {
321 					#power-domain-cells = <0>;
324 				mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC {
327 					clock-names = "mfg";
328 					#address-cells = <1>;
329 					#size-cells = <0>;
330 					#power-domain-cells = <1>;
332 					power-domain@MT6795_POWER_DOMAIN_MFG_2D {
334 						#address-cells = <1>;
335 						#size-cells = <0>;
336 						#power-domain-cells = <1>;
338 						power-domain@MT6795_POWER_DOMAIN_MFG {
340 							#power-domain-cells = <0>;
349 			compatible = "mediatek,mt6795-pinctrl";
351 			reg-names = "base", "eint";
354 			gpio-controller;
355 			#gpio-cells = <2>;
356 			gpio-ranges = <&pio 0 0 196>;
357 			interrupt-controller;
358 			#interrupt-cells = <2>;
362 			compatible = "mediatek,mt6795-wdt";
365 			#reset-cells = <1>;
366 			timeout-sec = <20>;
370 			compatible = "mediatek,mt6795-timer",
371 				     "mediatek,mt6577-timer";
378 			compatible = "mediatek,mt6795-pwrap";
380 			reg-names = "pwrap";
383 			reset-names = "pwrap";
385 			clock-names = "spi", "wrap";
388 		sysirq: intpol-controller@10200620 {
389 			compatible = "mediatek,mt6795-sysirq",
390 				     "mediatek,mt6577-sysirq";
391 			interrupt-controller;
392 			#interrupt-cells = <3>;
393 			interrupt-parent = <&gic>;
398 			compatible = "mediatek,mt6795-systimer";
402 			clock-names = "clk13m";
406 			compatible = "mediatek,mt6795-m4u";
409 			clock-names = "bclk";
412 			power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
413 			#iommu-cells = <1>;
417 			compatible = "mediatek,mt6795-apmixedsys", "syscon";
419 			#clock-cells = <1>;
422 		fhctl: clock-controller@10209f00 {
423 			compatible = "mediatek,mt6795-fhctl";
429 			compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce";
433 			clock-names = "gce";
434 			#mbox-cells = <2>;
437 		gic: interrupt-controller@10221000 {
438 			compatible = "arm,gic-400";
439 			#interrupt-cells = <3>;
440 			interrupt-parent = <&gic>;
441 			interrupt-controller;
451 			compatible = "arm,cci-400";
452 			#address-cells = <1>;
453 			#size-cells = <1>;
457 			cci_control0: slave-if@1000 {
458 				compatible = "arm,cci-400-ctrl-if";
459 				interface-type = "ace-lite";
463 			cci_control1: slave-if@4000 {
464 				compatible = "arm,cci-400-ctrl-if";
465 				interface-type = "ace";
469 			cci_control2: slave-if@5000 {
470 				compatible = "arm,cci-400-ctrl-if";
471 				interface-type = "ace";
476 				compatible = "arm,cci-400-pmu,r1";
487 			compatible = "mediatek,mt6795-uart",
488 				     "mediatek,mt6577-uart";
492 			clock-names = "baud", "bus";
494 			dma-names = "tx", "rx";
499 			compatible = "mediatek,mt6795-uart",
500 				     "mediatek,mt6577-uart";
504 			clock-names = "baud", "bus";
506 			dma-names = "tx", "rx";
510 		apdma: dma-controller@11000380 {
511 			compatible = "mediatek,mt6795-uart-dma",
512 				     "mediatek,mt6577-uart-dma";
529 			dma-requests = <8>;
531 			clock-names = "apdma";
532 			mediatek,dma-33bits;
533 			#dma-cells = <1>;
537 			compatible = "mediatek,mt6795-uart",
538 				     "mediatek,mt6577-uart";
542 			clock-names = "baud", "bus";
544 			dma-names = "tx", "rx";
549 			compatible = "mediatek,mt6795-uart",
550 				     "mediatek,mt6577-uart";
554 			clock-names = "baud", "bus";
556 			dma-names = "tx", "rx";
561 			compatible = "mediatek,mt6795-pwm";
563 			#pwm-cells = <2>;
574 			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
580 			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
583 			clock-div = <16>;
585 			clock-names = "main", "dma";
586 			#address-cells = <1>;
587 			#size-cells = <0>;
592 			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
595 			clock-div = <16>;
597 			clock-names = "main", "dma";
598 			#address-cells = <1>;
599 			#size-cells = <0>;
604 			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
607 			clock-div = <16>;
609 			clock-names = "main", "dma";
610 			#address-cells = <1>;
611 			#size-cells = <0>;
616 			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
619 			clock-div = <16>;
621 			clock-names = "main", "dma";
622 			#address-cells = <1>;
623 			#size-cells = <0>;
628 			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
631 			clock-div = <16>;
633 			clock-names = "main", "dma";
634 			#address-cells = <1>;
635 			#size-cells = <0>;
640 			compatible = "mediatek,mt6795-mmc";
646 			clock-names = "source", "hclk", "source_cg";
651 			compatible = "mediatek,mt6795-mmc";
656 			clock-names = "source", "hclk";
661 			compatible = "mediatek,mt6795-mmc";
666 			clock-names = "source", "hclk";
671 			compatible = "mediatek,mt6795-mmc";
676 			clock-names = "source", "hclk";
681 			compatible = "mediatek,mt6795-mmsys", "syscon";
683 			power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
684 			assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
685 			assigned-clock-rates = <400000000>;
686 			#clock-cells = <1>;
687 			#reset-cells = <1>;
690 			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
694 			compatible = "mediatek,mt6795-smi-larb";
697 			clock-names = "apb", "smi";
699 			mediatek,larb-id = <0>;
700 			power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
704 			compatible = "mediatek,mt6795-smi-common";
706 			power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
708 			clock-names = "apb", "smi";
712 			compatible = "mediatek,mt6795-smi-larb";
715 			clock-names = "apb", "smi";
717 			mediatek,larb-id = <2>;
718 			power-domains = <&spm MT6795_POWER_DOMAIN_ISP>;
721 		vdecsys: clock-controller@16000000 {
722 			compatible = "mediatek,mt6795-vdecsys";
724 			#clock-cells = <1>;
728 			compatible = "mediatek,mt6795-smi-larb";
731 			mediatek,larb-id = <1>;
733 			clock-names = "apb", "smi";
734 			power-domains = <&spm MT6795_POWER_DOMAIN_VDEC>;
737 		vencsys: clock-controller@18000000 {
738 			compatible = "mediatek,mt6795-vencsys";
740 			#clock-cells = <1>;
744 			compatible = "mediatek,mt6795-smi-larb";
747 			clock-names = "apb", "smi";
749 			mediatek,larb-id = <3>;
750 			power-domains = <&spm MT6795_POWER_DOMAIN_VENC>;